On the acquisition time for an Apollo ranging code.
Apollo ranging code with phase locked loop for bit synchronization, plotting SNR vs error probability and acquisition time
APOLLO PROJECT↗
SEARCH · Engineering Papers
Results for “phase locked loops”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Cooperative Inverters to Overcome PLL Malfunctions
This paper presents a cooperative strategy between smart inverters to overcome instability and undesired trips of inverters caused by Phase-Locked Loop (PLL) malfunctions. For the grid-interactive inverter, PLL is typically required to measure the phase angle of the AC voltage at the Point of Common Coupling (PCC) of the inverter. Accurate phase-angle measurement is critical for grid-interactive inverters to stay synchronized with the power grid. If the inverters are interconnected through a communication link, they can support each other by sharing their grid information, such as phase-angles at their PCCs. The cooperative strategy utilizes the phase-angles and voltages at PCCs in a neighborhood to identify any possible PLL malfunctions or measurement inaccuracies and then enable the inverters to make corrective decisions. The efficacy of the cooperative strategy has been verified through simulation results in MATLAB/Simulink environment in this paper.
Sadeque, Fahmid↗
A simulation analysis of phase processing circuitry in the Ohio University Omega receiver prototype
A FORTRAN IV simulation study of the all-digital phase-processing circuitry is described. A digital phase-lock loop (DPLL) forms the heart of the Omega navigation receiver prototype, and through the DPLL, the phase of the 10.2 KHz Omega signal was estimated when the true signal phase is contaminated with noise. The DPLL uses a frequency synthesizer as the reference oscillator. The synthesizer is composed of synchronous rate multipliers (SRM's) driven by a temperature-compensated crystal oscillator, and the use of the SRM's in this application introduces phase jitter which degrades system performance. Simulation of the frequency synthesizer discussed was to analyze the circuits on a bit-by-bit level in order to evaluate the overall design, to see easily the effects of proposed design changes prior to actual breadboarding, to determine the optimum integration time for the DPLL in an environment typical of general aviation conditions, and to quantify the phase error introduced by the SRM synthesizer and examine its effect on the system.
Palkovic, R. A.↗
The effects of sinusoidal interference on the second-order carrier tracking loop preceded by a bandpass limiter in the Block 4 receiver
Drop-lock relationships for the second-order phase-locked loop are derived when the carrier and a sinusoidal signal lie within the predetection filter bandwidth of the Block 4 receiver. Limiter suppression factors are calculated when a bandpass hard limiter is used to maintain constant total power at the loop. The parameters of interest are the interference-to-signal power ratio (ISR), the input signal-to-noise power ratio (NSR), and the interference signal frequency offset from carrier delta f. Limiter suppression caused by the combined effects of the noise and the interference signal accounts for the variability in the drop-lock threshold for given values of the input SNR and ISR parameters. Going beyond earlier published work that focused on the limiter's effect on the drop-lock threshold; an account is made for the limiter action in the interference mode and an overall imporvement is provided in the prediction accuracy of the drop-lock model.
Ruggier, C. J.↗
Programmable Oscillator
A programmable oscillator is a frequency synthesizer with an output phase that tracks an arbitrary function. An offset, phase-locked loop circuit is used in combination with an error control feedback loop to precisely control the output phase of the oscillator. To down-convert the received signal, several stages of mixing may be employed with the compensation for the time-base distortion of the carrier occurring at any one of those stages. In the Goldstone Solar System Radar (GSSR), the compensation occurs in the mixing from an intermediate frequency (IF), whose value is dependent on the station and band, to a common IF used in the final stage of down-conversion to baseband. The programmable oscillator (PO) is used in the final stage of down-conversion to generate the IF, along with a time-varying phase component that matches the time-base distortion of the carrier, thus removing it from the final down-converted signal.
Quirk, Kevin J.↗
Design and Performance of Sampled Data Loops for Subcarrier and Carrier Tracking
Design parameters and resulting performance are presented for the sampled data analogies of continuous time phase locked loops of second and third order containing perfect integrators. Expressions for noise equivalent bandwidth and steady state errors are given. Stability and gain margin are investigated using z plane root loci. Finally, an application is presented for Voyager subcarrier and carrier tracking under the dynamics of the encounters with Uranus and Neptune. For carrier tracking, loop bandwidth narrow enough for satisfactory loop signal to noise ratios can be achieved using third order loops without rate aiding, whereas second order loops would require aiding. For subcarrier tracking, third order loops can be used when the sampling rate is limited to approximately once per second, as in the Baseband Assembly, whereas second order loops sufficiently wide to track the dynamics have stability problems at that sampling rate.
Aguirre, S.↗
Data-aided carrier tracking loops
Power in composite signal sidebands is used to enhance signal-to-noise ratio in carrier tracking loop, thereby reducing radio loss and decreasing probability of receiver error. By adding quadrature channel to phase-lock-loop detector circuit of receiver, dc component can be fed back into carrier tracking loop.
Lindsey, W. C.↗
Computer program CORDET
A FORTRAN 4 computer program provides convenient simulation of an all-digital phase-lock loop (DPLL). The DPLL forms the heart of the Omega navigation receiver prototype. Through the DPLL, the phase of the 10.2 KHz Omega signal is estimated when the true signal phase is contaminated with noise. This investigation has provided a convenient means of evaluating loop performance in a variety of noise environments, and has proved to be a useful tool for evaluating design changes. The goals of the simulation are to: (1) analyze the circuit on a bit-by-bit level in order to evaluate the overall design; (2) see easily the effects of proposed design changes prior to actual breadboarding; and (3) determine the optimum integration time for the DPLL in an environment typical of general aviation conditions.
Palkovic, R. A.↗
Improved PLL For FM Demodulator
Phase-locked loop (PLL) for frequency demodulator contains improved frequency-to-voltage converter producing less ripple than conventional phase detector. In improved PLL, phase detector replaced by state estimator, implemented by ramp/sample-and-hold circuit. Intended to reduce noise in receiver of frequency-modulated (FM) telemetry link without sacrificing bandwidth. Also applicable to processing received FM signals.
Kirkham, Harold↗
Free-space laser communication technologies IV; Proceedings of the 4th Conference, Los Angeles, CA, Jan. 23, 24, 1992
Papers included in this volume are grouped under topics of receivers; laser transmitters; components; system analysis, performance, and applications; and beam control (pointing, acquisition, and tracking). Papers are presented on an experimental determination of power penalty contributions in an optical Costas-type phase-locked loop receiver, a resonant laser receiver for free-space laser communications, a simple low-loss technique for frequency-locking lasers, direct phase modulation of laser diodes, and a silex beacon. Particular attention is given to experimental results on an optical array antenna for nonmechanical beam steering, a potassium Faraday anomalous dispersion optical filter, a 100-Mbps resonant cavity phase modulator for coherent optical communications, a numerical simulation of a 325-Mbit/s QPPM optical communication system, design options for an optical multiple-access data relay terminal, CCD-based optical tracking loop design trades, and an analysis of a spatial-tracking subsystem for optical communications.
Begley, David L.↗
Open-loop digital frequency multiplier
Monostable multivibrator is implemented by using digital integrated circuits where multiplier constant is too large for conventional phase-locked-loop integrated circuit. A 400 Hz clock is generated by divide-by-N counter from 1 Hz timing reference.
Moore, R. C.↗
A proposed spacecraft-to-earth communications link - the unified carrier approach.
Unified carrier, range tracking and communications system using phase-locked loop techniques for coherent spacecraft-to-Earth communications
PHASE LOCK↗
Noninvasive Intracranial Volume and Pressure Measurements Using Ultrasound (Head and Spinal)
Prevention of secondary brain injuries following head trauma can be accomplished most easily when intracranial pressure (ICP) is monitored. However, current measurement techniques are invasive and thus not practical in the combat environment. The Pulsed Phase Lock Loop device, which was developed and patented by consultants Drs. Yost and Cantrell, uses a unique, noninvasive ultrasonic phase comparison method to measure slight changes in cranial volume which occur with changes in ICP. Year two studies included whole body head-up and head-down tilting effects on intracranial compliance and pressure in six healthy volunteers.
Hargens, Alan R.↗
Unsymmetrical QPSK demodulator
The present invention is a demodulator for demodulating an unsymmetrical QPSK signal (1), i.e., one in which the amplitudes of the I and Q channels are different, and the I and Q channels have been modulated by signals having differnt bit rates. Analog versions of the I and Q modulating baseband signals are first extracted from the carrier. Each baseband signal is then subjected to a bit-rate-matched low pass filter (23, 13). The channel having the higher bit rate is subjected to a delay (32) to time-align the two baseband signals. The time-aligned filtered signals are then amplified by amplifiers (22, 12) having unequal gains that are preselected to substantially equalize the amplifier (22, 12) outputs. The amplified time-aligned filtered signals are then subjected to a phase error (E) generating means (15, 25, 16, 26, 34). The phase error (E) is passed through a loop integrator (38) and a VCO (30) and back to the baseband signal extracting means to complete a phase lock loop. Frequency searching means (40), frequency lock detect means (42, 44), and AGC control ( 46, 8) are optionally present.
Guyer, Edward↗
Theoretical and experimental studies of sub-optimal second and third generation self-adaptive binary communication system Semiannual report, Jan. 1 - Jun. 30, 1966
Intersymbol interference in digital communication systems, phase lock loop studies, channel simulator studies, binary signal sets for channel models, and shift register sequences
CHANNEL↗
A class of Wiener filters useful in PLL APPLICATIONS.
Wiener filters in phase locked loop design, noting tracking function for orbital trajectory, derivation of optimum filter and noise bandwidth
MATHEMATICAL MODEL↗
Slot clock recovery in optical PPM communication systems with avalanche photodiode photodetectors
Slot timing recovery in a direct-detection optical PPM communication system can be achieved by processing the photodetector output waveform with a nonlinear device whose output forms the input to a phase-locked loop. The choice of a simple transition detector as the nonlinearity is shown to give satisfactory synchronization performance. The rms phase error of the recovered slot clock and the effect of slot timing jitter on the bit error probability were directly measured. The experimental system consisted of an AlGaAs laser diode (wavelength = 834 nm) and a silicon avalanche photodiode photodetector. The system used Q = 4 PPM signaling and operated at a source data rate of 25 Mbits/s. The mathematical model developed to compute the rms phase error of the recovered clock is shown to be in good agreement with results of actual measurements of phase errors. The use of the recovered slot clock in the receiver resulted in no significant degradation in receiver sensitivity compared to a system with perfect slot timing. The system achieved a bit error probability of 10 to the -6th at a received optical signal energy of 55 detected photons per information bit.
Davidson, Frederic M.↗
An Ultra-Fast Inrush-Current-Free Startup Method for Grid-tie Inverter without Voltage Sensors
This paper proposes an ultra-fast inrush-currentfree startup method for grid-tie inverters without voltage sensors and phase-locked loop (PLL). Traditionally, the grid-tie inverter needs the voltage measured from points of common couplings (PCC) to generate the phase angle via PLL for inverter pulsewidth- modulation (PWM) signals. The startup procedure is slow and inrush current occurs if the initial PWM does not match the unknown grid voltage well. This paper proposes a startup method that only uses measured inverter ac currents to generate the initial PWM by controlling the current to zero. The generated PWM pattern can be used to reproduce the real grid voltage regardless of the grid impedance. The zero-crossing points of the grid voltage are detected and then used for grid synchronization. The proposed startup procedure only needs a few cycles (16.67 ms/cycle) to reliably synchronize the inverter to the grid without any inrush current. Simulation and experimental results are presented to verify the effectiveness of this control strategy.
He, Yuchen↗