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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 325 records · Page 18
All sourcesNASA NTRSDOE OSTI
NASA NTRS1972

Multi-processing system study

The results are summarized of a multiprocessor systems design review. The systems were reviewed against use in a space station environment. The proposed designs were evaluated from a systems viewpoint in general and from the systems software in particular. The recommendations resulting from this evaluation are anticipated to be considered for the design of a multiprocessing system built around a SUMC. Two multiprocessing system designs were reviewed. The designs reviewed were highly functional and many questions could not be answered. However, several major issues were uncovered which could be evaluated to some detail, and which could greatly impact the SUMC-MP design. The major issues relevant to a multiprocessing system design revolve around the following functions: (1) Storage Management, (2) Processor Management, (3) Intermodule Communication, (4) Memory Access Interference, (5) System Efficiency, and (6) System Recovery/Reliability.

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NASA NTRS1973

Optimum spaceborne computer system design by simulation

A deterministic simulator is described which models the Automatically Reconfigurable Modular Multiprocessor System (ARMMS), a candidate computer system for future manned and unmanned space missions. Its use as a tool to study and determine the minimum computer system configuration necessary to satisfy the on-board computational requirements of a typical mission is presented. The paper describes how the computer system configuration is determined in order to satisfy the data processing demand of the various shuttle booster subsytems. The configuration which is developed as a result of studies with the simulator is optimal with respect to the efficient use of computer system resources.

Williams, T.↗
NASA NTRS1972

Information management system breadboard data acquisition and control system.

Description of a breadboard configuration of an advanced information management system based on requirements for high data rates and local and centralized computation for subsystems and experiments to be housed on a space station. The system is to contain a 10-megabit-per-second digital data bus, remote terminals with preprocessor capabilities, and a central multiprocessor. A concept definition is presented for the data acquisition and control system breadboard, and a detailed account is given of the operation of the bus control unit, the bus itself, and the remote acquisition and control unit. The data bus control unit is capable of operating under control of both its own test panel and the test processor. In either mode it is capable of both single- and multiple-message operation in that it can accept a block of data requests or update commands for transmission to the remote acquisition and control unit, which in turn is capable of three levels of data-handling complexity.

Mallary, W. E.↗
NASA NTRS1974

Modular digital computer system design

Automatically-Reconfigurable Modular Multiprocessor System (ARMMS) provides redundant processing with dynamic mode switching in real time. Design will provide higher computer capability than that presently available for same amount of hardware and will furnish modular system which is responsive to diverse problems effectively.

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NASA NTRS1972

Design of a modular digital computer system, DRL 4

The design is reported of an advanced modular computer system designated the Automatically Reconfigurable Modular Multiprocessor System, which anticipates requirements for higher computing capacity and reliability for future spaceborne computers. Subjects discussed include: an overview of the architecture, mission analysis, synchronous and nonsynchronous scheduling control, reliability, and data transmission.

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NASA NTRS1973

Design of a fault tolerant airborne digital computer. Volume 1: Architecture

This volume is concerned with the architecture of a fault tolerant digital computer for an advanced commercial aircraft. All of the computations of the aircraft, including those presently carried out by analogue techniques, are to be carried out in this digital computer. Among the important qualities of the computer are the following: (1) The capacity is to be matched to the aircraft environment. (2) The reliability is to be selectively matched to the criticality and deadline requirements of each of the computations. (3) The system is to be readily expandable. contractible, and (4) The design is to appropriate to post 1975 technology. Three candidate architectures are discussed and assessed in terms of the above qualities. Of the three candidates, a newly conceived architecture, Software Implemented Fault Tolerance (SIFT), provides the best match to the above qualities. In addition SIFT is particularly simple and believable. The other candidates, Bus Checker System (BUCS), also newly conceived in this project, and the Hopkins multiprocessor are potentially more efficient than SIFT in the use of redundancy, but otherwise are not as attractive.

Wensley, J. H.↗
NASA NTRS1975

Systems analysis of the space shuttle

Developments in communications systems, computer systems, and power distribution systems for the space shuttle are described. The use of high speed delta modulation for bit rate compression in the transmission of television signals is discussed. Simultaneous Multiprocessor Organization, an approach to computer organization, is presented. Methods of computer simulation and automatic malfunction detection for the shuttle power distribution system are also described.

Schilling, D. L.↗
NASA NTRS1975

Feasibility study for the implementation of NASTRAN on the ILLIAC 4 parallel processor

The ILLIAC IV, a fourth generation multiprocessor using parallel processing hardware concepts, is operational at Moffett Field, California. Its capability to excel at matrix manipulation, makes the ILLIAC well suited for performing structural analyses using the finite element displacement method. The feasibility of modifying the NASTRAN (NASA structural analysis) computer program to make effective use of the ILLIAC IV was investigated. The characteristics are summarized of the ILLIAC and the ARPANET, a telecommunications network which spans the continent making the ILLIAC accessible to nearly all major industrial centers in the United States. Two distinct approaches are studied: retaining NASTRAN as it now operates on many of the host computers of the ARPANET to process the input and output while using the ILLIAC only for the major computational tasks, and installing NASTRAN to operate entirely in the ILLIAC environment. Though both alternatives offer similar and significant increases in computational speed over modern third generation processors, the full installation of NASTRAN on the ILLIAC is recommended. Specifications are presented for performing that task with manpower estimates and schedules to correspond.

Field, E. I.↗
NASA NTRS1974

Research in the Aloha system

The Aloha system was studied and developed and extended to advanced forms of computer communications networks. Theoretical and simulation studies of Aloha type radio channels for use in packet switched communications networks were performed. Improved versions of the Aloha communications techniques and their extensions were tested experimentally. A packet radio repeater suitable for use with the Aloha system operational network was developed. General studies of the organization of multiprocessor systems centered on the development of the BCC 500 computer were concluded.

Abramson, N.↗
NASA NTRS1975

Interactive image processing for meteorological applications at NASA/Goddard Space Flight Center

The meteorological data processing program at the space center is centered on the analysis of geostationary satellite data. Its objectives are to detect and predict severe storms, to improve short range and long range global numerical weather forecasting models, and to develop improved satellite systems. The Image Display and Manipulation System (IDAMS) for earth resources satellite data processing is described, as is the special purpose software package, METPAK, for performing meteorology operations on IDAMS. The Atmospheric and Oceanographic Information Processing System (AOIPS), a dual terminal multiprocessor is also described.

Billingsley, J. B.↗
NASA NTRS1976

Higher order software - A methodology for defining software

Higher order software (HOS) is concerned only with computable functions and relationships. The HOS methodology can be used for the definition of software for multiprogrammed, multiprocessor, or multicomputer systems. A description of HOS methodology is presented, giving attention to questions of formulation, interface correctness, specification language principles, and HOS analyzers. Aspects of system design are considered, and details of software management are discussed. Attention is given to modularity as defined by HOS, frozen module management, the assembly control supervisor, and aspects of reliability and efficiency.

Hamilton, M.↗
NASA NTRS1979

A method for classifying multispectral remote sensing data using context

The paper describes a method of classifying multispectral remote sensing data using a context classifier. Because the computational requirements of the context classifier are very large, its implementation on parallel/pipelined multiprocessor systems is being investigated, so that the types of computations can be efficiently implemented. Special considerations necessary for such implementations are discussed, with particular reference to implementation on an array of Control Data Corporation Flexible Processors.

Swain, P. H.↗
NASA NTRS1981

Measurement of fault latency in a digital avionic miniprocessor

The results of fault injection experiments utilizing a gate-level emulation of the central processor unit of the Bendix BDX-930 digital computer are presented. The failure detection coverage of comparison-monitoring and a typical avionics CPU self-test program was determined. The specific tasks and experiments included: (1) inject randomly selected gate-level and pin-level faults and emulate six software programs using comparison-monitoring to detect the faults; (2) based upon the derived empirical data develop and validate a model of fault latency that will forecast a software program's detecting ability; (3) given a typical avionics self-test program, inject randomly selected faults at both the gate-level and pin-level and determine the proportion of faults detected; (4) determine why faults were undetected; (5) recommend how the emulation can be extended to multiprocessor systems such as SIFT; and (6) determine the proportion of faults detected by a uniprocessor BIT (built-in-test) irrespective of self-test.

Mcgough, J. G.↗
NASA NTRS1982

The P-POD Project

The programmable pilot oriented display (P-POD), a multiprocessor based flight information processing and display unit, is discussed. Communication protocols between the three Z-80 processors inside P-POD are reviewed. The interface between the video processor, P2, and the main processor, P1, was tested. Hardware and software were revised. Data flow between P1 and P2 is illustrated. While running diagnostic routines to exercise the P1/P2 interface at maximum speed an intermittent failure was observed. A check of possible noise sources or race conditions in the hardware did not reveal the source of this failure. Possible software timing problems were also fully investigated. To eliminate the effects of this type of failure a performance monitor routine was used to detect these occasional failures and correct them. The data transmission cycle between P1/P2 is either allowed to continue normal operation or is re-initialized and restarted when an error is detected.

Littlefield, J. A.↗
NASA NTRS1982

Problems related to the integration of fault tolerant aircraft electronic systems

Problems related to the design of the hardware for an integrated aircraft electronic system are considered. Taxonomies of concurrent systems are reviewed and a new taxonomy is proposed. An informal methodology intended to identify feasible regions of the taxonomic design space is described. Specific tools are recommended for use in the methodology. Based on the methodology, a preliminary strawman integrated fault tolerant aircraft electronic system is proposed. Next, problems related to the programming and control of inegrated aircraft electronic systems are discussed. Issues of system resource management, including the scheduling and allocation of real time periodic tasks in a multiprocessor environment, are treated in detail. The role of software design in integrated fault tolerant aircraft electronic systems is discussed. Conclusions and recommendations for further work are included.

Bannister, J. A.↗
NASA NTRS1983

Testing the bus guardian unit of the FTMP

Fault-tolerant multiprocessor (FTMP) operation is discussed. Fault-modeling in the bus guardian units (BGUs) is covered. Testing the BGU is discussed. A testing algorithm is proposed.

Jha, M. K.↗
NASA NTRS1982

Models for evaluating the performability of degradable computing systems

Recent advances in multiprocessor technology established the need for unified methods to evaluate computing systems performance and reliability. In response to this modeling need, a general modeling framework that permits the modeling, analysis and evaluation of degradable computing systems is considered. Within this framework, several user oriented performance variables are identified and shown to be proper generalizations of the traditional notions of system performance and reliability. Furthermore, a time varying version of the model is developed to generalize the traditional fault tree reliability evaluation methods of phased missions.

Wu, L. T.↗
NASA NTRS1983

Design of a high-speed digital processing element for parallel simulation

A prototype of a custom designed computer to be used as a processing element in a multiprocessor based jet engine simulator is described. The purpose of the custom design was to give the computer the speed and versatility required to simulate a jet engine in real time. Real time simulations are needed for closed loop testing of digital electronic engine controls. The prototype computer has a microcycle time of 133 nanoseconds. This speed was achieved by: prefetching the next instruction while the current one is executing, transporting data using high speed data busses, and using state of the art components such as a very large scale integration (VLSI) multiplier. Included are discussions of processing element requirements, design philosophy, the architecture of the custom designed processing element, the comprehensive instruction set, the diagnostic support software, and the development status of the custom design.

Milner, E. J.↗