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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 325 records · Page 18
All sourcesNASA NTRSDOE OSTI
DOE OSTI2014

Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests

A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2015

Shape memory polymers

New shape memory polymer compositions, methods for synthesizing new shape memory polymers, and apparatus comprising an actuator and a shape memory polymer wherein the shape memory polymer comprises at least a portion of the actuator. A shape memory polymer comprising a polymer composition which physically forms a network structure wherein the polymer composition has shape-memory behavior and can be formed into a permanent primary shape, re-formed into a stable secondary shape, and controllably actuated to recover the permanent primary shape. Polymers have optimal aliphatic network structures due to minimization of dangling chains by using monomers that are symmetrical and that have matching amine and hydroxyl groups providing polymers and polymer foams with clarity, tight (narrow temperature range) single transitions, and high shape recovery and recovery force that are especially useful for implanting in the human body.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Evaluation methodology for comparing memory and communication of analytic processes in visual analytics

Provenance tools can help capture and represent the history of analytic processes. In addition to supporting analytic performance, provenance tools can be used to support memory of the process and communication of the steps to others. Objective evaluation methods are needed to evaluate how well provenance tools support analyst s memory and communication of analytic processes. In this paper, we present several methods for the evaluation of process memory, and we discuss the advantages and limitations of each. We discuss methods for determining a baseline process for comparison, and we describe various methods that can be used to elicit process recall, step ordering, and time estimations. Additionally, we discuss methods for conducting quantitative and qualitative analyses of process memory. By organizing possible memory evaluation methods and providing a meta-analysis of the potential benefits and drawbacks of different approaches, this paper can inform study design and encourage objective evaluation of process memory and communication.

Ragan, Eric D↗
DOE OSTI2015

Memory Scalability and Efficiency Analysis of Parallel Codes

Memory scalability is an enduring problem and bottleneck that plagues many parallel codes. Parallel codes designed for High Performance Systems are typically designed over the span of several, and in some instances 10+, years. As a result, optimization practices which were appropriate for earlier systems may no longer be valid and thus require careful optimization consideration. Specifically, parallel codes whose memory footprint is a function of their scalability must be carefully considered for future exa-scale systems. In this paper we present a methodology and tool to study the memory scalability of parallel codes. Using our methodology we evaluate an application s memory footprint as a function of scalability, which we coined memory efficiency, and describe our results. In particular, using our in-house tools we can pinpoint the specific application components which contribute to the application s overall memory foot-print (application data- structures, libraries, etc.).

Janjusic, Tommy↗
DOE OSTI2016

Silent store detection and recording in memory storage

An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Silent store detection and recording in memory storage

An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Silent store detection and recording in memory storage

An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Silent store detection and recording in memory storage

An aspect includes receiving a write request that includes a memory address and write data. Stored data is read from a memory location at the memory address. Based on determining that the memory location was not previously modified, the stored data is compared to the write data. Based on the stored data matching the write data, the write request is completed without writing the write data to the memory and a corresponding silent store bit, in a silent store bitmap is set. Based on the stored data not matching the write data, the write data is written to the memory location, the silent store bit is reset and a corresponding modified bit is set. At least one of an application and an operating system is provided access to the silent store bitmap.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Shape memory polymers

New shape memory polymer compositions, methods for synthesizing new shape memory polymers, and apparatus comprising an actuator and a shape memory polymer wherein the shape memory polymer comprises at least a portion of the actuator. A shape memory polymer comprising a polymer composition which physically forms a network structure wherein the polymer composition has shape-memory behavior and can be formed into a permanent primary shape, re-formed into a stable secondary shape, and controllably actuated to recover the permanent primary shape. Polymers have optimal aliphatic network structures due to minimization of dangling chains by using monomers that are symmetrical and that have matching amine and hydroxl groups providing polymers and polymer foams with clarity, tight (narrow temperature range) single transitions, and high shape recovery and recovery force that are especially useful for implanting in the human body.

36 MATERIALS SCIENCE↗
DOE OSTI2018

DRAGON: breaking GPU memory capacity limits with direct NVM access

Heterogeneous computing with accelerators is growing in importance in high performance computing (HPC). Recently, application datasets have expanded beyond the memory capacity of these accelerators, and often beyond the capacity of their hosts. Meanwhile, nonvolatile memory (NVM) storage has emerged as a pervasive component in HPC systems because NVM provides massive amounts of memory capacity at affordable cost. Currently, for accelerator applications to use NVM, they must manually orchestrate data movement across multiple memories and this approach only performs well for applications with simple access behaviors. To address this issue, we developed DRAGON, a solution that enables all classes of GP-GPU applications to transparently compute on terabyte datasets residing in NVM. DRAGON leverages the page-faulting mechanism on the recent NVIDIA GPUs by extending capabilities of CUDA Unified Memory (UM). Our experimental results show that DRAGON transparently expands memory capacity and obtain additional speedups via automated I/O and data transfer overlapping.

Markthub, Pak↗
DOE OSTI2019

Per-page control of physical address space distribution among memory modules

Systems, apparatuses, and methods for implementing per-page control of physical address space distribution among memory modules are disclosed. A computing system includes a plurality of processing units coupled to a plurality of memory modules. A determination is made as to which physical address space distribution granularity to implement for physical memory pages allocated for a first data structure. The determination can be made on a per-data-structure basis (e.g., file, page, block, etc.) or on a per-application-basis. A physical address space distribution granularity is encoded as a property of each physical memory page allocated for the first data structure, and physical memory pages of the first data structure distributed across the plurality of memory modules based on a selected physical address space distribution granularity. Page table entries (PTEs) may be annotated with the selected physical address space distribution granularity, using an addressing mapping granularity (AMG) field of a page table entry, where the granularity may be, for example, a fine-grain distribution granularity or a coarse-grain distribution granularity.

Jayasena, Nuwan S.↗
DOE OSTI2019

Single instruction multiple data page table walk scheduling at input output memory management unit

A data processing system includes a memory and an input output memory management unit that is connected to the memory. The input output memory management unit is adapted to receive batches of address translation requests. The input output memory management unit has instructions that identify, from among the batches of address translation requests, a later batch having a lower number of memory access requests than an earlier batch, and selectively schedules access to a page table walker for each address translation request of a batch.

Basu, Arkaprava↗
DOE OSTI2019

Cache coherence for processing in memory

A cache coherence bridge protocol provides an interface between a cache coherence protocol of a host processor and a cache coherence protocol of a processor-in-memory, thereby decoupling coherence mechanisms of the host processor and the processor-in-memory. The cache coherence bridge protocol requires limited change to existing host processor cache coherence protocols. The cache coherence bridge protocol may be used to facilitate interoperability between host processors and processor-in-memory devices designed by different vendors and both the host processors and processor-in-memory devices may implement coherence techniques among computing units within each processor. The cache coherence bridge protocol may support different granularity of cache coherence permissions than those used by cache coherence protocols of a host processor and/or a processor-in-memory. The cache coherence bridge protocol uses a shadow directory that maintains status information indicating an aggregate view of copies of data cached in a system external to a processor-in-memory containing that data.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Memory access system

A method and system for accessing a memory for a data processing system. The method comprises sending a read request for a plurality of locations in the memory to read the plurality of locations in parallel based on an upper bound for reading the memory. The upper bound for a number of locations is based on a group of constraints for the memory. The method receives a summed value of a plurality of memory values in the plurality of locations in the memory.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Bit error protection in cache memories

A computing device having a cache memory that is configured in a write-back mode is described. A cache controller in the cache memory acquires, from a record of bit errors that are present in each of a plurality of portions of the cache memory, a number of bit errors in a portion of the cache memory. The cache controller detects a coherency state of data stored in the portion of the cache memory. Based on the coherency state and the number of bit errors, the cache controller selects an error protection from among a plurality of error protections. The cache controller uses the selected error protection to protect the data stored in the portion of the cache memory from errors.

Kalamatianos, John↗
DOE OSTI2022

Ballistic reversible superconducting memory element

A reversible memory element is provided. The reversible memory element comprises a reversible memory cell comprising a Josephson junction and a passive inductor. A ballistic interconnect is connected to the reversible memory cell by a bidirectional input/output port. A polarized input fluxon propagating along the ballistic interconnect exchanges polarity with a stationary stored fluxon in the reversible memory cell in response to the input fluxon reflecting off the reversible memory cell.

Frank, Michael P.↗
DOE OSTI2022

Shape memory polymers

New shape memory polymer compositions, methods for synthesizing new shape memory polymers, and apparatus comprising an actuator and a shape memory polymer wherein the shape memory polymer comprises at least a portion of the actuator. A shape memory polymer comprising a polymer composition which physically forms a network structure wherein the polymer composition has shape-memory behavior and can be formed into a permanent primary shape, re-formed into a stable secondary shape, and controllably actuated to recover the permanent primary shape. Polymers have optimal aliphatic network structures due to minimization of dangling chains by using monomers that are symmetrical and that have matching amine and hydroxl groups providing polymers and polymer foams with clarity, tight (narrow temperature range) single transitions, and high shape recovery and recovery force that are especially useful for implanting in the human body.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2023

Shape memory polymers

New shape memory polymer compositions, methods for synthesizing new shape memory polymers, and apparatus comprising an actuator and a shape memory polymer wherein the shape memory polymer comprises at least a portion of the actuator. A shape memory polymer comprising a polymer composition which physically forms a network structure wherein the polymer composition has shape-memory behavior and can be formed into a permanent primary shape, re-formed into a stable secondary shape, and controllably actuated to recover the permanent primary shape. Polymers have optimal aliphatic network structures due to minimization of dangling chains by using monomers that are symmetrical and that have matching amine and hydroxl groups providing polymers and polymer foams with clarity, tight (narrow temperature range) single transitions, and high shape recovery and recovery force that are especially useful for implanting in the human body.

Wilson, Thomas S.↗