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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 325 records · Page 18
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Distributed Outage Detection in Power Distribution Networks

Real time topology knowledge is essential for situational awareness of power distribution networks. Line outages change the topology of a distribution network. Hence, outage detection is an important task. Most of the existing outage detection algorithms are centralized, in which sensors communicate their data to a control center which performs outage detection using the received data. However, with the increasing size of the distribution network and with different areas of the network being monitored by different operators, communication is a bottleneck and scalability is a major concern. To address these issues, we propose a novel outage detection algorithm using a divide and conquer approach. First, we divide a distribution network into sub-networks, such that outage detection can be run in parallel in each sub-network independently ensuring scalability to large networks. Further, to reduce the latency, bandwidth and attenuation challenges associated with communications in a large network, we divide each sub-network into multiple control areas which communicate only with their neighbors. We employ a distributed iterative load estimation across the control areas of each sub-network and then use the load estimate for local outage detection in each control area. Here, the performance of our algorithm is evaluated for multiple feeder models and compared against traditional centralized outage detection algorithms.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗
DOE OSTI2025

Synchro-Waveform-Based Event Identification Using Multi-Task Time-Frequency Transform Networks

Influenced by the transient dynamics and reduced inertia characteristics of high-penetration renewable energy systems, power system events frequently exhibit distinct characteristics such as high-frequency components including wide-band oscillations and hyper-harmonics. This makes standard systems face challenges including significant latency and reduced accuracy due to limited data resolution. However, current methods face significant limitations, including insufficient pattern capture ability, low noise immunity, limited feature learning, and restricted localization capabilities, thereby hindering real-time performance. To tackle this issue, this paper proposed a novel synchro-waveform-based event identification approach via a Multi-task Time-frequency Transform Network (MTTNet). Initially, a Time-frequency Transform Block (TTB) is developed to extract both local and global information. The TTB leverages both Fourier and S-transforms to derive comprehensive time-frequency information from synchro-waveforms. Subsequently, a multi-task learning strategy is employed to identify the type and distinguish localization of events. Integrating the TTB and multi-task learning, the MTTNet is designed for synchro-waveform-based event identification, incorporating an adaptive weighting strategy and simplified computation for the S-transform. Two different datasets, comprising simulated and actual synchro-waveforms, are collected from the IEEE 123 bus system and a real-world high-penetration renewable energy system using a universal grid analyzer. Extensive experiments on various conditions are carried out. In conclusion, results demonstrated that the MTTNet consistently surpasses both basic and advanced baselines, with maximum improvements of 13.24% and 9.86%, respectively, while reducing the calculation burden by 15-19 times to achieve real-time event identification.

Event identification↗
DOE OSTI2021

Stochastic Gradient-Based Distributed Bayesian Estimation in Cooperative Sensor Networks

Distributed Bayesian inference provides a full quantification of uncertainty offering numerous advantages over point estimates that autonomous sensor networks are able to exploit. However, fully-decentralized Bayesian inference often requires large communication overheads and low network latency, resources that are not typically available in practical applications. In this paper, we propose a decentralized Bayesian inference approach based on stochastic gradient Langevin dynamics, which produces full posterior distributions at each of the nodes with significantly lower communication overhead. We provide analytical results on convergence of the proposed distributed algorithm to the centralized posterior, under typical network constraints. Finally, we also provide extensive simulation results to demonstrate the validity of the proposed approach.

42 ENGINEERING↗
DOE OSTI2024

Exploring Enhanced Dominant Resource Fairness Using Linear Programming Calculated Weights

Maintaining resource fairness while achieving optimization for various performance metrics such as resource utilization, turnaround time and job latency is a well-known resource scheduling challenge in cloud computing. Despite the significant progress made with the introduction of dominant resource fairness by Ghodsi et al., which ensures major allocation properties such as sharing incentive, strategy-proofness, envy-freeness and Pareto efficiency to be achieved

Yan, Bo [Binghamton University]↗
DOE OSTI2024

Reliable edge machine learning hardware for scientific applications

Extreme data rate scientific experiments create massive amounts of data that require efficient ML edge processing. This leads to unique validation challenges for VLSI implementations of ML algorithms: enabling bit-accurate functional simulations for performance validation in experimental software frameworks, verifying those ML models are robust under extreme quantization and pruning, and enabling ultra-fine-grained model inspection for efficient fault tolerance. We discuss approaches to developing and validating reliable algorithms at the scientific edge under such strict latency, resource, power, and area requirements in extreme experimental environments. We study metrics for developing robust algorithms, present preliminary results and mitigation strategies, and conclude with an outlook of these and future directions of research towards the longer-term goal of developing autonomous scientific experimentation methods for accelerated scientific discovery.

Baldi, Tommaso↗
DOE OSTI2024

Rev1 overexpression accelerates N -methyl- N -nitrosourea (MNU)-induced thymic lymphoma by increasing mutagenesis

Rev1 has two important functions in the translesion synthesis pathway, including dCMP transferase activity, and acts as a scaffolding protein for other polymerases involved in translesion synthesis. However, the role of Rev1 in mutagenesis and tumorigenesis in vivo remains unclear. We previously generated Rev1-overexpressing (Rev1-Tg) mice and reported that they exhibited a significantly increased incidence of intestinal adenoma and thymic lymphoma (TL) after N-methyl-N-nitrosourea (MNU) treatment. In this study, we investigated mutagenesis of MNU-induced TL tumorigenesis in wild-type (WT) and Rev1-Tg mice using diverse approaches, including whole-exome sequencing (WES). In Rev1-Tg TLs, the mutation frequency was higher than that in WT TL in most cases. However, no difference in the number of nonsynonymous mutations in the Catalogue of Somatic Mutations in Cancer (COSMIC) genes was observed, and mutations involved in Notch1 and MAPK signaling were similarly detected in both TLs. Mutational signature analysis of WT and Rev1-Tg TLs revealed cosine similarity with COSMIC mutational SBS5 (aging-related) and SBS11 (alkylation-related). Interestingly, the total number of mutations, but not the genotypes of WT and Rev1-Tg, was positively correlated with the relative contribution of SBS5 in individual TLs, suggesting that genetic instability could be accelerated in Rev1-Tg TLs. Finally, we demonstrated that preleukemic cells could be detected earlier in Rev1-Tg mice than in WT mice, following MNU treatment. In conclusion, Rev1 overexpression accelerates mutagenesis and increases the incidence of MNU-induced TL by shortening the latency period, which may be associated with more frequent DNA damage-induced genetic instability.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2021

SQL and NoSQL Databases for Cyber Physical Production Systems in Internet of Things for Manufacturing (IoTfM)

Abstract In this paper, the design and performance differences between Relational Database Management Systems (RDBMS) and NoSQL Database Systems are examined, with attention to their applicability for real-world Internet of Things for manufacturing (IoTfM) data. While previous work has extensively compared SQL and NoSQL for both generalized and IoT uses, this work specifically examines the tradeoffs and performance differences for manufacturing applications by using a high-fidelity data set collected from a large US manufacturing firm. Growing an IoT system beyond the pilot stage requires scalable data storage; this work seeks to determine the impact of selected database systems on data write performance at scale. Payload size and message frequency were used as the primary characteristics to maintain model fidelity in simulated clients. As the number of simulated asset clients grow, the data write latency was calculated to determine how both database systems’ performance were affected. To isolate the RDBMS and NoSQL differences, a cloud environment was created using Amazon Web Services (AWS) with two identical data ingestion pipelines: writing data to an RDMBS (1) using AWS Aurora MySQL, and (2) using AWS DynamoDB NoSQL. The findings may provide guidance for further experimentation in large-scale manufacturing IoT implementations.

Gamero, David↗
DOE OSTI2024

Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines

Field programmable gate array (FPGA) is widely used in the acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the trade-off between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. Here, we propose a ferroelectric field-effect transistor (FeFET)–based context-switching FPGA supporting dynamic reconfiguration to break this trade-off, enabling loading of arbitrary configuration without interrupting the active configuration execution. Leveraging the intrinsic structure and nonvolatility of FeFETs, compact FPGA primitives are proposed and experimentally verified. The evaluation results show our design shows a 63.0%/74.7% reduction in a look-up table (LUT)/connection block (CB) area and 82.7%/53.6% reduction in CB/switch box power consumption with a minimal penalty in the critical path delay (9.6%). Besides, our design yields significant time savings by 78.7 and 20.3% on average for context-switching and dynamic reconfiguration applications, respectively.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Scalable Asynchronous Domain Decomposition Solvers

We discuss how parallel implementations of linear iterative solvers generally alternate between phases of data exchange and phases of local computation. Increasingly large problem sizes and more heterogeneous compute architectures make load balancing and the design of low latency network interconnects that are able to satisfy the communication requirements of linear solvers very challenging tasks. In particular, global communication patterns such as inner products become increasingly limiting at scale. We explore the use of asynchronous communication based on one-sided Message Passing Interface primitives in the context of domain decomposition solvers. In particular, a scalable asynchronous two-level Schwarz method is presented. We discuss practical issues encountered in the development of a scalable solver and show experimental results obtained on a state-of-the-art supercomputer system that illustrate the benefits of asynchronous solvers in load balanced as well as load imbalanced scenarios. Using the novel method, we can observe speedups of up to four times over its classical synchronous equivalent.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Soft syndrome iterative decoding of quantum LDPC codes and hardware architectures

In practical quantum error correction implementations, the measurement of syndrome information is an unreliable step—typically modeled as a binary measurement outcome flipped with some probability. However, the measured syndrome is in fact a discretized value of the continuous voltage or current values obtained in the physical implementation of the syndrome extraction. In this paper, we use this “soft” or analog information to benefit iterative decoders for decoding quantum low-density parity-check (QLDPC) codes. Syndrome-based iterative belief propagation decoders are modified to utilize the soft syndrome to correct both data and syndrome errors simultaneously. We demonstrate the advantages of the proposed scheme not only in terms of comparison of thresholds and logical error rates for quasi-cyclic lifted-product QLDPC code families but also with faster convergence of iterative decoders. Additionally, we derive hardware (FPGA) architectures of these soft syndrome decoders and obtain similar performance in terms of error correction to the ideal models even with reduced precision in the soft information. The total latency of the hardware architectures is about 600 ns (for the QLDPC codes considered) in a 20 nm CMOS process FPGA device, and the area overhead is almost constant—less than 50% compared to min-sum decoders with noisy syndromes.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2020

A massively parallel and scalable multi-CPU material point method

Harnessing the power of modern multi-GPU architectures, we present a massively parallel simulation system based on the Material Point Method (MPM) for simulating physical behaviors of materials undergoing complex topological changes, self-collision, and large deformations. Our system makes three critical contributions. First, we introduce a new particle data structure that promotes coalesced memory access patterns on the GPU and eliminates the need for complex atomic operations on the memory hierarchy when writing particle data to the grid. Second, we propose a kernel fusion approach using a new Grid-to-Particles-to-Grid (G2P2G) scheme, which efficiently reduces GPU kernel launches, improves latency, and significantly reduces the amount of global memory needed to store particle data. Finally, we introduce optimized algorithmic designs that allow for efficient sparse grids in a shared memory context, enabling us to best utilize modern multi-GPU computational platforms for hybrid Lagrangian-Eulerian computational patterns. We demonstrate the effectiveness of our method with extensive benchmarks, evaluations, and dynamic simulations with elastoplasticity, granular media, and fluid dynamics. In comparisons against an open-source and heavily optimized CPU-based MPM codebase [Fang et al. 2019] on an elastic sphere colliding scene with particle counts ranging from 5 to 40 million, our GPU MPM achieves over 100x per-time-step speedup on a workstation with an Intel 8086K CPU and a single Quadro P6000 GPU, exposing exciting possibilities for future MPM simulations in computer graphics and computational science. Moreover, compared to the state-of-the-art GPU MPM method [Hu et al. 2019a], we not only achieve 2x acceleration on a single GPU but our kernel fusion strategy and Array-of-Structs-of-Array (AoSoA) data structure design also generalizes to multi-GPU systems. Our multi-GPU MPM exhibits near-perfect weak and strong scaling with 4 GPUs, enabling performant and large-scale simulations on a 10243 grid with close to 100 million particles with less than 4 minutes per frame on a single 4-GPU workstation and 134 million particles with less than 1 minute per frame on an 8-GPU workstation.

Wang, Xinlei↗
DOE OSTI2021

Strong and Efficient Consistency with Consistency-aware Durability

We introduce consistency-aware durability or C ad , a new approach to durability in distributed storage that enables strong consistency while delivering high performance. We demonstrate the efficacy of this approach by designing cross-client monotonic reads , a novel and strong consistency property that provides monotonic reads across failures and sessions in leader-based systems; such a property can be particularly beneficial in geo-distributed and edge-computing scenarios. We build O rca , a modified version of ZooKeeper that implements C ad and cross-client monotonic reads. We experimentally show that O rca provides strong consistency while closely matching the performance of weakly consistent ZooKeeper. Compared to strongly consistent ZooKeeper, O rca provides significantly higher throughput (1.8--3.3×) and notably reduces latency, sometimes by an order of magnitude in geo-distributed settings. We also implement C ad in Redis and show that the performance benefits are similar to that of C ad ’s implementation in ZooKeeper.

Computer Science↗
DOE OSTI2021

Single-node Partitioned-Memory for Huge Graph Analytics: Cost and Performance Trade-offs

Nonvolatile memory NVDIMMs, available as Intel Optane, are less expensive than DRAM and bring large byte-addressable storage within reach to many applications. Evaluations on graph analytics have shown promising performance only when DRAM is used as a hardware cache (Memory mode). An open question is whether graph applications can exploit Optane and DRAM directly (AppDirect mode) and achieving better-than-DRAM average bandwidth and run times. We evaluate Optane as a volatile pool on two large-scale graph applications with very different computational patterns, Grappolo and Ripples. We show that AppDirect mode can deliver better-than-DRAM performance, by allocating data structures to Optane and DRAM according to their access characteristics, resulting in higher average memory bandwidth and lower average latency. Memory mode provides DRAM-competitive performance with capacity equal to persistent memory. We demonstrate occasional 4x improvement using the latest AppDirect option and frequently observe competitive performance between Optane AppDirect Memory modes and DRAM.

Ghosh, Sayan↗
DOE OSTI2021

MAPA: Multi-Accelerator Pattern Allocation Policy for Multi-Tenant GPU Servers

Multi-accelerator servers are increasingly being deployed in shared multi-tenant environments (such as in cloud data centers) in order to meet the demands of large-scale compute-intensive workloads. In addition, these accelerators are increasingly being inter-connected in complex topologies and workloads are exhibiting a wider variety of inter-accelerator communication patterns. However, existing al-location policies are ill-suited for these emerging use-cases. Specifically, this work identifies that multi-accelerator workloads are commonly fragmented leading to reduced bandwidth and increased latency for inter-accelerator communication. We propose Multi-Accelerator Pattern Allocation (MAPA), a graph pattern mining approach towards providing generalized allocation support for allocating multi-accelerator workloads on multi-accelerator servers. We demonstrate that MAPA is able to improve the execution time of multi-accelerator workloads and that MAPA is able to provide generalized benefits across various accelerator topologies. Finally, we demonstrate a speedup of 12.4% for75th percentile of jobs with the worst case execution time reduced by up to 35% against baseline policy using MAPA.

Ranganath, Kiran↗
DOE OSTI2021

Timely Reporting of Heavy Hitters Using External Memory

Given an input stream S of size N, a Φ-heavy hitter is an item that occurs at least ΦN times in S. The problem of finding heavy-hitters is extensively studied in the database literature. In this work, we study a real-time heavy-hitters variant in which an element must be reported shortly after we see its T = Φ N-th occurrence (and hence it becomes a heavy hitter). We call this the Timely Event Detection (TED) Problem. The TED problem models the needs of many real-world monitoring systems, which demand accurate (i.e., no false negatives) and timely reporting of all events from large, high-speed streams with a low reporting threshold (high sensitivity). Like the classic heavy-hitters problem, solving the TED problem without false-positives requires large space (Ω (N) words). Thus in-RAM heavy-hitters algorithms typically sacrifice accuracy (i.e., allow false positives), sensitivity, or timeliness (i.e., use multiple passes). We show how to adapt heavy-hitters algorithms to external memory to solve the TED problem on large high-speed streams while guaranteeing accuracy, sensitivity, and timeliness. Our data structures are limited only by I/O-bandwidth (not latency) and support a tunable tradeoff between reporting delay and I/O overhead. With a small bounded reporting delay, our algorithms incur only a logarithmic I/O overhead. We implement and validate our data structures empirically using the Firehose streaming benchmark. Multi-threaded versions of our structures can scale to process 11M observations per second before becoming CPU bound. In comparison, a naive adaptation of the standard heavy-hitters algorithm to external memory would be limited by the storage device’s random I/O throughput, i.e., ≈100K observations per second.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

Spiking Neural Networks (SNNs) are an emerging computation model that uses event-driven activation and bio-inspired learning algorithms. SNN-based machine learning programs are typically executed on tile-based neuromorphic hardware platforms, where each tile consists of a computation unit called a crossbar, which maps neurons and synapses of the program. However, synthesizing such programs on an off-the-shelf neuromorphic hardware is challenging. This is because of the inherent resource and latency limitations of the hardware, which impact both model performance, e.g., accuracy, and hardware performance, e.g., throughput. We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware. The proposed framework works in four steps. First, it analyzes a machine learning program and generates SNN workload using representative data. Second, it partitions the SNN workload and generates clusters that fit on crossbars of the target neuromorphic hardware. Third, it exploits the rich semantics of the Synchronous Dataflow Graph (SDFG) to represent a clustered SNN program, allowing for performance analysis in terms of key hardware constraints such as number of crossbars, dimension of each crossbar, buffer space on tiles, and tile communication bandwidth. Finally, it uses a novel scheduling algorithm to execute clusters on crossbars of the hardware, guaranteeing hardware performance. We evaluate DFSynthesizer with 10 commonly used machine learning programs. Our results demonstrate that DFSynthesizer provides a much tighter performance guarantee compared to current mapping approaches.

Computer Science↗
DOE OSTI2022

Exploring the Use of Novel Spatial Accelerators in Scientific Applications

Driven by the need to find alternative accelerators which can viably replace GPUs in next-generation Supercomputing systems, this paper proposes a methodology to enable agile application/hardware co-design. The application-first methodology provides the ability to come up with design of accelerators while working with real-world workloads, available accelerators, and system software. The iterative design process targets a set of kernels in a workload for performance estimates that can prune the design space for later phases of detailed architectural evaluations. To this effect, in this paper, a novel data-parallel device model is introduced that simulates the latency of performance-sensitive operations in an accelerator including data transfers and kernel computation using multi-core CPUs. The use of off-the-shelf simulators, such as pre-RTL simulator Aladdin or multiple tools available for exploring the design of deep neural network accelerators (e.g., Timeloop) is demonstrated for evaluation of various accelerator designs using applications with realistic inputs. Examples of multiple device configurations that are instantiable in a system are explored to evaluate the performance benefit of deploying novel accelerators. The proposed device is integrated with a programming model and system software to potentially explore the impacts of high-level programming languages/compilers and low-level effects such as task scheduling on multiple accelerators. We analyze our methodology for a set of applications that represent high-performance computing (HPC) and graph analytics. The applications include a computational chemistry kernel realized using tensor contractions, triangle counting, GraphSAGE and Breadth-first Search. These applications include kernels such as dense matrix-dense matrix multiplication, sparse matrix-spare matrix multiplication, and sparse matrix-dense vector multiplication. Our results indicate potential performance benefits and insights for system design by including accelerators that realize these kernels along-side general purpose accelerators.

AI, codesign, Accelerated Computing, Modeling and ↗
DOE OSTI2023

Analysis of a Runtime Data Sharing Architecture over LTE for a Heterogeneous CAV Fleet

This paper describes a lightweight runtime architecture for telemetry, communication, and control of cars deployed with advanced driver assistance systems where a human is in the loop with the car, via an LTE connection. The system architecture supports both local control decisions based on car sensors and safety algorithms as well as high-level input from external systems that may provide insight into traffic state ahead of sensor data. Implementation of the architecture is done in ROS and depends on open-source software packages for runtime decoding of information from the vehicle’s controller area network (CAN) and integration of GPS data from accompanying sensors. The contribution of the paper is to describe the overall architecture, the data it can communicate to other systems, performance of the system at runtime, and challenges faced when deploying the architecture across a heterogeneous fleet. Preliminary results from analysis of test data will provide insights into whether the use of high-latency communication can be effective for societal-scale intelligent transportation systems when applied in future scenarios

Richardson, Alex↗