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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 325 records · Page 18

Truss structure design

An integrally formed three-dimensional truss structure, including molds and methods for production of same, containing outer top and bottom plane surfaces thereof comprising interconnected rod segments integrally formed at their points of intersection on the outer top and bottom surfaces, the top and bottom surfaces also integrally joined together through additional interconnected rod segments passing through an integrally formed intersection, wherein the additional interconnected rod segments passing through the integrally formed intersection form a three-dimensional continuous array of triangles.

Daily, Carl S.↗

Vibration isolation mounting system

A system is disclosed for mounting a vibration producing device onto a spacecraft structure and also for isolating the vibration forces thereof from the structure. The system includes a mount on which the device is securely mounted and inner and outer rings. The rings and mount are concentrically positioned. The system includes a base (secured to the structure) and a set of links which are interconnected by a set of torsion bars which allow and resist relative rotational movement therebetween. The set of links are also rotatably connected to a set of brackets which are rigidly connected to the outer ring. Damped leaf springs interconnect the inner and outer rings and the mount allow relative translational movement therebetween in X and Y directions. The links, brackets and base are interconnected and configured so that they allow and resist translational movement of the device in the Z direction so that in combination with the springs they provide absorption of vibrational energy produced by the device in all three dimensions while providing rotational stiffness about all three axes to prevent undesired rotational motions.

Carter, Sam D.↗

High conductance ohmic junction for monolithic semiconductor devices

In order to increase the efficiency of solar cells, a monolithic stacked device is constructed comprising a plurality of solar sub-cells adjusted for different bands of radiation. The interconnection between these sub-cells has been a significant technical problem. The invention provides an interconnection which is a thin layer of high ohmic conductance material formed between the sub-cells. Such a layer tends to form beads which serve as a shorting interconnect while passing a large fraction of the radiation to the lower sub-cells and permitting lattice-matching between the sub-cells to be preserved.

Lewis, Carol R.↗

Method of making a high conductance ohmic junction for monolithic semiconductor devices

In order to increase the efficiency of solar cells, a monolithic stacked device is constructed comprising a plurality of solar sub-cells adjusted for different bands of radiation. The interconnection between these sub-cells has been a significant technical problem. The invention provides an interconnection which is a thin layer of high ohmic conductance material formed between the sub-cells. Such a layer tends to form beads which serve as a shorting interconnect while passing a large fraction of the radiation to the lower sub-cells and permitting lattice-matching between the sub-cells to be preserved.

Lewis, Carol R.↗

Computationally efficient modeling and simulation of large scale systems

A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X.sup.1 and at least one other matrix, with first equation including X.sup.1Y, X.sup.1A, and X.sup.1P, and the second equation including X.sup.1A and X.sup.1P.

Jain, Jitesh↗

Computationally efficient modeling and simulation of large scale systems

A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X.sup.-1 and at least one other matrix, with first equation including X.sup.-1Y, X.sup.-1A, and X.sup.-1P, and the second equation including X.sup.-1A and X.sup.-1P.

Jain, Jitesh↗

Fully Printed, Flexible, Phased Array Antenna for Lunar Surface Communication

NASAs future exploration missions focus on the manned exploration of the Moon, Mars, and beyond, which will rely heavily on the development of a reliable communications infrastructure from planetary surface-to-surface, surface-to-orbit, and back to Earth. Flexible antennas are highly desired in many scenarios. Active phased array antennas (active PAAs) with distributed control and processing electronics at the surface of an antenna aperture offer numerous advantages for radar communications. Large-area active PAAs on flexible substrates are of particular interest in NASA s space radars due to their efficient inflatable package that can be rolled up during transportation and deployed in space. Such an inflatable package significantly reduces stowage volume and mass. Because of these performance and packaging advantages, large-area inflatable active PAAs are highly desired in NASA s surface-to-orbit and surface-to-relay communications. To address the issues of flexible electronics, a room-temperature printing process of active phased-array antennas on a flexible Kapton substrate was developed. Field effect transistors (FETs) based on carbon nanotubes (CNTs), with many unique physical properties, were successfully proved feasible for the PAA system. This innovation is a new type of fully inkjet-printable, two-dimensional, high-frequency PAA on a flexible substrate at room temperature. The designed electronic circuit components, such as the FET switches in the phase shifter, metal interconnection lines, microstrip transmission lines, etc., are all printed using a special inkjet printer. Using the developed technology, entire 1x4, 2x2, and 4x4 PAA systems were developed, packaged, and demonstrated at 5.3 GHz. Several key solutions are addressed in this work to solve the fabrication issues. The source/drain contact is developed using droplets of silver ink printed on the source/drain areas prior to applying CNT thin-film. The wet silver ink droplets allow the silver to wet the CNT thin-film area and enable good contact with the source and drain contact after annealing. A passivation layer to protect the device channel is developed by bonding a thin Kapton film on top of the device channel. This film is also used as the media for transferring the aligned CNT thin-film on the device substrate. A simple and cost-effective technique to form multilayer metal interconnections on flexible substrate is developed and demonstrated. Contact vias are formed on the second substrate prior to bonding on the first substrate. Inkjet printing is used to fill the silver ink into the via structure. The printed silver ink penetrates through the vias to contact with the contact pads on the bottom layer. It is then annealed to form a good connection. One-dimensional and two-dimensional PAAs were fabricated and characterized. In these circuits, multilayer metal interconnects were used to make a complete PAA system.

Subbaraman, Harish↗

Computationally Efficient Modeling and Simulation of Large Scale Systems

A system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, including a processor, and a memory, the processor configured to perform obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure, the element values for each matrix including inductance L and inverse capacitance P, obtaining an adjacency matrix A associated with the interconnect structure, storing the matrices X, Y, and A in the memory, and performing numerical integration to solve first and second equations.

Jain, Jitesh↗

Interfacing Space Communications and Navigation Network Simulation with Distributed System Integration Laboratories (DSIL)

NASA's planned Lunar missions will involve multiple NASA centers where each participating center has a specific role and specialization. In this vision, the Constellation program (CxP)'s Distributed System Integration Laboratories (DSIL) architecture consist of multiple System Integration Labs (SILs), with simulators, emulators, testlabs and control centers interacting with each other over a broadband network to perform test and verification for mission scenarios. To support the end-to-end simulation and emulation effort of NASA' exploration initiatives, different NASA centers are interconnected to participate in distributed simulations. Currently, DSIL has interconnections among the following NASA centers: Johnson Space Center (JSC), Kennedy Space Center (KSC), Marshall Space Flight Center (MSFC) and Jet Propulsion Laboratory (JPL). Through interconnections and interactions among different NASA centers, critical resources and data can be shared, while independent simulations can be performed simultaneously at different NASA locations, to effectively utilize the simulation and emulation capabilities at each center. Furthermore, the development of DSIL can maximally leverage the existing project simulation and testing plans. In this work, we describe the specific role and development activities at JPL for Space Communications and Navigation Network (SCaN) simulator using the Multi-mission Advanced Communications Hybrid Environment for Test and Evaluation (MACHETE) tool to simulate communications effects among mission assets. Using MACHETE, different space network configurations among spacecrafts and ground systems of various parameter sets can be simulated. Data that is necessary for tracking, navigation, and guidance of spacecrafts such as Crew Exploration Vehicle (CEV), Crew Launch Vehicle (CLV), and Lunar Relay Satellite (LRS) and orbit calculation data are disseminated to different NASA centers and updated periodically using the High Level Architecture (HLA). In addition, the performance of DSIL under different traffic loads with different mix of data and priorities are evaluated.

Traffic Measuring and Monitoring↗

Progress Towards Prolonged Deployment of SiC JFET-R ICs Into Previously Inaccessible Hostile Environments

This invited presentation describes demonstration of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. SiC junction field effect transistor-resistor (JFET-R) ICs with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient [1], 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber [2], and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes [3]. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C T-span) without significant change in signal (input /output) or power supply voltages [4]. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards this end, the processing that forms the SiC JFETs and resistors (without interconnect) for the NASA Glenn “Generation 12” design prototype JFET-R ICs was conducted at GE Research. Once the COVID-delayed IC interconnect and bond pad fabrication processing on these wafers is completed at NASA Glenn, the resulting chips will be packaged and oven-tested [5]. It is expected that further technology transfer to complete commercial production will lower investment and risk barriers to useful application deployment. For NASA, an initial high-value deployment is opening the Venus surface to extended missions for robotic scientific exploration.

Silicon Carbide↗

Method of improving contact bonds in silicon integrated circuits

Fabrication method produces stable and reliable metallic systems for interconnections, contact pads, and bonded leads in silicon planar integrated circuits. The method is based on substrate isolation of the interconnection metal from the contact pad and bonded wire.

Lytle, W. J.↗

Breakaway electrical connector

One-shot, breakaway multiwire cable connector is fabricated by using a number of small-diameter interconnecting wires, each of which, differing incrementally in length, is welded to neighboring pin and cable terminations. This design eliminates frictional binding and provides highly reliable cable interconnections until the connector is disengaged.

Katzin, L.↗

Ceramic wiring board increases packaging density of electronic modules

Ceramic multilayer wiring board interconnects large scale integration /LSI/ modules which dissipate nearly 2W/cc. Extremely high packaging density is possible by application of alumina cover hermetically sealed to board. Signal interconnections are completely dependent on transfer heat between layers.

Hamley, L. D.↗

Development of chip passivated monolithic complementary MISFET circuits with beam leads

Fabrication method is described for alumina passivated silicon MISFET arrays. Technique involves total passivation beam-lead approach and provides completely sealed chip with double level interconnect capability. Refractory metal alloy is used to form interconnect system and obtain metal contacts that withstand temperatures of 873 K for short periods of time.

Ragonese, L. J.↗

Flat conductor cable design, manufacture, and installation

Pertinent information for hardware selection, design, manufacture, and quality control necessary for flat conductor cable interconnecting harness application is presented. Comparisons are made between round wire cable and flat conductor cable. The flat conductor cable interconnecting harness systems show major cost, weight, and space savings, plus increased system performance and reliability. The design application section includes electrical characteristics, harness design and development, and a full treatise on EMC considerations. Manufacturing and quality control sections pertain primarily to the developed conductor-contact connector system and special flat conductor cable to round wire cable transitions.

Angele, W.↗

Development of a lightweight body-mounted solar cell array with a high power to weight ratio.

Three lightweight solar cell arrays have been fabricated with a high power-to-weight ratio. These arrays incorporate resistance welded interconnections, improved antireflection coating on the solar cell and lightweight substrates. Two of the substrates were constructed of magnesium with different structural geometry, while the third substrate was conventional aluminum honeycomb. All arrays utilized thin solar cells having a titanium-palladium-silver contact system and an antireflection coating of titanium oxide. The cells were welded with silver plated molybdenum interconnections. The two arrays having magnesium substrates exhibited a power/weight of 70.4 W/kg (32 W/lb.) and 81 W/kg (36.8 W/lb.), while the conventional array demonstrated a power/weight of 45.2 W/kg (20.6 W/lb.).

Somberg, H.↗

Advanced On-Board Processor (AOP)

Advanced On-board Processor the (AOP) uses large scale integration throughout and is the most advanced space qualified computer of its class in existence today. It was designed to satisfy most spacecraft requirements which are anticipated over the next several years. The AOP design utilizes custom metallized multigate arrays (CMMA) which have been designed specifically for this computer. This approach provides the most efficient use of circuits, reduces volume, weight, assembly costs and provides for a significant increase in reliability by the significant reduction in conventional circuit interconnections. The required 69 CMMA packages are assembled on a single multilayer printed circuit board which together with associated connectors constitutes the complete AOP. This approach also reduces conventional interconnections thus further reducing weight, volume and assembly costs.

Source record↗

Decomposition-aggregation stability analysis

This report presents the development and description of the decomposition aggregation approach to stability investigations of high dimension mathematical models of dynamic systems. The high dimension vector differential equation describing a large dynamic system is decomposed into a number of lower dimension vector differential equations which represent interconnected subsystems. Then a method is described by which the stability properties of each subsystem are aggregated into a single vector Liapunov function, representing the aggregate system model, consisting of subsystem Liapunov functions as components. A linear vector differential inequality is then formed in terms of the vector Liapunov function. The matrix of the model, which reflects the stability properties of the subsystems and the nature of their interconnections, is analyzed to conclude over-all system stability characteristics. The technique is applied in detail to investigate the stability characteristics of a dynamic model of a hypothetical spinning Skylab.

Siljak, D. D.↗