Beam-lead processing of complementary MOS integrated circuits
Beam-lead technology application to complementary MOS IC processing
Murray, L. A.↗
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Evaluation of errors in prior mean and variance in the estimation of integrated circuit failure rates using Bayesian methods
The critical point of any Bayesian analysis concerns the choice and quantification of the prior information. The effects of prior data on a Bayesian analysis are studied. Comparisons of the maximum likelihood estimator, the Bayesian estimator, and the known failure rate are presented. The results of the many simulated trails are then analyzed to show the region of criticality for prior information being supplied to the Bayesian estimator. In particular, effects of prior mean and variance are determined as a function of the amount of test data available.
Fletcher, B. C.↗
Derivation of a tangent function using an integrated circuit four-quadrant multiplier
A tangent function generator is provided which utilizes input signals proportionate to the sine and cosine of a given angle. The equipment accomplishes a trigonometric manipulation which forms an output signal substantially independent of the input reference voltage but proportional to the tangent of the angle. The device uses a multiplier and operational amplifier.
Bregman, B. J.↗
A quick accurate method to measure the dielectric constant of microwave integrated-circuit substrates.
Explore the source record for details and available documents.
Howell, J. Q.↗
Integrated-circuit balanced parametric amplifier
Amplifier, fabricated on single dielectric substrate, has pair of Schottky barrier varactor diodes mounted on single semiconductor chip. Circuit includes microstrip transmission line and slot line section to conduct signals. Main features of amplifier are reduced noise output and low production cost.
Dickens, L. E.↗
An optimized output stage for MOS integrated circuits
An output device for optimizing propagation delay and minimizing chip area is described. An optimum means of tapering the output stages to minimize propagation delay is determined. The minimum delay is a function of the capacitive load to node ratio, the number of output stages, and the interstage propagation delay. The effects on area are also presented. A figure of merit which is a function of area and propagation time is defined which is of use in designing output stages. An optimum exists which can be considered the best compromise between further decreasing propagation delay and increasing chip area. Data are also presented which allow a designer to determine the minimum chip area once the capacitive load and the maximum allowable delay are known.
Lin, H. C.↗
The 1.06 micrometer avalanche photodiode detectors with integrated circuit preamplifiers
The development of a complete solid state 1.06 micron optical receiver which can be used in optical communications at data rates approaching 1.5 Gb/s, or in other applications requiring sensitive, short-pulse detection, is reported. This work entailed both the development of a new type of heterojunction 3-5 semiconductor alloy avalanche photodiode and an extremely charge-sensitive wideband low-noise preamp design making use of GaAs Schottky barrier-gate field effect transistors.
Eden, R. C.↗
Complementary DMOS/VMOS integrated-circuit-structure
Complementary metal-oxide-semiconductor (CMOS) structure has relatively high speed, high breakdown voltage, high transconductance and high packing densities.
Jhabvala, M. D.↗
On the applicability of integrated circuit technology to general aviation orientation estimation
The criteria of the significant value of the panel instruments used in general aviation were examined and kinematic equations were added for comparison. An instrument survey was performed to establish the present state of the art in linear and angular accelerometers, pressure transducers, and magnetometers. A very preliminary evaluation was done of the computers available for data evaluation and estimator mechanization. The mathematical model of a light twin aircraft employed in the evaluation was documented, the results of the sensor survey and the results of the design studies were presented.
Debra, D. B.↗
Reclaiming hybrid integrated circuits
Reclamation method consists of opening very small hole in package and shaking out trapped particles. Procedure is performed in dry box through which an inert gas is flowing to insure no room air enters package. Acoustic transducer monitors sound of vibrating particles. Amplifier produces audio and oscilloscope output. Hole is sealed with heated solder form.
Ebel, G.↗
Custom large scale integrated circuits for spaceborne SAR processors
The application of modern LSI technology to the development of a time-domain azimuth correlator for SAR processing is discussed. General design requirements for azimuth correlators for missions such as SEASAT-A, Venus orbital imaging radar (VOIR), and shuttle imaging radar (SIR) are summarized. Several azimuth correlator architectures that are suitable for implementation using custom LSI devices are described. Technical factors pertaining to selection of appropriate LSI technologies are discussed, and the maturity of alternative technologies for spacecraft applications are reported in the context of expected space mission launch dates. The preliminary design of a custom LSI time-domain azimuth correlator device (ACD) being developed for use in future SAR processors is detailed.
Tyree, V. C.↗
Complementary DMOS-VMOS integrated circuit structure
A high speed CMOS formed on a single semiconductor substrate includes a DMOS having an asymmetric channel and a VMOS with a relatively short channel length. The short channel length of the VMOS is achieved by forming a double diffusion along one edge of a V groove, or ion implanting boron into the apex of the V groove and diffusing a single layer to a relatively deep depth along both edges of the groove.
Jhabvala, M. O.↗
Custom large scale integrated circuits for spaceborne SAR processors
The application of modern LSI technology to the development of a time-domain azimuth correlator for SAR processing is discussed. General design requirements for azimuth correlators for such missions as Seasat-A, Venus Orbital Imaging Radar, and Shuttle Imaging Radar are summarized. Several azimuth correlator architectures suitable for implementation using custom LSI devices are described. Technical factors pertaining to selection of appropriate LSI technologies are discussed, and the maturity of alternative technologies for spacecraft application is examined in the context of the expected launch dates. In particular, it is demonstrated that a custom LSI device is practical for a system as complex as the DMSP.
Tyree, V. C.↗
CADAT integrated circuit artwork program
Versatile, ready-to-use program (ARTWORK) converts artwork data into mask patterns. ARTWORK generates signals for controlling mask-fabricating equipment. Extensive utility package enables user to create new pattern libraries, develop and incorporate new cells, and perform systems orientation functions. Program is written in FORTRAN IV.
Kvelthau, R. L.↗
Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation
Progress in developing the application of ion implantation techniques to silicon gate CMOS/SOS processing is described. All of the conventional doping techniques such as in situ doping of the epi-film and diffusion by means of doped oxides are replaced by ion implantation. Various devices and process parameters are characterized to generate an optimum process by the use of an existing SOS test array. As a result, excellent circuit performance is achieved. A general description of the all ion implantation process is presented.
Woo, D. S.↗
Simulation of cosmic-ray induced soft errors and latchup in integrated-circuit computer memories
Soft errors have been induced in solid-state static RAM's by iron nuclei from the Lawrence Berkeley Laboratory (LBL) Bevalac, in experiments designed to prove the ability of iron-group cosmic rays to generate such errors. Subsequently, various delidded device types were tested in beams of argon and krypton ions from the LBL 88-inch Cyclotron, at energies near 2 MeV/nucleon. The latter tests showed that some devices are essentially immune to bit error while others are quite susceptible. Good agreement was obtained with model predictions in cases where the latter exist. Latchup, whose cause is attributed to individual heavy ions, was also observed in some device types.
Kolasinski, W. A.↗
User's manual for large-scale integrated circuit layout check program
A computer program is described that checks for the correctness of chip design layout generated by the Banning Placement Routing Folding program (PRF) by verifying agreement between a specified circuit design and a corresponding computer generated circuit layout as stored on the Artwork (PRF output) tape. An example computer run is included.
Source record↗
An evaluation of the Intel 2920 digital signal processing integrated circuit
The circuit consists of a digital to analog converter, accumulator, read write memory and UV erasable read only memory. The circuit can convert an analog signal to a digital representation, perform mathematical operations on the digital signal and subsequently convert the digital signal to an analog output. Development software tailored for programming the 2920 is presented.
Heller, J.↗