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Number of addressable registers increased. Monitoring and controlling interface circuit expands capabilities of DR11-C (or equivalent) input/output port for computer that communicates with peripheral equipment via UNIBUS (or equivalent) data bus. Using only three address locations on bus, unit enables any number of external registers to be addressed, read, or written.
Mohammad Zadeh from ETAP presented various modeling improvements that included the following: • Address convergence issues by using complete Norton Equivalent model including the IBR series filter impedance. • Fault ride through identification within iterations while short circuit results have not been converged and how that may impact final SC results. • Options for FRT curve 1- using a timer to lock FRT logic vs a hysteresis in FRT curve to avoid unwanted toggling. • Report recent co-operation between software vendors (Aspen, CAPE and ETAP) for adopting a C++ interface for IBR blackbox SC modeling. There was lot of interest to know about the model improvements that are being considered.
The objective of this study is to develop a new methodology for estimating the reliability of engineering systems that encompass multiple disciplines. The methodology is formulated in the context of the NESSUS probabilistic structural analysis code developed under the leadership of NASA Lewis Research Center. The NESSUS code has been successfully applied to the reliability estimation of a variety of structural engineering systems. This study examines whether the features of NESSUS could be used to investigate the reliability of systems in other disciplines such as heat transfer, fluid mechanics, electrical circuits etc., without considerable programming effort specific to each discipline. In this study, the mechanical equivalence between system behavior models in different disciplines are investigated to achieve this objective. A new methodology is presented for the analysis of heat transfer, fluid flow, and electrical circuit problems using the structural analysis routines within NESSUS, by utilizing the equivalence between the computational quantities in different disciplines. This technique is integrated with the fast probability integration and system reliability techniques within the NESSUS code, to successfully compute the system reliability of multi-disciplinary systems. Traditional as well as progressive failure analysis methods for system reliability estimation are demonstrated, through a numerical example of a heat exchanger system involving failure modes in structural, heat transfer and fluid flow disciplines.
The objective of this study is to develop a new methodology for estimating the reliability of engineering systems that encompass multiple disciplines. The methodology is formulated in the context of the NESSUS probabilistic structural analysis code, developed under the leadership of NASA Glenn Research Center. The NESSUS code has been successfully applied to the reliability estimation of a variety of structural engineering systems. This study examines whether the features of NESSUS could be used to investigate the reliability of systems in other disciplines such as heat transfer, fluid mechanics, electrical circuits etc., without considerable programming effort specific to each discipline. In this study, the mechanical equivalence between system behavior models in different disciplines are investigated to achieve this objective. A new methodology is presented for the analysis of heat transfer, fluid flow, and electrical circuit problems using the structural analysis routines within NESSUS, by utilizing the equivalence between the computational quantities in different disciplines. This technique is integrated with the fast probability integration and system reliability techniques within the NESSUS code, to successfully compute the system reliability of multidisciplinary systems. Traditional as well as progressive failure analysis methods for system reliability estimation are demonstrated, through a numerical example of a heat exchanger system involving failure modes in structural, heat transfer and fluid flow disciplines.
The short-circuit current reduction in GaAs shallow junction heteroface solar cells was calculated according to a simplified solar cell damage model in which the nonuniformity of the damage as a function of penetration depth is treated explicitly. Although the equivalent electron fluence was not uniquely defined for low-energy monoenergetic proton exposure, an equivalent electron fluence is found for proton spectra characteristic of the space environment. The equivalent electron fluence ratio was calculated for a typical large solar flare event for which the proton spectrum is PHI(sub p)(E) = A/E(p/sq. cm) where E is in MeV. The equivalent fluence ratio is a function of the cover glass shield thickness or the corresponding cutoff energy E(sub c). In terms of the cutoff energy, the equivalent 1 MeV electron fluence ratio is r(sub p)(E sub c) = 10(9)/E(sub c)(1.8) where E(sub c) is in units of KeV.
Several previously used instrumentation amplifier circuits were examined to find limitations and possibilities for improvement. One general configuration is analyzed in detail, and methods for improvement are enumerated. An improved amplifier circuit is described and analyzed with respect to common mode rejection and noise. Experimental data are presented showing good agreement between calculated and measured common mode rejection ratio and equivalent noise resistance. The amplifier is shown to be capable of common mode rejection in excess of 140 db for a trimmed circuit at frequencies below 100 Hz and equivalent white noise below 3.0 nv/square root of Hz above 1000 Hz.
The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.
Results of hydrogen-passivated polycrystalline silicon solar cells are summarized. Very small grain or short minority-carrier diffusion length silicon was used. Hydrogenated solar cells fabricated from this material appear to have effective minority-carrier diffusion lengths that are still not very long, as shown by the open-circuit voltages of passivated cells that are still significantly less than those of single-crystal solar cells. The short-circuit current of solar cells fabricated from large-grain cast polycrystalline silicon is nearly equivalent to that of single-crystal cells, which indicates long bulk minority-carrier diffusion length. However, the open-circuit voltage, which is sensitive to grain boundary recombination, is sometimes 20 to 40 mV less. The goal was to minimize variations in open-circuit voltage and fill-factor caused by defects by passivating these defects using a hydrogenation process. Treatments with molecular hydrogen showed no effect on large-grain cast polycrystaline silicon solar cells.
Indium phosphide (InP) solar cells are being made on silicon (Si) wafers (InP/Si) to take advantage of both the radiation-hardness properties of the InP solar cell and the light weight and low cost of Si wafers compared to InP or germanium (Ge) wafers. The InP/Si cell application is for long duration and/or high radiation orbit space missions. InP/Si cells have higher absolute efficiency after a high radiation dose than gallium arsenide (GaAs) or silicon (Si) solar cells. In this work, base electron diffusion lengths in the N/P cell are extracted from measured AM0 short-circuit photocurrent at various irradiation levels out to an equivalent 1 MeV fluence of 1017 1 MeV electrons/sq cm for a 1 sq cm 12% BOL InP/Si cell. These values are then checked for consistency by comparing measured Voc data with a theoretical Voc model that includes a dark current term that depends on the extracted diffusion lengths.
Charging can occur in space due to plasma and high energy particles. Charging is especially severe in certain earth orbits such as geostationary orbit, medium earth orbit and highly inclined orbit. A spacecraft that travels to other planets such as Jupiter also encounters high level of charging due to Jupiter’s radiation belt. The major concern for spacecraft operation due to charging is the survival of sensitive electrical circuits. Dielectrics and floating metal can charge up and discharge onto interface circuits. The electrical circuits need to be evaluated for survival from the electrostatic-discharge (ESD) threat. Both ESD induced upset and damage need to be assessed. The interface circuits are often located inside a shielded unit in the spacecraft structure or a shielded vault with sufficient radiation shielding to avoid surface and internal charging. The materials external to the highly shielded area can charge up and discharge onto wires that can directly dissipate the ESD onto the interface circuits. Figure 1 shows a possible discharge mechanism onto the interfacing circuits. If the wire has an external shield or a coaxial line, some or most of the discharge can flow on the shield to chassis ground. There is always coupling from external discharge. If the wire has no shield, the discharge flows onto the interface circuit. Fig. 1 Possible discharge paths onto the interface circuits. The purpose of this article is to address how to model the ESD threat to be used as the discharge source onto the interface circuit based on the electron beam test data. Different models are needed for different impedances associated with the interface circuits. Once those models are derived, one needs to analyze the interface circuit with the corresponding model using an electrical simulation tool. Then, the circuit’s front-end components can be assessed for damage and upset. Upset is highly dependent on the circuit operation and system requirements, and thus it is not addressed any further. Damage of electrical parts is often rated under Human-Body-Model (HBM) ESD. One can utilize this industry-wide available information to assess the damage vulnerability due to space discharges. However, the HBM waveform does not always match the discharge waveform. To estimate the damage vulnerability of the circuit and set margin, one needs to compare the equivalent energy delivered to the victim between a HBM discharge and the results from an ESD source model based on actual discharges. This paper presents such a comparison for a few select cases.
We develop a global variable substitution method that reduces n-variable monomials in combinatorial optimization problems to equivalent instances with monomials in fewer variables. We apply this technique to 3-SAT and analyze the optimal quantum unitary circuit depth needed to solve the reduced problem using the quantum approximate optimization algorithm. For benchmark 3-SAT problems, we find that the upper bound of the unitary circuit depth is smaller when the problem is formulated as a product and uses the substitution method to decompose gates than when the problem is written in the linear formulation, which requires no decomposition.
The Skipper CCD-in-CMOS Parallel Read-Out Circuit (SPROCKET) is a mixed-signal front-end design for the readout of Skipper CCD-in-CMOS image sensors. SPROCKET is fabricated in a 65 nm CMOS process and each pixel occupies a 50$\mu$m $\times$ 50$\mu$m footprint. SPROCKET is intended to be heterogeneously integrated with a Skipper-in-CMOS sensor array, such that one readout pixel is connected to a multiplexed array of nine Skipper-in-CMOS pixels to enable massively parallel readout. The front-end includes a variable gain preamplifier, a correlated double sampling circuit, and a 10-bit serial successive approximation register (SAR) ADC. The circuit achieves a sample rate of 100 ksps with 0.48 $\mathrm{e^-_{rms}}$ equivalent noise at the input to the ADC. SPROCKET achieves a maximum dynamic range of 9,000 $e^-$ at the lowest gain setting (or 900 $e^-$ at the lowest noise setting). The circuit operates at 100 Kelvin with a power consumption of 40 $\mu W$ per pixel. A SPROCKET test chip was submitted in September 2022, and test results will be presented at the conference.
The efficiency of all-perovskite tandem devices falls far below theoretical efficiency limits, mainly because a widening bandgap fails to increase open-circuit voltage. We report on a bifacial all-perovskite tandem structures with an equivalent efficiency of 29.3% under back-to-front irradiance ratio of 30. This increases energy yield and reduces the required bandgap of a wide-bandgap cell. Open-circuit voltage deficit is therefore minimized, although its performance under only front irradiance is not ideal. The bifacial device needs a sputtered rear transparent electrode, which could reduce photon path length and deteriorate stability of Pb-Sn perovskites. Embedding a light-scattering micrometer-sized particle layer into perovskite to trap light, effectively increases absorptance by 5 to 15% in the infrared region. Using a nonacidic hole transport layer markedly stabilizes the hole-extraction interface by avoiding proton-accelerated formation of iodine. These two strategies together increase efficiency of semitransparent Pb-Sn cells from 15.6 to 19.4%, enabling fabrication of efficient bifacial all-perovskite tandem devices.
The TAXI Direct-to-Disk interface is a special-purpose interface circuit for demultiplexing of data from a Racal Storeplex (or equivalent) multichannel recorder onto one or more hard disks that reside in, and/or are controlled by, a personal computer (PC). (The name TAXI as used here is derived from the acronym TAXI, which signifies transparent asynchronous transceiver interface.) The TAXI Direct-to-Disk interface was developed for original use in capturing data from instrumentation on a test stand in a NASA rocket-testing facility. The control, data-recording, and data-postprocessing equipment of the facility are located in a control room at a safe distance from the test stand. Heretofore, the transfer of data from the instrumentation to the postprocessing equipment has entailed post-test downloading via software, requiring many hours to days of post-test reduction before the data could be viewed in a channelized format. The installation of the TAXI Direct-to-Disk interface, in conjunction with other modifications, causes the transfer of data to take place in real time, so that the data are immediately available for review during or after the test. The instrumentation is connected to the input terminals of the signal-processing unit of multichannel recorder by standard coaxial cables. The coaxial output of the signal processing unit is converted to fiber-optic output by means of a commercial coaxial-cable/fiber-optic converter (that is, a fiber-optic transceiver) designed specifically for this application. The fiber-optic link carries the data signals to an identical fiber-optic transceiver in the control room. On the way to the TAXI Direct-to-Disk interface that is the focus of this article, the data signals are processed through a companion special purpose circuit denoted by the similar name parallel TAXI interface.
Optimizing parameterized quantum circuits (PQCs) is the leading approach to make use of near-term quantum computers. However, very little is known about the cost function landscape for PQCs, which hinders progress towards quantum-aware optimizers. In this work, we investigate the connection between three different landscape features that have been observed for PQCs: (1) exponentially vanishing gradients (called barren plateaus (BPs)), (2) exponential cost concentration about the mean, and (3) the exponential narrowness of minima (called narrow gorges). Here we analytically prove that these three phenomena occur together, i.e., when one occurs then so do the other two. A key implication of this result is that one can numerically diagnose BPs via cost differences rather than via the computationally more expensive gradients. More broadly, our work shows that quantum mechanics rules out certain cost landscapes (which otherwise would be mathematically possible), and hence our results could be interesting from a quantum foundations perspective.
An advanced solid-state power amplifier that can generate an output power of as much as 17 W at a design operating frequency of 8.4 GHz has been designed and constructed as a smaller, lighter, less expensive alternative to traveling-wave-tube X-band amplifiers and to prior solid-state X-band power amplifiers of equivalent output power. This amplifier comprises a monolithic microwave integrated circuit (MMIC) amplifier module and a power-converter module integrated into a compact package (see Figure 1). The amplifier module contains an input variable-gain amplifier (VGA), an intermediate driver stage, a final power stage, and input and output power monitors (see Figure 2). The VGA and the driver amplifier are 0.5-m GaAs-based metal semiconductor field-effect transistors (MESFETs). The final power stage contains four parallel high-efficiency, GaAs-based pseudomorphic high-electron-mobility transistors (PHEMTs). The gain of the VGA is voltage-variable over a range of 10 to 24 dB. To provide for temperature compensation of the overall amplifier gain, the gain-control voltage is generated by an operational-amplifier circuit that includes a resistor/thermistor temperature-sensing network. The driver amplifier provides a gain of 14 dB to an output power of 27 dBm to drive the four parallel output PHEMTs, each of which is nominally capable of putting out as much as 5 W. The driver output is sent to the input terminals of the four parallel PHEMTs through microstrip power dividers; the outputs of these PHEMTs are combined by microstrip power combiners (which are similar to the microstrip power dividers) to obtain the final output power of 17 W.
Many critical infrastructures depend on the reliability of electronic circuits, whose health depends on the values of internal circuit elements that degrade over time. It is therefore important to estimate the values of internal circuit elements from external measurements and monitor them for changes. The challenge to doing so is that, typically, the internal voltages and currents are not accessible for measurement. Prior work on internal circuit element monitoring uses data obtained from sensors placed inside the circuit or requires additional circuitry to be added to the given system, both of which are undesirable. We propose a new multi-harmonic frequency-domain based system identification method that is non-intrusive. It exploits the latent non-idealities already present in the system, specifically harmonics in the measured input and output signals. We show how sensitivity analysis can be used to both assess the accuracy of the method as well as to optimize the choice of harmonics to use. We use as a motivation and illustrative example the problem of determining the equivalent series resistance and capacitance in a class of dc-link capacitance circuits in Adjustable Speed Drives. We assess the performance of this method using simulations, and establish its validity by experimental results.
We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 uW and 10.4 uW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16 x16 pixel matrix.