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At least 325 records · Page 18
All sourcesNASA NTRSDOE OSTI
NASA NTRSDate not supplied

Hard Fault Protection for a Silicon Carbide-Based Aerospace Motor Drive

Due to increasingly high DC link voltages and further advancements in the current density of silicon carbide (SiC) MOSFETs, it has become evident that conventional IGBT protection methods are not sufficient to protect these devices from overcurrent during low-inductance fault events. The use of an air core Rogowski coil topology was explored to see if it could mitigate these hard fault events. The design of this circuit resulted in safe shutdown of a low impedance phase-tophase fault, tested up to DC link voltages of 1 kV.

High Voltage↗
DOE OSTI2025

Monolithic AlScN/SiC phononic waveguides for scalable acoustoelectric and quantum devices

Unlike conventional surface acoustic wave devices, phononic waveguide systems enable higher circuit density and stronger strain and piezoelectric fields, making them promising for advanced acoustoelectric and quantum applications. One such material system for generating and guiding phonons at gigahertz frequencies is AlScN on SiC, which can be synthesized by sputter depositing AlScN directly onto SiC wafers. The AlScN on the SiC platform allows for tightly vertically-confined acoustic modes with high electromechanical coupling, high speed of sound, and simple fabrication of strip and rib waveguides. Until now, this system has only been studied as a slab waveguide platform, i.e., without any lateral waveguiding. Here, we demonstrate a two-dimensionally confined phononic architecture in AlScN on SiC that supports guided modes at 2.95 and 4.05 GHz. These modes exhibit strong electromechanical coupling coefficients (k 2 = 4.27%) and propagation losses on the order of 10 dB/mm. Furthermore, this architecture is well-suited for phononic routing and power-efficient active or nonlinear devices such as amplifiers, mixers, and oscillators, and is compatible with the integration of quantum systems, including vacancy centers, charge carriers, photons, and spins, either embedded in SiC or heterogeneously integrated on the surface.

Electrical components↗
DOE OSTI2023

Adroit Materials Final Scientific/Technical Report kV-class GaN-based Junction Barrier Schottky diodes using ion implantation

The primary aim of this research was to develop GaN-based Junction Barrier Schottky (JBS) diodes using an innovative ion implantation process previously established in ARPA-E funded projects. The central focus of our proposed technology revolves around selective area p-type doping, accomplished through the implantation of Mg ions. This approach builds upon our successes in the ARPA-E PNDIODES program, advancing towards commercial device integration. Selective area p-doping plays a pivotal role in realizing the next generation of GaN-based power devices, capable of significantly reducing the carbon footprint in the United States by several million tons. While ion implantation is a well-established technique for achieving selective area doping in SiC and Si materials, its feasibility in GaN had not been demonstrated until now. To fabricate high voltage GaN JBS diodes, we initially created thick n-type drift layers with high carrier concentrations ranging from 5×1015 cm-3 to 2×1016 cm-3 and very high mobilities. Subsequently, Mg ions were selectively implanted to form p-type islands within the n-type drift layer. To reduce electric field crowding at the edge of the diode and to achieve high breakdown voltage, junction edge termination (JTE) and floating field rings (FFRs) were formed using Mg implantation. A high temperature, high-pressure post-implantation annealing process was carried out to activate the implanted Mg ions. As a result, we were able to demonstrate GaN JBS diodes with a breakdown voltage of 915 V and an on-resistance of 0.6 mΩ·cm2. These diodes exhibited a forward bias current density of 1 kA/cm2 at 1.5 V. Subsequently, we achieved GaN JBS diodes with a remarkable breakdown voltage of 1900 V and an on-resistance of 1.9 mΩ·cm2, capable of sustaining a forward bias current density of 0.5 kA/cm2 at 1.5 V. Importantly, the ON and OFF state performance of these GaN JBS diodes surpassed that of Si and SiC-based power diodes reported in existing literature. Lastly, we successfully grew 60 μm thick GaN:Si layers using HVPE with a carrier concentration of approximately 3 to 5×1015 cm-3. Based on simulation and empirical data these devices represent 5 kV GaN JBS power diodes, leveraging the developed processes in this project.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Wide Band Gap Chalcogenide Semiconductors

Wide band gap semiconductors are essential for today’s electronic devices and energy applications because of their high optical transparency, controllable carrier concentration, and tunable electrical conductivity. The most intensively investigated wide band gap semiconductors are transparent conductive oxides (TCOs), such as tin-doped indium oxide (ITO) and amorphous In–Ga–Zn–O (IGZO), used in displays and solar cells, carbides (e.g., SiC) and nitrides (e.g., GaN) used in power electronics, and emerging halides (e.g., γ-CuI) and 2D electronic materials (e.g., graphene) used in various optoelectronic devices. Compared to these prominent materials families, chalcogen-based (Ch = S, Se, Te) wide band gap semiconductors are less heavily investigated but stand out because of their propensity for p-type doping, high mobilities, high valence band positions (i.e., low ionization potentials), and broad applications in electronic devices such as CdTe solar cells. This manuscript provides a review of wide band gap chalcogenide semiconductors. First, we outline general materials design parameters of high performing transparent semiconductors, as well as the theoretical and experimental underpinnings of the corresponding research methods. We proceed to summarize progress in wide band gap (EG > 2 eV) chalcogenide materials—namely, II–VI MCh binaries, CuMCh 2 chalcopyrites, Cu 3 MCh 4 sulvanites, mixed-anion layered CuMCh(O,F), and 2D materials—and discuss computational predictions of potential new candidates in this family, highlighting their optical and electrical properties. Then, we finally review applications—for example, photovoltaic and photoelectrochemical solar cells, transistors, and light emitting diodes—that employ wide band gap chalcogenides as either an active or passive layer. Overall, by examining, categorizing, and discussing prospective directions in wide band gap chalcogenides, this Review aims to inspire continued research on this emerging class of transparent semiconductors and thereby enable future innovations for optoelectronic devices.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
NASA NTRS1976

Silicon ribbon growth by a capillary action shaping technique

The technique of silicon ribbon growth by the capillary action shaping is assessed for applicability to photovoltaic power device material. Ribbons 25 mm in width and up to 0.5 m in length have been grown from SiC dies, and some new characteristics of growth from such dies have been identified. Thermal modifiers have been studied, and systems were developed which reduce the frozen-in stress un silicon ribbons and improve the thickness uniformity of the ribbons. Preliminary spreading resistance measurements indicate that neither surface striations nor twin boundaries give rise to appreciable resistivity variations, but that large-angle grain boundaries cause local resistivity increases of up to 200%.

Schwuttke, G. H.↗
DOE OSTI2025

Epitaxial integration of superconducting nitrides with cubic GaN

Epitaxial combination of transition metal nitrides and group III-nitrides holds significant potential for novel device architectures, given their wide array of properties and similar lattice constants. However, the mixture of hexagonal and cubic crystals limits structural quality and has stymied development. This work will discuss the molecular beam epitaxy synthesis of metastable cubic GaN on 3C-SiC templates and its integration with cubic ZrN and NbN superconductors in single and multilayer heterostructures. The fully cubic nature of GaN and the epitaxial nature of all layers are confirmed via in situ and ex situ techniques. The electrical transport properties of transition metal nitrides on cubic GaN (001) are compared to those grown directly on 3C-SiC (001) and c-plane hexagonal GaN templates. The determination of a similar growth window for cubic wide-bandgap and superconducting metal nitrides creates a platform for new epitaxial device architectures and potential applications in metamaterials, quantum information science, and condensed matter physics.

Condensed matter physics↗
NASA NTRS2019

Modeling and Mitigation of Multi-Loops Related Device Overvoltage in Three Level Active Neutral Point Clamped Converter

This paper establishes an analytical model for the device drain-source overvoltage related to the two loops in three level active neutral point clamped (3L-ANPC) converters. Taking into account the non-linear device output capacitance, two commonly used modulations are investigated in detail. The result shows that the line switching frequency device usually has higher overvoltage, and the switching speed of the high switching frequency device is not strongly influenced by the multiple loops. By keeping the non-active clamping switch off, the effect of the non-linear device output capacitance can be significantly mitigated, which helps reduce the overvoltage. Moreover, the loop inductance can be reduced with vertical loop layout and magnetic cancellation in PCB and busbar design. A 500 kVA 3L-ANPC converter using SiC MOSFETs is built and tested. The experimental results validate the overvoltage model of the two modulations as well as the busbar design. With the non-active clamping switch off, the overvoltage of both the high and line switching frequency devices is significantly reduced, which helps achieve higher switching speed.

Model↗
DOE OSTI2024

Analysis of dislocation configurations in SiC crystals through X-ray topography aided by ray tracing simulations

Silicon carbide as a wide bandgap semiconductor is of great research interest for its widespread deployment in a range of electronic and optoelectronic devices, particularly in power electronics. However, defects in silicon carbide crystals are still major concerns that is hampering the development of high-performance devices. X-ray topography, particularly using the synchrotron beam has been instrumental in characterizing and analyzing defect configurations in silicon carbide crystals to optimize crystal growth as well as understand the effect of defects on device performance. Here, in recent years, the use of ray-tracing simulation technique based on the orientation contrast mechanism to simulate contrast of defects observed on actual X-ray topographs has proven to be an effective approach to investigate the nature of crystallographic defects in various semiconductors. This review discusses the principle of ray-tracing simulation and its application and modifications to incorporate the effects of surface relaxation and photoelectric absorption to better simulate different dislocations observed in 4H–SiC as well as 6H–SiC crystals of various orientations. The adaptation to weak beam topography and plane wave topography is also discussed. The application of ray-tracing simulation in dislocation characterization of silicon carbide of different polytypes is systematically reviewed including different types of dislocations observed in both off-axis wafers and axial-sliced samples through synchrotron X-ray topography under various beam conditions, recording geometries and reflections. The result of ray-tracing simulation is further utilized in other studies including the investigation of effective penetration depth of all types of dislocations lying on the basal plane on grazing-incidence X-ray topography.

Engineering↗
NASA NTRS2001

Packaging Technology Developed for High-Temperature Silicon Carbide Microsystems

High-temperature electronics and sensors are necessary for harsh-environment space and aeronautical applications, such as sensors and electronics for space missions to the inner solar system, sensors for in situ combustion and emission monitoring, and electronics for combustion control for aeronautical and automotive engines. However, these devices cannot be used until they can be packaged in appropriate forms for specific applications. Suitable packaging technology for operation temperatures up to 500 C and beyond is not commercially available. Thus, the development of a systematic high-temperature packaging technology for SiC-based microsystems is essential for both in situ testing and commercializing high-temperature SiC sensors and electronics. In response to these needs, researchers at Glenn innovatively designed, fabricated, and assembled a new prototype electronic package for high-temperature electronic microsystems using ceramic substrates (aluminum nitride and aluminum oxide) and gold (Au) thick-film metallization. Packaging components include a ceramic packaging frame, thick-film metallization-based interconnection system, and a low electrical resistance SiC die-attachment scheme. Both the materials and fabrication process of the basic packaging components have been tested with an in-house-fabricated SiC semiconductor test chip in an oxidizing environment at temperatures from room temperature to 500 C for more than 1000 hr. These test results set lifetime records for both high-temperature electronic packaging and high-temperature electronic device testing. As required, the thick-film-based interconnection system demonstrated low (2.5 times of the room-temperature resistance of the Au conductor) and stable (decreased 3 percent in 1500 hr of continuous testing) electrical resistance at 500 C in an oxidizing environment. Also as required, the electrical isolation impedance between printed wires that were not electrically joined by a wire bond remained high (greater than 0.4 GW) at 500 C in air. The attached SiC diode demonstrated low (less than 3.8 W/mm2) and relatively consistent dynamic resistance from room temperature to 500 C. These results indicate that the prototype package and the compatible die-attach scheme meet the initial design standards for high-temperature, low-power, and long-term operation. This technology will be further developed and evaluated, especially with more mechanical tests of each packaging element for operation at higher temperatures and longer lifetimes.

Chen, Liang-Yu↗
DOE OSTI2023

The BiDFET Device and Its Impact on Converters

The matrix converter topology for direct ac-to-ac conversion offers elimination of the bulky and unreliable D.C. link capacitors used in the popular Voltage-Source Inverter (VSI) with a front-end rectifier. The resulting more compact and higher efficiency implementation is a desirable solution for a wide variety of applications, such as photovoltaic energy generation, motor drives, and energy storage systems. The development of matrix converters has been hampered by the lack of availability of commercial bidirectional power switches with the ability to block high voltages in the first and third quadrants, carry on state current in both quadrants with low voltage drop, exhibit large forward-biased safe-operating-area (FBSOA), and low switching power losses. Consequently, many implementations have been tried in the past using discrete devices, as listed in Table I. Two implementations utilize commonly available asymmetric blocking IGBTs, while two cases make use of SiC power MOSFETs. They generally have a large parts count (4-6 individual switches) that occupies significant space in the converter where multiple bi-directional switches are required. They also have a high on-state voltage drop that degrades efficiency. As a result, one implementation utilizes symmetric blocking IGBT to achieve a low parts count (2), but its switching losses are unacceptably high.

42 ENGINEERING↗
DOE OSTI2020

Estimation, Minimization, and Validation of Commutation Loop Inductance for a 135-kW SiC EV Traction Inverter

With growing interests in low inductance SiC based power module packaging, it is vital to focus on system level design aspects to facilitate easy integration of the modules and reap system level benefits. To effectively utilize the low inductance modules, busbar and interconnects should also be designed with low stray inductances. A wholistic investigation of the flux path and flux cancellations in the module-busbar assembly which as differentially coupled series inductors is thus mandatory for a system level design. This work presents a busbar design which can be adopted to effectively integrate the CREE’s low inductance 1.2 kV/1.7 kV SiC power modules. The paper also proposes a novel measurement technique to measure the inductance of the modulebusbar assembly as a whole rather than deducing it from individual components. The inductance of the overall commutation loop of the inverter which encompasses the SiC power module, interconnects and PCB busbar have been estimated using finite element analysis (FEA). Furthermore, insights gained from FEA provided the guidelines to decide on the placement of the decoupling capacitors in the busbar to minimize the overall commutation loop inductance from 12.8 nH to 7.4 nH which resulted in significant reduction in the device voltage overshoot. The simulation results have been validated through measurements using an impedance analyzer with less than 5% difference between extracted loop inductance from FEA and measurements. The bus bar design study and the measurement technique discussed in this paper, can be easily extended to other power module packages. Finally, the 135 kW inverter has been compared to a similar highpower inverter utilizing a laminated busbar to highlight the performance of the former.

42 ENGINEERING↗
NASA NTRS2021

Practical SiC JFET-R Analog Integrated Circuit Design for Extreme Environment Applications

Silicon carbide (SiC) junction field effect transistor and SiC resistor (SiC JFET-R) integrated circuits(ICs) have uniquely demonstrated prolonged operation above 450 °C that promises significant operational improvements to a variety of NASA missions. However, the SiC epiwafers used to fabricate these ICs suffer from epi-growth process immaturity that imparts large and systematic spreads in JFET threshold voltages as a function of the device distance from the center on the wafer. Furthermore, the unprecedently wide range of intended application operating temperatures (in many cases over 600 °C wide) imparts as much as 5-fold change in JFET bias currents. This Technical Memorandum documents methods by which both temperature and radius associated JFET electrical parameter variances can be adequately eliminated, or even exploited in JFET-R circuit designs. Full analog circuit examples, including operational amplifiers, and SPICE simulations across experimentally documented SiC JFET parameter extremes are given to illustrate the efficacy of these methods. The reader may use the examples in this memorandum as either an end point, to get a desired analog signal conditioning design into hardware implemented in SiC JFET-R ICs, or as a basis point from which to derive further improvement.

Michael J Krasowski↗
DOE OSTI2020

Design Considerations for High-Voltage Insulated Gate Drive Power Supply for 10-kV SiC MOSFET Applied in Medium-Voltage Converter

High-performance gate drive power supply (GDPS) plays a crucial role in ensuring the reliability and safety of the gate driver for power semiconductor devices. This article focuses on the design of a high-voltage-insulated GDPS for the 10-kV silicon carbide MOSFET in medium-voltage (MV) application. Design considerations, including insulation scheme, high-voltage-insulated transformer design, and load voltage regulation scheme, are proposed. In addition, the performance of the secondary-side-regulated (SSR) GDPS and that of the primary-side-regulated (PSR) GDPS are compared for several aspects, including interwinding capacitance, load voltage regulation rate, conversion efficiency, and hardware complexity. Finally, an SSR GDPS and a PSR GDPS, with an insulation voltage of 20 kV, are built in the lab. Furthermore, the test results demonstrate that the PSR GDPS is more preferable because of lower interwinding capacitance, lower load voltage regulation rate, higher conversion efficiency, and simpler control circuit.

42 ENGINEERING↗
DOE OSTI2025

Creating and Probing Large Gap 2D Topological Insulators for Quantum Computing (Final Report)

Research under this award focused on experimental and theoretical efforts in developing and characterizing 2D topological insulators (TIs). Key areas of investigation included materials synthesis, device fabrication and characterization, and theoretical advancements. The team synthesized ZrTe 5 , a material with potential for TI phases. Additionally, the team pursued the synthesis of elemental thin films like Indene and Bismuthene, known for their large TI gaps. Indene was successfully stabilized on SiC. Another approach involved stacking and twisting transition metal dichalcogenides (TMDs) to engineer desired TI band structures. On the theoretical front, advancements made under this award predicted remarkable topological properties in twisted WSe2 bilayers, motivating experimental efforts to realize these states. Regarding device fabrication and characterization, significant progress was made in reducing contact resistance, crucial for reliable transport measurements. Contactless Pulsed Tunneling Spectroscopy (CPTS) was employed to study the electronic properties of WTe 2 and WSe 2 . However, challenges in device fabrication and electrode material selection hampered efforts to obtain desired spectra. Ancillary work, utilizing pulsed electrical methods, on the study of sliding ferroelectrics yielded impactful results demonstrating high speed operation and lack of degradation of devices after many billions of cycles.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2022

Novel Source Development for Focused Ion Beam Implantation and Irradiation [Slides]

We have demonstrated focused ion implantation for fabrication of single atom devices and nanofabrication. This is a viable solution for prototyping - fast and easy! There is on-going work in diamond, SiN, SiC, hBN, GaN, AlGan, etc. A new liquid metal alloy ion source development is on-going. There is a pathway towards deterministic defect centers in wide bandgap materials using FIB implantation.

43 PARTICLE ACCELERATORS↗
NASA NTRS1993

Silicon carbide semiconductor technology for high temperature and radiation environments

Viewgraphs on silicon carbide semiconductor technology and its potential for enabling electronic devices to function in high temperature and high radiation environments are presented. Topics covered include silicon carbide; sublimation growth of 6H-SiC boules; SiC chemical vapor deposition reaction system; 6H silicon carbide p-n junction diode; silicon carbide MOSFET; and silicon carbide JFET radiation response.

Matus, Lawrence G.↗
NASA NTRS2001

Fabrication of Very High Efficiency 5.8 GHz Power Amplifiers using AlGaN HFETs on SiC Substrates for Wireless Power Transmission

For wireless power transmission using microwave energy, very efficient conversion of the DC power into microwave power is extremely important. Class E amplifiers have the attractive feature that they can, in theory, be 100% efficient at converting, DC power to RF power. Aluminum gallium nitride (AlGaN) semiconductor material has many advantageous properties, relative to silicon (Si), gallium arsenide (GaAs), and silicon carbide (SiC), such as a much larger bandgap, and the ability to form AlGaN/GaN heterojunctions. The large bandgap of AlGaN also allows for device operation at higher temperatures than could be tolerated by a smaller bandgap transistor. This could reduce the cooling requirements. While it is unlikely that the AlGaN transistors in a 5.8 GHz class E amplifier can operate efficiently at temperatures in excess of 300 or 400 C, AlGaN based amplifiers could operate at temperatures that are higher than a GaAs or Si based amplifier could tolerate. Under this program, AlGaN microwave power HFETs have been fabricated and characterized. Hybrid class E amplifiers were designed and modeled. Unfortunately, within the time frame of this program, good quality HFETs were not available from either the RSC laboratories or commercially, and so the class E amplifiers were not constructed.

Sullivan, Gerry↗