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At least 325 records · Page 18

A solid-state digital temperature recorder for space use

A solid-state, digital, temperature recorder has been developed for use in space experiments. The recorder is completely self-contained and includes a temperature sensor; all necessary electronics for signal conditioning, processing, storing, control and timing; and a battery power supply. No electrical interfacing with the particular spacecraft on which the unit is used is required. The recorder is small, light, and sturdy, and has no moving parts. It uses only biocompatible materials and has passed vibration and shock spaceflight qualification tests. The unit is capable of storing 2048, -10 to +45 C, 8-bit temperature measurements taken at intervals selectable by factors of 2 from 1.875 to 240 min; data can be retained for at least 6 months. The basic recorder can be simplified to accommodate a variety of applications by adding memory to allow more data to be recorded, by changing the front end to permit measurements other than temperature to be made, and by using different batteries to realize various operating periods. Stored flight data are read out from the recorder by means of a ground read-out unit.

Westbrook, R. M.↗

Climatespark: an In-Memory Distributed Computing Framework for Big Climate Data Analytics

The unprecedented growth of climate data creates new opportunities for climate studies, and yet big climate data pose a grand challenge to climatologists to efficiently manage and analyze big data. The complexity of climate data content and analytical algorithms increases the difficulty of implementing algorithms on high performance computing systems. This paper proposes an in-memory, distributed computing framework, ClimateSpark, to facilitate complex big data analytics and time-consuming computational tasks. Chunking data structure improves parallel I/O efficiency, while a spatiotemporal index is built for the chunks to avoid unnecessary data reading and preprocessing. An integrated, multi-dimensional, array-based data model (ClimateRDD) and ETL operations are developed to address big climate data variety by integrating the processing components of the climate data lifecycle. ClimateSpark utilizes Spark SQL and Apache Zeppelin to develop a web portal to facilitate the interaction among climatologists, climate data, analytic operations and computing resources (e.g., using SQL query and Scala/Python notebook). Experimental results show that ClimateSpark conducts different spatiotemporal data queries/analytics with high efficiency and data locality. ClimateSpark is easily adaptable to other big multiple- dimensional, array-based datasets in various geoscience domains.

Hu, Fei↗

Memory Circuit Fault Simulator

Spacecraft are known to experience significant memory part-related failures and problems, both pre- and postlaunch. These memory parts include both static and dynamic memories (SRAM and DRAM). These failures manifest themselves in a variety of ways, such as pattern-sensitive failures, timingsensitive failures, etc. Because of the mission critical nature memory devices play in spacecraft architecture and operation, understanding their failure modes is vital to successful mission operation. To support this need, a generic simulation tool that can model different data patterns in conjunction with variable write and read conditions was developed. This tool is a mathematical and graphical way to embed pattern, electrical, and physical information to perform what-if analysis as part of a root cause failure analysis effort.

Sheldon, Douglas J.↗

Three-Dimensional Magnetic-Bubble Memory System

Proposed magnetic-bubble memory system includes stack of two-dimensional memory modules. Design enables overall storage density of system to be greater than prior magnetic-bubble memories. Provides nonvolatile storage, with readout access times in millisecond range. Has partly parallel input/output configuration supporting high-performance computing. Also relatively invulnerable to damage by ionizing radiation. Binary data, as represented by direction of magnetization of magnetic bubbles, reads out via Faraday effect.

Katti, Romney R.↗

Development of a software interface for optical disk archival storage for a new life sciences flight experiments computer

The current Life Sciences Laboratory Equipment (LSLE) microcomputer for life sciences experiment data acquisition is now obsolete. Among the weaknesses of the current microcomputer are small memory size, relatively slow analog data sampling rates, and the lack of a bulk data storage device. While life science investigators normally prefer data to be transmitted to Earth as it is taken, this is not always possible. No down-link exists for experiments performed in the Shuttle middeck region. One important aspect of a replacement microcomputer is provision for in-flight storage of experimental data. The Write Once, Read Many (WORM) optical disk was studied because of its high storage density, data integrity, and the availability of a space-qualified unit. In keeping with the goals for a replacement microcomputer based upon commercially available components and standard interfaces, the system studied includes a Small Computer System Interface (SCSI) for interfacing the WORM drive. The system itself is designed around the STD bus, using readily available boards. Configurations examined were: (1) master processor board and slave processor board with the SCSI interface; (2) master processor with SCSI interface; (3) master processor with SCSI and Direct Memory Access (DMA); (4) master processor controlling a separate STD bus SCSI board; and (5) master processor controlling a separate STD bus SCSI board with DMA.

Bartram, Peter N.↗

Coherent Control over Nuclear Hyperpolarization Using an Optically Initializable Chromophore-Radical System

Chromophore radicals (CR) are emerging as important components for molecular quantum information science (QIS), especially in the context of quantum sensing. Here, we demonstrate that the optically hyperpolarized electrons in a 1,6,7,12-tetrakis(4-tert-butylphenoxy)-perylene-3,4,9,10-bis(dicarboximide) (tpPDI) covalently linked to a partially deuterated 1,3-bis(diphenylene)-d 16 -2-phenylallyl radical (BDPA-d 16 ) can be coherently manipulated via pulsed dynamic nuclear polarization (DNP) methods to transfer polarization to nuclear spins and back. Under light illumination at 85 K, electron hyperpolarization in BDPA is enhanced 2.1- to 2.4-fold over thermal polarization and lasts for more than 100 ms. By applying nuclear orientation via electron spin-locking (NOVEL) DNP, this optically amplified electron hyperpolarization was successfully transferred to a 1 H nuclear spin within the CR system and efficiently returned to the electron spin for readout via reverse-NOVEL. The NOVEL transfer efficiency of 65% amounts to a 688-fold nuclear spin hyperpolarization of the target nuclear spin, considering the 2.1-fold electron spin hyperpolarization. This reversible coherent manipulation of hyperpolarization transfer highlights the utility of CR systems to initialize and read out nuclear spin states in a disordered matrix at moderate cryogenic temperatures. Coupled with CRs’ environmental compatibility, tunability, and precise state initialization, these results highlight the promising role of nuclear spins in CRs for QIS applications, including quantum sensing and memory.

charge transfer↗

Persistent Memory Object Storage and Indexing for Scientific Computing

This paper presents Mosiqs, a persistent memory object storage framework with metadata indexing and querying for scientific computing. We design Mosiqs based on the key idea that memory objects on shared PM pool can live beyond the application lifetime and can become the sharing currency for applications and scientists. Mosiqs provides an aggregate memory pool atop an array of persistent memory devices to store and access memory objects. Mosiqs uses a lightweight persistent memory key-value store to manage the metadata of memory objects such as persistent pointer mappings, which enables memory object sharing for effective scientific collaborations. Mosiqs is implemented atop PMDK. We evaluate the proposed approach on many-core server with an array of real PM devices. The preliminary evaluation confirms a 100% improvement for write and 30% in read performance against a PM-aware file system approach.

Khan, Awais↗

Estimation of the time for steam generator trip due to cyber intrusions

The time required to trip a pressurized water reactor (PWR) by inserting malicious signals into its steam generator (SG) control system has been studied using the Generic PWR (GPWR) Simulator. A semi-analytical model is developed to approximately reproduce the simulator response and understand the dynamics of the control unit. A series of two proportional-integral controllers determines control action according to preset constants, the readings from the feedwater level sensor, and those from feedwater and steam flowrate transmitters. It is observed that the most important factor that determines whether a trip will occur is how much additional water is added to or withheld from the SG over time compared to normal operating conditions. In order to determine the effects of control action on the SG, changes in mass inventory are considered. This approach models the SG water level as a function of mass inventory and has a backward temporal memory. A Python interface is developed for the GPWR framework to automatically simulate different spoofing scenarios and post-process the related data. We observe that the trip times predominantly depend on flow mismatch and/or level errors. Controller parameters, including the integral time and gain constants, either speed up or slow down the rate of progression to a trip setpoint but do not cause a trip by themselves. The reactor can trip on a high-level signal when the reading crosses above 78%, increased from its reference level of 57%, or a low-level reading when it is below 25%. The present results show roughly how long the operators would have to respond to an attack, given a specific set of spoofing signals within the issue space analyzed. Furthermore, we have generated a simple surface by fitting a combination of exponential functions to the data obtained from the GPWR Simulator. In general, trips on a low level have been observed to occur faster than those on a high level.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

Design of Low Power CMOS Read-Out with TDI Function for Infrared Linear Photodiode Array Detectors

A new low voltage CMOS infrared readout circuit using the buffer-direct injection method is presented. It uses a single supply voltage of 1.8 volts and a bias current of 1uA. The time-delay integration technique is used to increase the signal to noise ratio. A current memory circuit with faulty diode detection is used to remove dark current for background compensation and to disable a photodiode in a cell if detected as faulty. Simulations are shown that verify the circuit that is currently in fabrication in 0.5ym CMOS technology.

Vizcaino, Paul↗

Sharing tuples across independent coordination namespace systems

A system and method for federating a tuple storage database across multiple coordinated namespace (CNS) extended memory storage systems allowing the sharing of tuples and tuple data across independent systems. The method provides a federation service for multiple coordination namespace systems. The method retrieves a tuple from connected independent CNS systems wherein a local CNS Controller sends a read request to the local gatekeeper to retrieve a first tuple and creates a local pending remote record. The local gatekeeper at a requesting node sends a broadcast query to a plurality of remote gatekeepers for the tuple and Remote gatekeepers at remote nodes query in its local CNS for the tuple. The Local gatekeeper process at the requesting node receives results from a plurality of remote gatekeepers for the said tuple and selects one remote gatekeeper to receive the requested tuple and broadcasts a read for tuple data with selected gatekeeper.

Jacob, Philip↗

Accelerating Scientific Workflows on HPC Platforms with In Situ Processing

Scientific workflows drive most modern large-scale science breakthroughs by allowing scientists to define their computations as a set of jobs executed in a given order based on their data dependencies. Workflow management systems (WMSs) have become key to automating scientific workflows-executing computational jobs and orchestrating data transfers between those jobs running on complex high-performance computing (HPC) platforms. Traditionally, WMSs use files to communicate between jobs: a job writes out files that are read by other jobs. However, HPC machines face a growing gap between their storage and compute capabilities. To address that concern, the scientific community has adopted a new approach called in situ, which bypasses costly parallel filesystem I/O operations with faster in-memory or in-network communications. When using in situ approaches, communication and computations can be interleaved. In this work, we leverage the Decaf in situ dataflow framework to accelerate task-based scientific workflows managed by the Pegasus WMS, by replacing file communications with faster MPI messaging. We propose a new execution engine that uses Decaf to manage communications within a sub-workflow (i.e., set of jobs) to optimize inter-job communications. We consider two workflows in this study: (i) a synthetic workflow that benchmarks and compares file- and MPI-based communication; and (ii) a realistic bioinformatics workflow that computes mu-tational overlaps in the human genome. Experiments show that in situ communication can improve the bioinformatics workflow execution time by 22% to 30% compared with file communication. Our results motivate further opportunities and challenges for bridging traditional WMSs with in situ frameworks.

Decaf↗

Single event upset vulnerability of selected 4K and 16K CMOS static RAM's

Upset thresholds for bulk CMOS and CMOS/SOS RAMS were deduced after bombardment of the devices with 140 MeV Kr, 160 MeV Ar, and 33 MeV O beams in a cyclotron. The trials were performed to test prototype devices intended for space applications, to relate feature size to the critical upset charge, and to check the validity of computer simulation models. The tests were run on 4 and 1 K memory cells with 6 transistors, in either hardened or unhardened configurations. The upset cross sections were calculated to determine the critical charge for upset from the soft errors observed in the irradiated cells. Computer simulations of the critical charge were found to deviate from the experimentally observed variation of the critical charge as the square of the feature size. Modeled values of series resistors decoupling the inverter pairs of memory cells showed that above some minimum resistance value a small increase in resistance produces a large increase in the critical charge, which the experimental data showed to be of questionable validity unless the value is made dependent on the maximum allowed read-write time.

Kolasinski, W. A.↗

Notes on implementation of sparsely distributed memory

The Sparsely Distributed Memory (SDM) developed by Kanerva is an unconventional memory design with very interesting and desirable properties. The memory works in a manner that is closely related to modern theories of human memory. The SDM model is discussed in terms of its implementation in hardware. Two appendices discuss the unconventional approaches of the SDM: Appendix A treats a resistive circuit for fast, parallel address decoding; and Appendix B treats a systolic array for high throughput read and write operations.

Keeler, J. D.↗

Index grating lifetime in photorefractive GaAs

The index grating lifetime in liquid encapsulated Czochralski-grown undoped semi-insulating GaAs was measured using a beam coupling technique. The largest lifetime measure was about 8 s under a read beam intensity of 0.7 mW/sq cm with the grating periodicity being 0.63 microns. The measured value decreases to milliseconds as the read beam intensity and the grating periodicity increase to about 10 mW/sq cm and 4 microns, respectively. This range of grating lifetime in this material is adequate for its use in real-time spatial light modulators, reconfigurable beam steering devices, and dynamic memory elements, for optical computing. In addition, the results suggest that the lifetime is sensitive to residual imperfections in the crystal.

Cheng, Li-Jen↗

Concurrent conditions access across validity intervals in CMSSW

The CMS software system, known as CMSSW, has a generalized conditions, calibration, and geometry data products system called the EventSetup. The EventSetup caches results of reading or calculating data products based on the 'interval of validity', IOV, which is based on the time period for which that data product is appropriate. With the original single threaded CMSSW framework, updating only on an IOV boundary meant we only required memory for a single data product of a given type at any time during the program execution. In 2016 CMS transitioned to using a multi-threaded framework as away to save on memory during processing. This was accomplished by amortizing the memory cost of EventSetup data products across multiple concurrent events. To initially accomplish that goal required synchronizing event processing across IOV boundaries, thereby decreasing the scalability of the system. In this presentation we will explain how we used 'limited concurrent task queues' to allow concurrent IOVs while still being able to limit the memory utilized.

Dagenhart, David↗

Holographic recording materials development

The area of organic cis-trans photoisomerization systems for holographic memory applications was examined. Photochemical studies were made of stilbene, indigo, and thioindigo derivatives in solution and in a variety of polymer matrix materials, to optimize the photorefractive behavior of the chemical system as a whole. Lithium niobate was used to study the writing and reading efficiencies of thick phase holograms. Both phase-wave holograms and Fourier-transform holograms were employed, and a number of reconstruction techniques are discussed. The possibility of using cis-trans photoisomerization of appropriate organic chemicals as the basis for a holographic recording system is confirmed.

Source record↗

SpaceCube Version 1.5

SpaceCube 1.5 is a high-performance and low-power system in a compact form factor. It is a hybrid processing system consisting of CPU (central processing unit), FPGA (field-programmable gate array), and DSP (digital signal processor) processing elements. The primary processing engine is the Virtex- 5 FX100T FPGA, which has two embedded processors. The SpaceCube 1.5 System was a bridge to the SpaceCube 2.0 and SpaceCube 2.0 Mini processing systems. The SpaceCube 1.5 system was the primary avionics in the successful SMART (Small Rocket/Spacecraft Technology) Sounding Rocket mission that was launched in the summer of 2011. For SMART and similar missions, an avionics processor is required that is reconfigurable, has high processing capability, has multi-gigabit interfaces, is low power, and comes in a rugged/compact form factor. The original SpaceCube 1.0 met a number of the criteria, but did not possess the multi-gigabit interfaces that were required and is a higher-cost system. The SpaceCube 1.5 was designed with those mission requirements in mind. The SpaceCube 1.5 features one Xilinx Virtex-5 FX100T FPGA and has excellent size, weight, and power characteristics [4×4×3 in. (approx. = 10×10×8 cm), 3 lb (approx. = 1.4 kg), and 5 to 15 W depending on the application]. The estimated computing power of the two PowerPC 440s in the Virtex-5 FPGA is 1100 DMIPS each. The SpaceCube 1.5 includes two Gigabit Ethernet (1 Gbps) interfaces as well as two SATA-I/II interfaces (1.5 to 3.0 Gbps) for recording to data drives. The SpaceCube 1.5 also features DDR2 SDRAM (double data rate synchronous dynamic random access memory); 4- Gbit Flash for storing application code for the CPU, FPGA, and DSP processing elements; and a Xilinx Platform Flash XL to store FPGA configuration files or application code. The system also incorporates a 12 bit analog to digital converter with the ability to read 32 discrete analog sensor inputs. The SpaceCube 1.5 design also has a built-in accelerometer. In addition, the system has 12 receive and transmit RS- 422 interfaces for legacy support. The SpaceCube 1.5 processor card represents the first NASA Goddard design in a compact form factor featuring the Xilinx Virtex- 5. The SpaceCube 1.5 incorporates backward compatibility with the Space- Cube 1.0 form factor and stackable architecture. It also makes use of low-cost commercial parts, but is designed for operation in harsh environments.

Geist, Alessandro↗

Variation-Resilient FeFET-Based In-Memory Computing Leveraging Probabilistic Deep Learning

Reliability issues stemming from device level nonidealities of nonvolatile emerging technologies like ferroelectric field-effect transistors (FeFETs), especially at scaled dimensions, cause substantial degradation in the accuracy of in-memory crossbar-based AI systems. Here, in this work, we present a variation-aware design technique to characterize the device level variations and to mitigate their impact on hardware accuracy employing a Bayesian neural network (BNN) approach. An effective conductance variation model is derived from the experimental measurements of cycle-to-cycle (C2C) and device-to-device (D2D) variations performed on FeFET devices fabricated using 28 nm high-k metal gate technology. The variations were found to be a function of different conductance states within the given programming range, which sharply contrasts earlier efforts where a fixed variation dispersion was considered for all conductance values. Such variation characteristics formulated for three different device sizes at different read voltages were provided as prior variation information to the BNN to yield a more exact and reliable inference. Near-ideal accuracy for shallow networks (MLP5 and LeNet models) on the MNIST dataset and limited accuracy decline by ~3.8%–16.1% for deeper AlexNet models on CIFAR10 dataset under a wide range of variations corresponding to different device sizes and read voltages, demonstrates the efficacy of our proposed device-algorithm co-design technique.

97 MATHEMATICS AND COMPUTING↗