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At least 325 records · Page 18

Generic Spiking Architecture (GenSA)

Neuromorphic devices are a rapidly growing area of interest in industry, with machines in production by IBM and Intel, among others. These devices promise to reduce size, weight and power (SWaP) costs while increasing resilience and facilitating high- performance computing (HPC). Each device will favor some set of algorithms, but this relationship has not been thoroughly studied. The field of neuromorphic computing is so new that existing devices were designed with merely estimated use-cases in mind. To better understand the fit between neuromorphic algorithms and machines, a simulated machine can be configured to any point in the design space. This will identify better choices of devices, and perhaps guide the market in new directions. The design of a generic spiking machine generalizes existing examples while also looking forward to devices that haven't been built yet. Each parameter is specified, along the approach/mechanism by which the relevant component is implemented in the simulator.

97 MATHEMATICS AND COMPUTING↗

Dynamic Stabilization of Metastable States in Triple-Well Ferroelectric Sn 2 P 2 S 6

Polarization dynamics in ferroelectric materials is governed by the effective potential energy landscape of the order parameter. The unique aspect of ferroelectrics compared to many other transitions is the possibility of more than two potential wells, leading to complicated energy landscapes with new fundamental and functional properties. In this work, direct dynamic evidence is revealed of a triple-well potential in the metal thiophosphate Sn 2 P 2 S 6 compound using multivariate scanning probe microscopy combined with theoretical simulations. The key finding is that the metastable zero polarization state can be accessed through a gradual switching process and is stabilized over a broad range of electric fields. Simulations confirm that the observed zero polarization state originates from a kinetic stabilization of the nonpolar state of the triple-well, as opposed to domain walls. Dynamically, the triple-well of Sn 2 P 2 S 6 becomes equivalent to antiferroelectric hysteresis loops. Therefore, this material combines the robust and well-defined domain structure of a proper ferroelectric with dynamic hysteresis loops present in antiferroelectrics. Moreover, the triple-well enhances mem-capacitive effects in Sn 2 P 2 S 6 , which are forbidden for ideal double-well ferroelectrics. These findings provide a path to tunable electronic elements for beyond binary high-density computing devices and neuromorphic circuits based on dynamic properties of the triple-well.

36 MATERIALS SCIENCE↗

Accurate and Accelerated Neuromorphic Network Design Leveraging A Bayesian Hyperparameter Pareto Optimization Approach

Neuromorphic systems allow for extremely efficient hardware implementations for neural networks (NNs). In recent years, several algorithms have been presented to train spiking NNs (SNNs) for neuromorphic hardware. However, SNNs often provide lower accuracy than their artificial NNs (ANNs) counterparts or require computationally expensive and slow training/inference methods. To close this gap, designers typically rely on reconfiguring SNNs through adjustments in the neuron/synapse model or training algorithm itself. Nevertheless, these steps incur significant design time, while still lacking the desired improvement in terms of training/inference times (latency). Designing SNNs that can mimic the accuracy of ANNs with reasonable training times is an exigent challenge in neuromorphic computing. In this work, we present an alternative approach that looks at such designs as an optimization problem rather than algorithm or architecture redesign. We develop a versatile multiobjective hyperparameter optimization (HPO) for automatically tuning HPs of two state-of-the-art SNN training algorithms, SLAYER and HYBRID. We emphasize that, to the best of our knowledge, this is the first work trying to improve SNNs’ computational efficiency, accuracy, and training time using an efficient HPO. We demonstrate significant performance improvements for SNNs on several datasets without the need to redesign or invent new training algorithms/architectures. Our approach results in more accurate networks with lower latency and, in turn, higher energy efficiency than previous implementations. In particular, we demonstrate improvement in accuracy and more than 5× reduction in the training/inference time for the SLAYER algorithm on the DVS Gesture dataset. In the case of HYBRID, we demonstrate 30% reduction in timesteps while surpassing the accuracy of the state-of-the-art networks on CIFAR10. Further, our analysis suggests that even a seemingly minor change in HPs could change the accuracy by 5 - 6×.

Parsa, Maryam↗

Radiation-Induced Noise Resilience of Neuromorphic Architectures

Neuromorphic event-based networks use asynchronous time-dependent information to extract features from input data that can allow for edge-based distributed applications such as object recognition. The noise resilience properties of such networks, especially in the context of space applications, are yet to be explored. In this paper, we use the hierarchy of time surfaces (HOTS) algorithm, which is one of the neuromorphic algorithms, to understand the least and most resilient modules in a neuromorphic network. The HOTS algorithm relies on the computing of time surfaces that maps the temporal delays between neighboring pixels into normalized features that involve many computations that are also found in other neuromorphic networks such as exponential decays, distance computations, etcetera. We implemented HOTS on a Digilent PYNQ board with a Xilinx Zynq 7020 system on a chip, and we subjected the boards running the HOTS network inference to neutron radiation at the Los Alamos Neutron Science Center. Furthermore, we used simulation models from our previous similar experiments on the event-based sensor to create a neutron induced noise model to quantify the effect of this noise on the overall performance of the network. This experiment provides the preliminary measurements of the reliability of the HOTS algorithm and proposes methods to create a more reliable HOTS architecture in future spacecraft missions.

Engineering↗

AI-enhanced Codesign for Next-Generation Neuromorphic Circuits and Systems

This report details work that was completed to address the Fiscal Year 2022 Advanced Science and Technology (AS&T) Laboratory Directed Research and Development (LDRD) call for “AI-enhanced Co-Design of Next Generation Microelectronics.” This project required concurrent contributions from the fields of 1) materials science, 2) devices and circuits, 3) physics of computing, and 4) algorithms and system architectures. During this project, we developed AI-enhanced circuit design methods that relied on reinforcement learning and evolutionary algorithms. The AI-enhanced design methods were tested on neuromorphic circuit design problems that have real-world applications related to Sandia’s mission needs. The developed methods enable the design of circuits, including circuits that are built from emerging devices, and they were also extended to enable novel device discovery. We expect that these AI-enhanced design methods will accelerate progress towards developing next-generation, high-performance neuromorphic computing systems.

42 ENGINEERING↗

Neuromorphic heat transport effects in a molecular junction

Understanding energy transport at the nanoscale is an open and fundamental challenge in the molecular sciences with direct implications for the design of new electronics, computing devices, and materials. While nanoscale energy transport under steady-state conditions has been studied extensively, there is much less known about energy transport under time-dependent driving forces, particularly in the far-from-equilibrium regime. In this work, we use nonequilibrium molecular dynamics simulations and stochastic thermodynamics to investigate energy transport in a well-studied nanoscale system—a molecular junction—subjected to a time-periodic temperature gradient. The primary observation is that molecular junctions can exhibit heat transport hysteresis, a phenomenon in which the heat flux through a system depends not only on the instantaneous value of a time-dependent temperature bias but also on the temporal history of that bias. The presented findings illustrate that molecular junctions can exhibit the specific memory effect—heat transport hysteresis—that is essential for the design of thermal neuromorphic computers. This work elucidates a potential pathway toward the realization of such devices.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Nonvolatile Memories in Spiking Neural Network Architectures: Current and Emerging Trends

A sustainable computing scenario demands more energy-efficient processors. Neuromorphic systems mimic biological functions by employing spiking neural networks for achieving brain-like efficiency, speed, adaptability, and intelligence. Current trends in neuromorphic technologies address the challenges of investigating novel materials, systems, and architectures for enabling high-integration and extreme low-power brain-inspired computing. This review collects the most recent trends in exploiting the physical properties of nonvolatile memory technologies for implementing efficient in-memory and in-device computing with spike-based neuromorphic architectures.

42 ENGINEERING↗

Low-temperature emergent neuromorphic networks with correlated oxide devices

Significance Designing neuromorphic hardware for cryoelectronics is an important area of research as the field of computing paradigms beyond complementary metal-oxide-semiconductor (CMOS) progresses. Superconductivity and metal−insulator transitions are two of the most celebrated emergent, collective properties found in quantum materials such as strongly correlated oxides. Here, we present simulations of artificial neural networks that can be designed by combining superconducting devices (e.g. Josephson junctions) with Mott metal−insulator transition−based tunable resistor devices. Our simulations show that 1) neurons and synapses can be seamlessly created, 2) their functions can be tuned via learning, and 3) controlling disorder by incorporating light ions enables exponential multiplicity of states. The results open up directions for incorporating emergent behavior seen in condensed matter into hardware design for artificial intelligence.

97 MATHEMATICS AND COMPUTING↗

Electronic Bottleneck Suppression in Next‐Generation Networks with Integrated Photonic Digital‐to‐Analog Converters

Digital‐to‐analog converters (DAC) are indispensable functional units in signal processing instrumentation and wide‐band telecommunication links for both civil and military applications. As photonic systems are capable of high data throughput and low latency, an increasingly found system limitation stems from the required domain crossing such as digital to analog and electronic to optical. A photonic DAC implementation, in contrast, enables a seamless signal conversion with respect to both energy efficiency and short signal delay, often requiring bulky discrete optical components and electric–optic transformation, hence introducing inefficiencies. Herein, a novel coherent parallel photonic DAC concept along with a 4‐bit experimental prototype capable of performing this DAC without optic–electric–optic domain crossing is introduced. This new paradigm guarantees a linear intensity weighting among bits when operating at high sampling rates (50 GHz), featuring an exceptional sampling efficiency (> 100 GS ) and small footprint (≈1 mm 2 ) in an 8‐bit implementation. Importantly, this photonic DAC enables seamless interfaces of next‐generation data processing hardware with high relevance in data centers, task‐specific compute accelerators such as neuromorphic engines, and network edge processing applications.

Meng, Jiawei↗

Synaptic Functionality and Neuromorphic Information Processing in Membrane Ion Channel Junctions

The human brain performs complex memory and computational tasks with high energy efficiency by regulating ion transport through membrane channels. These signaling mechanisms have been inspiring the development of nanofluidic memristors that emulate synaptic behavior. Here, in this study, we describe a membrane ion channel synapse (MICS), constructed from aqueous droplets linked by gramicidin A channels, that achieves neuromorphic functionality. MICS exhibits memristive ion transport with hysteretic current–voltage behavior arising from voltage-dependent channel formation and ion transport dynamics. MICS emulates a range of synaptic behaviors including associative learning. We further demonstrate its application in reservoir computing by performing handwritten digit classification and tic-tac-toe game and explore the system parameters that improve the computational performance. This droplet-based biomimetic synapse offers a potentially scalable and energy-efficient platform for next-generation neuromorphic computing systems.

Droplet interface bilayer↗

DFSynthesizer: Dataflow-based Synthesis of Spiking Neural Networks to Neuromorphic Hardware

Spiking Neural Networks (SNNs) are an emerging computation model that uses event-driven activation and bio-inspired learning algorithms. SNN-based machine learning programs are typically executed on tile-based neuromorphic hardware platforms, where each tile consists of a computation unit called a crossbar, which maps neurons and synapses of the program. However, synthesizing such programs on an off-the-shelf neuromorphic hardware is challenging. This is because of the inherent resource and latency limitations of the hardware, which impact both model performance, e.g., accuracy, and hardware performance, e.g., throughput. We propose DFSynthesizer, an end-to-end framework for synthesizing SNN-based machine learning programs to neuromorphic hardware. The proposed framework works in four steps. First, it analyzes a machine learning program and generates SNN workload using representative data. Second, it partitions the SNN workload and generates clusters that fit on crossbars of the target neuromorphic hardware. Third, it exploits the rich semantics of the Synchronous Dataflow Graph (SDFG) to represent a clustered SNN program, allowing for performance analysis in terms of key hardware constraints such as number of crossbars, dimension of each crossbar, buffer space on tiles, and tile communication bandwidth. Finally, it uses a novel scheduling algorithm to execute clusters on crossbars of the hardware, guaranteeing hardware performance. We evaluate DFSynthesizer with 10 commonly used machine learning programs. Our results demonstrate that DFSynthesizer provides a much tighter performance guarantee compared to current mapping approaches.

Computer Science↗

Abisko: Deep codesign of an architecture for spiking neural networks using novel neuromorphic materials

The Abisko project aims to develop an energy-efficient spiking neural network (SNN) computing architecture and software system capable of autonomous learning and operation. The SNN architecture explores novel neuromorphic devices that are based on resistive-switching materials, such as memristors and electrochemical RAM. Equally important, Abisko uses a deep codesign approach to pursue this goal by engaging experts from across the entire range of disciplines: materials, devices and circuits, architectures and integration, software, and algorithms. Here, the key objectives of our Abisko project are threefold. First, we are designing an energy-optimized high-performance neuromorphic accelerator based on SNNs. This architecture is being designed as a chiplet that can be deployed in contemporary computer architectures and we are investigating novel neuromorphic materials to improve its design. Second, we are concurrently developing a productive software stack for the neuromorphic accelerator that will also be portable to other architectures, such as field-programmable gate arrays and GPUs. Third, we are creating a new deep codesign methodology and framework for developing clear interfaces, requirements, and metrics between each level of abstraction to enable the system design to be explored and implemented interchangeably with execution, measurement, a model, or simulation. As a motivating application for this codesign effort, we target the use of SNNs for an analog event detector for a high-energy physics sensor.

97 MATHEMATICS AND COMPUTING↗

Exponential Escape Rate of Filamentary Incubation in Mott Spiking Neurons

Mott materials such as vanadium oxides, when subject to a strong applied voltage, present an inhomogeneous insulator-to-metal transition with formation of metallic filaments within the insulating bulk. This property is enabling the development of compact and power-efficient neuromorphic devices known as Mott neurons. However, the nature of the transition has not been fully understood yet, as it may be attributed to different effects, including Joule self-heating and hot-carrier injection. Moreover, the experimental determination of the threshold voltage needed to induce the transition has proven to be challenging, as the transition becomes increasingly unpredictable when the threshold is approached. The physical understanding of these issues would not only deepen our understanding of Mott insulators, but would also be an important step toward the realization of neuromorphic devices based on such materials. In this work we use numerical simulations based on the Mott resistor network model to study the nature of the filament incubation and formation process. Here, we show that both electronic and thermal effects, in the form of current density focusing and Joule self-heating, respectively, contribute to the filamentary incubation and growth. Remarkably, we find that the percolation of the metallic filaments near the threshold is intrinsically stochastic, qualitatively similar to the familiar Arrhenius activated behavior and to the stochastic firing of biological neurons. More precisely, we characterize the filament percolation as a Poisson point process, which has the same probability distribution as mathematical models of neuronal firing with an exponential escape rate. Finally, we support the numerical simulation results by performing experiments in VO 2 that are in agreement with the exponential escape rate behavior. Thus, we establish a functionality of Mott insulators that opens a path toward implementing neuromorphic hardware with quantum materials.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Photoresponsive Rotaxanes Switch Lipid Bilayer Neuromorphic Behavior with Light

A rotaxane consisting of a macrocycle ring with two azobenzene units mechanically interlocked onto a bolaamphiphilic axle was incorporated into droplet interface bilayers (DIBs). The azobenzene groups on the ring underwent quasi-reversible, photoisomerization-induced cycling between 1-E and 1-Z configurations when irradiated with 370 and 467 nm light, respectively, enabling programmable access to different history-dependent electrical behaviors from the same membrane. In the 1-E configuration, bilayers exhibited type-IIactive memristance that coincided with increasingly elevated ionic conduction, associated with progressively enhanced bilayer permeability during voltage cycling. In the 1-Z configuration, bilayers displayed type-I, passive memcapacitive behavior, reflecting tighter lipid packing and reduced ionic permeability. Photoswitching also yielded a nonvolatile, photoresponsive memcapacitor that could be modulated repetitively with negligible loss, likely via reversible changes in membrane thickness. Concurrent ohmic leakage currents across the membrane were less than 0.3%. These results agree with previous studies with increasing membrane permeability using photoswitchable rotaxanes and provide new insights into the coupling between volatile and nonvolatile memcapacitance during photoisomerization. More broadly, they demonstrate a new strategy for the manipulation of neuromorphic behaviors in soft materials using light, with implications for brain-inspired computation and sensing.

droplet interface bilayers↗

Design-Technology Co-Optimization for NVM-based Neuromorphic Processing Elements

An emerging use-case of machine learning (ML) is to train a model on a high-performance system and deploy the trained model on energy-constrained embedded systems. Neuromorphic hardware platforms, which operate on principles of the biological brain, can significantly lower the energy overhead of a machine learning inference task, making these platforms an attractive solution for embedded ML systems. In this paper, we present a design-technology tradeoff analysis to implement such inference tasks on the processing elements (PEs) of a Non-Volatile Memory (NVM)-based neuromorphic hardware. Through detailed circuit-level simulations at scaled process technology nodes, we show the negative impact of technology scaling on the information-processing latency, which impacts the quality-of-service (QoS) of an embedded ML system. At a finer granularity, the latency inside a PE depends on 1) the delay introduced by parasitic components on its current paths, and 2) the varying delay to sense different resistance states of its NVM cells. Based on these two observations, we make the following three contributions. First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the QoS. Second, on the architecture front, we introduce isolation transistors within each PE to partition it into regions that can be individually power-gated, reducing both latency and energy. Finally, on the system-software front, we propose a mechanism to leverage the proposed technological and architectural enhancements when implementing a machine-learning inference task on neuromorphic PEs of the hardware. Evaluations with a recent neuromorphic hardware architecture show that our proposed design-technology co-optimization approach improves both performance and energy efficiency of machine-learning inference tasks without incurring high cost-per-bit.

42 ENGINEERING↗