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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 325 records · Page 18

Eight microprocessor-based instrument data systems in the Galileo Orbiter spacecraft

Instrument data systems consist of a microprocessor, 3K bytes of Read Only Memory and 3K bytes of Random Access Memory. It interfaces with the spacecraft data bus through an isolated user interface with a direct memory access bus adaptor, and/or parallel data from instrument devices such as registers, buffers, analog to digital converters, multiplexers, and solid state sensors. These data systems support the spacecraft hardware and software communication protocol, decode and process instrument commands, generate continuous instrument operating modes, control the instrument mechanisms, acquire, process, format, and output instrument science data.

Barry, R. C.↗

Systems and methods for reconfiguring input devices

A system includes an input device having first and second input members configured to be activated by a user. The input device is configured to generate activation signals associated with activation of the first and second input members, and each of the first and second input members are associated with an input function. A processor is coupled to the input device and configured to receive the activation signals. A memory coupled to the processor, and includes a reconfiguration module configured to store the input functions assigned to the first and second input members and, upon execution of the processor, to reconfigure the input functions assigned to the input members when the first input member is inoperable.

Lancaster, Jeff↗

Weaves as an Interconnection Fabric for ASIM's and Nanosatellites

Many of the micromachines under consideration require computer support, indeed, one of the appeals of this technology is the ability to intermix mechanical, optical, analog, and digital devices on the same substrate. The amount of computer power is rarely an issue, the sticking point is the complexity of the software required to make effective use of these devices. Micromachines are the nano-technologist's equivalent of 'golden screws'. In other words, they will be piece parts in larger assemblages. For example, a nano-satellite may be composed of stacked silicon wafers where each wafer contains hundreds to thousands of micromachines, digital controllers, general purpose computers, memories, and high-speed bus interconnects. Comparatively few of these devices will be custom designed, most will be stock parts selected from libraries and catalogs. The novelty will lie in the interconnections. For example, a digital accelerometer may be a component part in an adaptive suspension, a monitoring element embedded in the wrapper of a package, or a portion of the smart skin of a launch vehicle. In each case, this device must inter-operate with other devices and probes for the purposes of command, control, and communication. We propose a software technology called 'weaves' that will permit large collections of micromachines and their attendant computers to freely intercommunicate while preserving modularity, transparency, and flexibility. Weaves are composed of networks of communicating software components. The network, and the components comprising it, may be changed even while the software, and the devices it controls, are executing. This unusual degree of software plasticity permits micromachines to dynamically adapt the software to changing conditions and allows system engineers to rapidly and inexpensively develop special purpose software by assembling stock software components in custom configurations.

Gorlick, Michael M.↗

Integrating Commercial Off-The-Shelf (COTS) graphics and extended memory packages with CLIPS

This paper addresses the question of how to mix CLIPS with graphics and how to overcome PC's memory limitations by using the extended memory available in the computer. By adding graphics and extended memory capabilities, CLIPS can be converted into a complete and powerful system development tool, on the other most economical and popular computer platform. New models of PCs have amazing processing capabilities and graphic resolutions that cannot be ignored and should be used to the fullest of their resources. CLIPS is a powerful expert system development tool, but it cannot be complete without the support of a graphics package needed to create user interfaces and general purpose graphics, or without enough memory to handle large knowledge bases. Now, a well known limitation on the PC's is the usage of real memory which limits CLIPS to use only 640 Kb of real memory, but now that problem can be solved by developing a version of CLIPS that uses extended memory. The user has access of up to 16 MB of memory on 80286 based computers and, practically, all the available memory (4 GB) on computers that use the 80386 processor. So if we give CLIPS a self-configuring graphics package that will automatically detect the graphics hardware and pointing device present in the computer, and we add the availability of the extended memory that exists in the computer (with no special hardware needed), the user will be able to create more powerful systems at a fraction of the cost and on the most popular, portable, and economic platform available such as the PC platform.

Callegari, Andres C.↗

CMOS imager for pointing and tracking applications

Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

Pain, Bedabrata↗

Single Event Testing of SDRAM, DDR2 and DDR3 Memories

SEE test results are presented for SDRAM, DDR2, and DDR3. No tested devices exhibited SEL. SBUs were observed, but no MBUs were observed in data words. SEFI data were taken at low and high speed.

Guertin, Steven M.↗

Simulation program of nonlinearities applied to telecommunication systems

In any satellite communication system, the problems of distorsion created by nonlinear devices or systems must be considered. The subject of this paper is the use of the Fast Fourier Transform (F.F.T.) in the prediction of the intermodulation performance of amplifiers, mixers, filters. A nonlinear memory-less model is chosen to simulate amplitude and phase nonlinearities of the device in the simulation program written in FORTRAN 4. The experimentally observed nonlinearity parameters of a low noise 3.7-4.2 GHz amplifier are related to the gain and phase coefficients of Fourier Service Series. The measured results are compared with those calculated from the simulation in the cases where the input signal is composed of two, three carriers and noise power density.

Thomas, C.↗

In-Flight Observations of Long-Term Single Event Effect(SEE)Performance on Orbview-2 and Xray Timing Explorer(XTE)Solid State Recorders (SSR)

This paper presents Single Event Effect (SEE) in-flight data on Solid State Recorders (SSR) that have been collected over a long period of time for two NASA spacecraft: Orbview-2 and XTE. SEE flight data on solid-state memories give an opportunity to study the behavior in space of SEE sensitive commercial devices. The actual Single Event Upset (SEU) rates can be compared with the calculated rates based on environment models and ground test data. The SEE mitigation schemes can also be evaluated in actual implementation. A significant amount of data has already been published concerning observed SEE effects on memories in space. However, most of the data presented cover either a short period of time or a small number of devices. The data presented here has been collected on a large number of devices during several years. This allows statistically significant information about the effect of space weather fluctuations on SEU rates, and the effectiveness of SEE countermeasures used to be analyzed. Only Orbview-2 data is presented in this summary. XTE data will be included in the final paper.

Poivey, Christian↗

A passive chevron replicator

Instrument design provides replicate function between device storage area and guardrail detector in order that nondestructive read-out of memory can be achieved. Use of guardrail detectors in magnetic domain (bubble) circuits is proposed method of increasing detector signal output by increasing detector size without dedicating an excessive amount of device chip area to detector portion.

Oeffinger, T. R.↗

Toward Accurate Thermal Modeling of Phase Change Material Based Photonic Devices

Reconfigurable or programmable photonic devices are rapidly growing and have become an integral part of many optical systems. The ability to selectively modulate electromagnetic waves through electrical stimuli is crucial in the advancement of a variety of applications from data communication and computing devices to environmental science and space explorations. Chalcogenide-based phase change materials (PCMs) are one of the most promising material candidates for reconfigurable photonics due to their large optical contrast between their different solid-state structural phases. Although significant efforts have been devoted to accurate simulation of PCM-based devices, in this paper, we highlight three important aspects which have often evaded prior models yet having significant impacts on the thermal and phase transition behavior of these devices: the enthalpy of fusion, the heat capacity change upon glass transition, as well as the thermal conductivity of liquid-phase PCMs. We further investigated the important topic of switching energy scaling in PCM devices, which also helps explain why the three above-mentioned effects have long been overlooked in electronic PCM memories but only become important in photonics. Our findings offer insight to facilitate accurate modeling of PCM-based photonic devices and can inform the development of more efficient reconfigurable optics.

Phase change materials↗

Trends in solid state electronics, part 2

Developments in the fields of semiconductors and magnetics are surveyed. Materials, devices, theory, and fabrication technology are discussed. Important events up until the present time are reported, and events are interpreted through historical perspective. A brief analysis of forces which have driven the development of today's electronic technology and some projections of present trends are given. More detailed discussions are presented for four areas of contemporary interest: amorphous semiconductors, bubble domain devices, charge-coupled devices, and electron and ion beam techniques. Beam addressed magnetic memories are reviewed to a lesser extent.

Gassaway, J. D.↗

Memory technology survey

The current status of semiconductor, magnetic, and optical memory technologies is described. Projections based on these research activities planned for the shot term are presented. Conceptual designs of specific memory buffer pplications employing bipola, CMOS, GaAs, and Magnetic Bubble devices are discussed.

Source record↗

Massively parallel processor computer

An apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array is described. It comprises a large number (e.g., 16,384 in a 128 x 128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered parallel data, including spatial translation by shifting or sliding of bits vertically or horizontally to neighboring processing elements.

Fung, L. W.↗

High performance flight computer developed for deep space applications

The development of an advanced space flight computer for real time embedded deep space applications which embodies the lessons learned on Galileo and modern computer technology is described. The requirements are listed and the design implementation that meets those requirements is described. The development of SPACE-16 (Spaceborne Advanced Computing Engine) (where 16 designates the databus width) was initiated to support the MM2 (Marine Mark 2) project. The computer is based on a radiation hardened emulation of a modern 32 bit microprocessor and its family of support devices including a high performance floating point accelerator. Additional custom devices which include a coprocessor to improve input/output capabilities, a memory interface chip, and an additional support chip that provide management of all fault tolerant features, are described. Detailed supporting analyses and rationale which justifies specific design and architectural decisions are provided. The six chip types were designed and fabricated. Testing and evaluation of a brass/board was initiated.

Bunker, Robert L.↗

Mode shape analysis using a commercially available peak store video frame buffer

Time exposure photography, sometimes coupled with strobe illumination, is an accepted method for motion analysis that bypasses frame by frame analysis and resynthesis of data. Garden variety video cameras can now exploit this technique using a unique frame buffer that is a non-integrating memory that compares incoming data with that already stored. The device continuously outputs an analog video signal of the stored contents which can then be redigitized and analyzed using conventional equipment. Historically, photographic time exposures have been used to record the displacement envelope of harmonically oscillating structures to show mode shape. Mode shape analysis is crucial, for example, in aeroelastic testing of wind tunnel models. Aerodynamic, inertial, and elastic forces can couple together leading to catastrophic failure of a poorly designed aircraft. This paper will explore the usefulness of the peak store device as a videometric tool and in particular discuss methods for analyzing a targeted vibrating plate using the 'peak store' in conjunction with calibration methods familiar to the close-range videometry community. Results for the first three normal modes will be presented.

Snow, Walter L.↗

Evaluation of Radiation Effects in Flash Memories

Features of flash memories: Flash memories are non-volatile; that is they do not require power to retain the information in its memory. They can be erased and written to while the device is still in the circuit.

Radiation effects↗

IBM powerPC 405 SEU mitigation using processor voting techniques in Xilinx Virtex-I1 pro FPGA

Not until recently, Xilinx has developed a new field programmable gate array (FPGA) device family, Virtex-I1 Pro. In this single device, not only dies it have density logic cells (3K to125K), gigabit connectivity, on chip memory, digital clock management, but also it can have up to four IBM PowerPC 405 Processor hard cores, running up to 400MHz and 633 Mbps. To utilize this cutting edge device in space applications, a few Single Event Upset (SEU) mitigation techniques need to be implemented to a design for the device. At Jet Propulsion Laboratory (JPL), we have successfully demonstrated the feasibility of running multiple processors running in a lock step fashion to accomplish SEU mitigation and fault tolerance.

single event upset (SEU)↗