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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 325 records · Page 18
All sourcesNASA NTRSDOE OSTI
NASA NTRS2017

Field Programmable Gate Array Failure Rate Estimation Guidelines for Launch Vehicle Fault Tree Models

Today's launch vehicles complex electronic and avionic systems heavily utilize the Field Programmable Gate Array (FPGA) integrated circuit (IC). FPGAs are prevalent ICs in communication protocols such as MIL-STD-1553B, and in control signal commands such as in solenoid/servo valves actuations. This paper will demonstrate guidelines to estimate FPGA failure rates for a launch vehicle, the guidelines will account for hardware, firmware, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC, FPGA memory and clock. The firmware portion will provide guidelines on the high level FPGA programming language and ways to account for software/code reliability growth. The radiation portion will provide guidelines on environment susceptibility as well as guidelines on tailoring other launch vehicle programs historical data to a specific launch vehicle.

Al Hassan, Mohammad↗
NASA NTRS2017

Field Programmable Gate Array Reliability Analysis Guidelines for Launch Vehicle Reliability Block Diagrams

Field Programmable Gate Arrays (FPGAs) integrated circuits (IC) are one of the key electronic components in today's sophisticated launch and space vehicle complex avionic systems, largely due to their superb reprogrammable and reconfigurable capabilities combined with relatively low non-recurring engineering costs (NRE) and short design cycle. Consequently, FPGAs are prevalent ICs in communication protocols and control signal commands. This paper will identify reliability concerns and high level guidelines to estimate FPGA total failure rates in a launch vehicle application. The paper will discuss hardware, hardware description language, and radiation induced failures. The hardware contribution of the approach accounts for physical failures of the IC. The hardware description language portion will discuss the high level FPGA programming languages and software/code reliability growth. The radiation portion will discuss FPGA susceptibility to space environment radiation.

Al Hassan, Mohammad↗
NASA NTRS2018

Gated CDS Integrator

A Gated CDS Integrator (GCI) may amplify low-level signals without introducing excessive offset and noise. The GCI may also amplify the low level signals with accurate and variable gain. The GCI may include a modulator preceding a linear amplifier such that offset or noise present in a signal path between the modulator and a demodulator input is translated to a higher out of band frequency.

Quilligan, Gerard T.↗
NASA NTRS2018

Self Diagnostic Accelerometer Field Programmable Gate Array (SDA FPGA)

A self-diagnostic accelerometer (SDA) field programmable gate array (FPGA) may be capable of real time or near-real time diagnostic processing to determine potential accelerometer issues during flight or other mission critical operational situations. The SDA FPGA may determine accelerometer structural health and an attachment condition using an electronics system that is smaller, more energy efficient, and more cost effective than previous diagnostic tools. Advantages of the system may include diagnosing sensors automatically, immediately, actively (i.e., confirming the fault), and consistently, without the influence of a human operator. Customizable SDA algorithms may be adjusted to the specific needs of the sensor/environment.

Tokars, Roger P.↗
NASA NTRS2018

Current Source Logic Gate

A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Krasowski, Michael J.↗
NASA NTRS2018

Gated CDS Integrator

A Gated CDS Integrator (GCI) may amplify low-level signals without introducing excessive offset and noise. The GCI may also amplify the low level signals with accurate and variable gain. The GCI may include a modulator preceding an amplifier such that offset or noise present in a signal path between the modulator and a demodulator input is translated to a higher out of band frequency, and thereafter reduced by a double sampled discrete time integrator which also reduces thermal noise. The thermal noise may also be reduced by averaging the output of the discrete time integrator.

Quilligan, Gerard T.↗
NASA NTRS2016

Fitting a Model to Floating Gate Prompt Charge Loss Test Data for the Samsung 8 Gb SLC NAND Flash Memory

A recent model provides risk estimates for the deprogramming, of initially programmed floating gates, via prompt charge loss produced by an ionizing radiation environment. The environment can be a mixture of electrons, protons, and heavy ions. The model requires several input parameters. Parameters intended to produce conservative risk estimates for the Samsung 8 Gb SLC NAND flash memory are given, subject to some qualifications.

Edmonds, L. D.↗
NASA NTRS2020

Single-Event Testing of the Texas Instruments SNV54LVC00AW Quadruple 2-Input Positive-NAND Gates

The purpose of this testing was to characterize the Texas Instruments SNV54LVC00AW for single-event latchup (SEL) in support of a NASA GSFC flight program. The SNV54LVC00A quadruple 2-input positive-NAND gate. These devices were tested at the Berkeley Accelerator Space Effects (BASE) Facility at Lawrence Berkeley National Laboratory (LBNL) where they were irradiated with the 10 MeV/amu heavy ion cocktail.

Campola, Michael↗
NASA NTRS2020

Performance Evaluation of Isolated Gate Driver, ADuM4121, Under Exposure to Extreme Temperature

Electronics designed for use in space missions are expected to be exposed to harsh environment including radiation and extreme temperature, to name a few. Severe thermal swings are also encountered depending on planetary exploration, orbital orientation, and mission duration. Most commercial-off-the-shelf (COTS) devices are not designed to function under such extreme conditions and very little data exist on their performance outside their specified range of operation. In this work, the performance of an isolated gate driver for controlling power-level transistors, including gallium nitride (GaN) and silicon carbide (SiC) devices, was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance for potential use of this device in space exploration missions under extreme temperature conditions.

Boomer, Kristen↗
NASA NTRS1995

Fabrication and Performance of Planar Schottky Diodes with T-gate-like Anodes in 200 GHz Subharmonically-Pumped Waveguide Mixers

A T-gate-like structure has been developed, fabricated and tested as the anode for millimeter and submillimeter-wave Schottky diodes. The low parasitics of the T-anode diodes yield extremely high cutoff frequencies, making the diodes useable at frequencies well beyond 1 THz. The diodes were tested as an antiparallel-pair, integrated monolithically with microstrip circuitry on a quartz substrate, in a subharmonically pumped waveguide mixer. A double sideband noise temperature of 600 K with a conversion loss of 4.7 dB were measured at 200 GHz. This is believed to be the lowest noise temperature ever reported for a room temperature subharmonically-pumped Schottky diode mixer at this frequency.

Planar↗
NASA NTRS2009

Single-Event Gate Rupture and Single-Event Burnout Test Results Performed on Hi-Rel Fuji Power MOSFETs: 2SK4217, 2SK4152, 2SK4155, and 2SK4158

Several newly available Hi-Rel total dose hardened power MOSFETs manufactured by Fuji Electric Device Technology Co. Ltd (FDT) in conjunction with the Japan Aerospace Exploration Agency (JAXA) were tested for single-event gate rupture (SEGR) and single-event burnout (SEB). The safe-operating area (SOA) of the 2SK4217 (a 100 V rated device), 2SK4152 (130 V), 2SK4155 (200 V), and the 2SK4158 (250 V) were tested with silver (Ag) and xenon (Xe) ions having incident LETs of 42.2 and 53.1 MeV cm2/mg, respectively. Test results show these devices are comparable to currently available total dose hardened technology.

Selva, Luis E.↗
NASA NTRS2001

Heavy ion induced soft breakdown of thin gate oxides

Heavy ion induced soft and hard breakdown are investigated in thin gate oxides as a function of LET, fluence, and voltage applied during irradiation. It is found that post-irradiation oxide conduction is well described by the Sune quantum point contact model.

radiation↗
NASA NTRS2009

Mitigation selection and qualification recommendations for Xilinx Virtex, Virtex-II, and Virtex-4 field programmable gate arrays

This work discusses mitigation selection and qualification techniques for Xilinx reconfigurable field programmable gate arrays (FPGAs). The aim of the paper is to provide readers with a better understanding of the engineering/reliability/project cost relationship that occurs when developing a mitigation strategy for static random access memory (SRAM)-based FPGAs.

Allen, Gregory↗
NASA NTRS2024

Single-Event Effects Test Report Lattice Semiconductor, LCMXO3D-9400HC-5BG484I Field Programmable Gate Array

The purpose of this test was to characterize single event effects (SEE) in the LCMXO3D-9400HC-5BG484I, a low power and low density field programmable gate array (FPGA). The SEE concerns for the device that were investigated in this testing are single event upsets (SEUs) in the configuration static random-access memory (SRAM), SEUs in the FPGA fabric, single event latch up (SEL), and single event functional interrupts (SEFIs). Testing was conducted at Lawrence Berkeley National Laboratory (LBNL) on August 26th, 2024 and August 28th, 2024.

Adia M Wood↗
NASA NTRS2006

Single Event Effects Test Results for the Actel ProASIC Plus and Altera Stratix-II Field Programmable Gate Arrays

This work describes radiation testing of Actel's ProASIC Plus and Altera's Stratix-II FPGAs. The Actel Device Under Test (DUT) was a ProASIC Plus APA300-PQ208 nonvolatile, field reprogrammable device which is based on a 0.22micron flash-based LVCMOS technology. Limited investigation has taken place into flash based FPGA technologies, therefore this test served as a preliminary reference point for various SEE behaviors. The Altera DUT was a Stratix-II EP2S60F1020C4. Single Event Upset (SEU) and Single Event Latchup (SEL) were the focus of these studies. For the Actel, a latchup test was done at an effective LET of 75.0 MeV-sq cm/mg at room temperature, and no latchup was detected when irradiated to a total fluence of 1 x 10(exp 7) particles/sq cm. The Altera part was shown to latchup at room temperature.

heavy ions↗
NASA NTRS2006

Upset Characterization of the PowerPC405 Hard-core Processor Embedded in Virtex-II Pro Field Programmable Gate Arrays

Shown in this presentation are recent results for the upset susceptibility of the various types of memory elements in the embedded PowerPC405 in the Xilinx V2P40 FPGA. For critical flight designs where configuration upsets are mitigated effectively through appropriate design triplication and configuration scrubbing, these upsets of processor elements can dominate the system error rate. Data from irradiations with both protons and heavy ions are given and compared using available models.

radiation effects↗