Results for “Computer Operations and Hardware” — Page 18

DOE OSTI2022

Benchmarking Real-Time Control Platforms Using a Matlab/Simulink Coder with Applications in the Control of DC/AC Switched Power Converters

In the control of DC/AC switched power converters (SPC), one of the most important aspects to be considered is the selection of the real-time control platform. The real-time control platform must be able to meet the high performance efficiency and regulation requirements of the DC/AC SPC, as these typically operate at switching frequencies in the order of kHz to MHz. For this reason, the hardware characteristics of the ADC and PWM, and the processing capacity of the real-time control platform are of vital importance when implementing advanced digital controllers that maintain voltage and current levels within regulatory standards. In this context, we aimed to perform a comparative study of the computation times of different real-time control platforms when implementing different control strategies for DC/AC switched power converters. We also analyzed the impact of the real-time control platforms on the THD of the voltages generated by the DC/AC switched power converters. With the help of this paper, researchers and developers will have criteria to select which real-time control platform to use in real-time control for DC/AC SPC applications.

42 ENGINEERING↗

DOE OSTI2025

A Review of Quantum Computing Technologies in Power System Optimization

As modern power grids increasingly integrate variable renewable generation, distributed energy resources, and energy storage systems, classical optimization techniques are facing unprecedented challenges. This review examines the emerging application of quantum computing to overcome these challenges in power system optimization, including optimal power flow (OPF), unit commitment (UC), economic dispatch (ED), and intelligent switching and topology optimization (IS-TO). Recent research has introduced various quantum methodologies—such as gate-based, annealing-based, variational algorithms, and quantum-inspired algorithms—to address the combinatorial complexity inherent in grid reconfiguration and energy management. The review summaries the quantum algorithms, quantum devices and the power system test cases, highlighting hybrid quantum–classical strategies that leverage the complementary strengths of both paradigms. Some quantum advantages have been observed, including theoretical speedup, accurate simulation results, scalable qubit usage, efficient QUBO mapping. In particular, the review emphasizes the importance of integrating quantum optimization techniques with classical control frameworks, these hybrid approaches demonstrate the potential to improve real-time grid management and operational reliability. A significant portion of the analysis is devoted to the practical limitations of current quantum devices. Present-day quantum hardware, operating in the noisy intermediate-scale quantum (NISQ) era, remains highly sensitive to noise and limited in qubit connectivity, which constrains the scale and accuracy of implemented algorithms. The review delves into specific challenges such as the need for qubit-efficient encoding techniques and error mitigation strategies that are critical for handling real-world grid optimization problems. In addition, the work draws attention to the performance discrepancies between theoretical quantum speedups and experimental validations, underscoring the importance of rigorous benchmark studies using representative power grid test cases. In summary, this review highlights both the promise and limitations of quantum computing for power system optimization. It provides a comprehensive overview of the state-of-the-art technologies, categorizes recent advancements in algorithm design, and discusses practical considerations for implementation, and serves as an informative resource on current research. Future research directions include developing robust hybrid frameworks, advancing qubit-efficient formulations, and scaling up experimental demonstrations to confirm the theoretical advantages of quantum methods in large-scale power system operations.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2022

SpecFIDLER User Manual: Software Version 2.4.0

The Spectroscopic Field Instrument for Detection of Low Energy Radiation (SpecFIDLER) allows response teams to detect and quantify plutonium contamination on the ground. Notional scenarios include dispersion from a weapon accident, or the launch failure of a space probe containing a radioisotope thermoelectric generator. Unlike other instruments, the thin-window sodium iodide detector is sensitive to the low-energy gamma rays emitted by plutonium isotopes. The system supports both mobile survey as well as stationary sampling. This manual provides information about installing, maintaining, and troubleshooting the SpecFIDLER. The scope of this document includes the physical hardware, software for data acquisition, and algorithms for data analysis. Recent changes to the software and algorithms aim to streamline the operation of the system.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2019

UPC++ Specification v1.0, Draft 10

UPC++ is a C++11 library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. We are revising the library under the auspices of the DOE’s Exascale Computing Project, to meet the needs of applications requiring PGAS support. UPC++ is intended for implementing elaborate distributed data structures where communication is irregular or fine-grained. The UPC++ interfaces for moving non-contiguous data and handling memories with different optimal access methods are composable and similar to those used in conventional C++. The UPC++ programmer can expect communication to run at close to hardware speeds. The key facilities in UPC++ are global pointers, that enable the programmer to express ownership information for improving locality, one-sided communication, both put/get and RPC, futures and continuations. Futures capture data readiness state, which is useful in making scheduling decisions, and continuations provide for completion handling via callbacks. Together, these enable the programmer to chain together a DAG of operations to execute asynchronously as high-latency dependencies become satisfied.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2019

UPC++ v1.0 Specification (Revision 2019.9.0)

UPC++ is a C++11 library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. We are revising the library under the auspices of the DOE’s Exascale Computing Project, to meet the needs of applications requiring PGAS support. UPC++ is intended for implementing elaborate distributed data structures where communication is irregular or fine-grained. The UPC++ interfaces for moving non-contiguous data and handling memories with different optimal access methods are composable and similar to those used in conventional C++. The UPC++ programmer can expect communication to run at close to hardware speeds. The key facilities in UPC++ are global pointers, that enable the programmer to express ownership information for improving locality, one-sided communication, both put/get and RPC, futures and continuations. Futures capture data readiness state, which is useful in making scheduling decisions, and continuations provide for completion handling via callbacks. Together, these enable the programmer to chain together a DAG of operations to execute asynchronously as high-latency dependencies become satisfied.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

UPC++ Specification v1.0, Draft 8

UPC++ is a C++11 library providing classes and functions that support Partitioned Global Address Space (PGAS) programming. We are revising the library under the auspices of the DOE’s Exascale Computing Project, to meet the needs of applications requiring PGAS support. UPC++ is intended for implementing elaborate distributed data structures where communication is irregular or fine-grained. The UPC++ interfaces for moving non-contiguous data and handling memories with different optimal access methods are composable and similar to those used in conventional C++. The UPC++ programmer can expect communication to run at close to hardware speeds. The key facilities in UPC++ are global pointers, that enable the programmer to express ownership information for improving locality, one-sided communication, both put/get and RPC, futures and continuations. Futures capture data readiness state, which is useful in making scheduling decisions, and continuations provide for completion handling via callbacks. Together, these enable the programmer to chain together a DAG of operations to execute asynchronously as high-latency dependencies become satisfied.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems

Fail-slow hardware is an under-studied failure mode. We present a study of 114 reports of fail-slow hardware incidents, collected from large-scale cluster deployments in 14 institutions. We show that all hardware types such as disk, SSD, CPU, memory, and network components can exhibit performance faults. We made several important observations such as faults convert from one form to another, the cascading root causes and impacts can be long, and fail-slow faults can have varying symptoms. From this study, we make suggestions to vendors, operators, and systems designers.

fail-slow↗

DOE OSTI2022

Computer Science Research Needs for Parallel Discrete Event Simulation (PDES)

Historically, scientific computing efforts have demonstrated the clear need for, and effective use of, supercomputing with traditional time-stepped simulations. Nevertheless, there are several areas in the mission spaces of the U.S. Department of Energy and other agencies waiting to tap advanced computing research using a different, discrete event style of modeling, simulation, and analysis. These span a wide spectrum of applications including energy grid resilience, urban planning and policy, transportation science, building technologies, emergency response and planning, environmental impact analysis, computational epidemiology, Internet communications, cyber security, and cyber-physical systems, to name only a few. Even within traditional scientific applications, the role of discrete event modes of execution is increasing in the form of new event-based mathematical solvers such as quantized state integration methods and discrete-continuous hybrid system solvers. Co-design of advanced supercomputing hardware systems is another area that exploits discrete event simulation at its core for effective analyses. Complex systems, entity behaviors and interconnections play a significant role in all these applications, which are mapped to large-scale models with discrete event formulations. To make advancements in all the aforementioned scientific areas, many technical aspects need to be more thoroughly studied and deeply understood in parallel discrete event simulation (PDES). The unique dynamics inherent in a discrete event modeling approach, by their very nature, intersect and influence the entire stack of the computing system, including (a) the unique nature of the instruction sets exercised in PDES workloads without a predominance of high-precision floating point operations, (b) virtual time-constrained multi-threaded execution of many logical processes per processor, (c) extremely variable and difficult to predict network traffic characteristics, (d) interfaces and inter-dependencies with machine learning and artificial intelligence codes at higher software layers, and (e) highly challenging load balancing needs, especially in effectively accounting for accelerated/extremely heterogeneous computing in current and future high-performance computing systems. Efficient and accurate parallel execution of PDES workloads is also dominated by challenges in dealing with their asynchronous concurrency fundamentally present at the model level. Conservative synchronization, optimistic/speculative synchronization, and their hybrid schemes open new questions in fundamental computer science with respect to reversibility of computation and prediction (lookahead) of behaviors inherent within model codes. On the implementation front, there are relatively few scalable, general-purpose parallel discrete event simulators in the world, and even fewer have been studied on emerging hardware platforms. To enable scientific advances using PDES, the research needs in computer science must also be pursued and met in the intersection of the algorithmic and hardware-aware aspects of scalable PDES engines. This report is aimed at capturing a computer science-oriented view of this important area of research in PDES, presenting a sample of important applications with their inherent discrete event technology elements. Needs are outlined in core areas of parallel discrete event research as well as cross-cutting directions in computer science research that positively impact scientific advancements across several important application areas. A selection of priority research opportunities in advanced computing for PDES is identified to serve as reference for key research topics and their order of importance for scientific advancements.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Memristive Ion Channel-Doped Biomembranes as Synaptic Mimics

Solid-state neuromorphic systems based on transistors or memristors have yet to achieve the interconnectivity, performance, and energy efficiency of the brain due to excessive noise, undesirable material properties, and nonbiological switching mechanisms. Here in this work, we demonstrate that an alamethicin-doped, synthetic biomembrane exhibits memristive behavior, emulates key synaptic functions including paired-pulse facilitation and depression, and enables learning and computing. Unlike state-of-the-art devices, our two-terminal, biomolecular memristor features similar structure (biomembrane), switching mechanism (ion channels), and ionic transport modality as biological synapses while operating at considerably lower power. The reversible and volatile voltage-driven insertion of alamethicin peptides into an insulating lipid bilayer creates conductive pathways that exhibit pinched current–voltage hysteresis at potentials above their insertion threshold. Moreover, the synapse-like dynamic properties of the biomolecular memristor allow for simplified learning circuit implementations. Finally, low-power memristive devices based on stimuli-responsive biomolecules represent a major advance toward implementation of full synaptic functionality in neuromorphic hardware.

36 MATERIALS SCIENCE↗

DOE OSTI2015

High performance techniques for micro channel plate computations in photo multipliers

Monte Carlo - MC methods, requiring heavy computations of large data volume, can be used to predict the amplitude distribution and variance of outputted electron charge in Micro Channel Plates - MCPs, which are fed with primary emitted electrons in their inputs. The concept of parallel and serial combination of separate stages of such stochastic processes, which can be applied in MCP systems and simulated using MC computations, has recently proposed and shown interesting theorems and results. Separating the electron multiplication procedures, occurring in the channels of MCP systems, into sub-procedures, which are similar in nature and occur either in parallel or in consecutive manners, is equivalent to splitting the relevant stochastic system calculations into smaller ones, which can be performed concurrently and/or sequentially. In this way, calculations similar in nature, can be executed only once, thus, eliminating a great percentage of heavy computations. However, when designing and implementing the calculation inferences of the derived theorems using High Performance Computation - HPC techniques, the overall computation cost can further and significantly be reduced. In this paper, the hardware mappings of the relevant theorem inferences onto parallel computing architectures, resulting in circuits of computing blocks for calculation purposes of MCP system stochastic processes, are investigated. Each of the designed and implemented computing circuits corresponds to a theorem inference or to a combination of inferences. The parallelism of the proposed circuits consists of both the concurrent functioning of all the system blocks and of the simultaneous operation of each block, which is processing pieces of data, for many parts of the whole circuit in which it belongs. All the circuits are designed and tested using Altera Quartus II environment and can be implemented as chips, which can be incorporated in computing devices to assist Monte Carlo computations for the estimation of different MCP electron multiplication system performances.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2022

Use of Multiple Tracer Gases to Quantify Vane Trailing Edge Flow Into Turbine Rim Seals

Abstract Overlapping features are commonly used as rim seals between stationary and rotating components in a turbine stage. These rim seals are used to prevent main gas path ingestion to the wheelspace cavity, which reduces the lifespan of critical engine components such as the turbine disk. In addition to the overlapping features, purge flow, diverted from the compressor, is injected into the rim cavity to act as an airflow sealing mechanism. Previous research identified that in addition to the purge flow in the rim cavity, cooling flow from the vane trailing edge (VTE) is ingested into the rim seal cavity carrying the potential to cool components in the wheelspace. These previous findings, however, were not able to distinctly separate purge from VTE cooling flows, which is the contribution of this paper based on uniquely using two different tracer gases. A one-stage test turbine operating at engine-relevant conditions and consisting of real engine hardware was used to validate and quantify the ingestion of the VTE flow by independently seeding the purge and VTE flows with two different tracer gases. Experimental results show the presence of VTE flow in the rim seal throughout all purge flowrates evaluated. Circumferential variation of VTE flow was also studied both experimentally and computationally using a computational fluid dynamics model. Results showed that ingested VTE flow can reduce the detrimental effect of hot gas ingestion particularly at higher purge flowrates.

Engineering↗

DOE OSTI2017

RAJA Performance Suite

The RAJA Performance Suite is designed to evaluate performance of the RAJA performance portability library on a wide variety of important high performance computing (HPC) algorithmic lulmels. These kernels assess compiler optimizations and various parallel programming model backends accessible through RAJA, such as OpenMP, CUDA, etc. The Initial version of the suite contains 25 computational kernels, each of which appears in 6 variants: Baseline SequcntiaJ, RAJA SequentiaJ, Baseline OpenMP, RAJA OpenMP, Baseline CUDA, RAJA CUDA. All variants of each kernel perform essentially the same mathematical operations and the loop body code for each kernel is identical across all variants. There are a few kernels, such as those that contain reduction operations, that require CUDA-specific coding for their CUDA variants. ActuaJ computer instructions executed and how they run in parallel differs depending on the parallel programming model backend used and which optimizations are perfonned by the compiler used to build the Perfonnance Suite executable. The Suite will be used primarily by RAJA developers to perform regular assessments of RAJA performance across a range of hardware platforms and compilers as RAJA features are being developed. It will also be used by LLNL hardware and software vendor panners for new defining requirements for future computing platform procurements and acceptance testing. In particular, the RAJA Performance Suite will be used for compiler acceptance testing of the upcoming CORAUSierra machine {initial LLNL delivery expected in late-2017/early 2018) and the CORAL-2 procurement. The Suite will aJso be used to generate concise source code reproducers of compiler and runtime issues we uncover so that we may provide them to relevant vendors to be fixed.

Hornung, RichardD.↗

DOE OSTI2016

Contingency Contractor Optimization Phase 3 Sustainment Platform Requirements - Contingency Contractor Optimization Tool - Prototype

Sandia National Laboratories (Sandia) is in Phase 3 Sustainment of development of a prototype tool, currently referred to as the Contingency Contractor Optimization Tool - Prototype (CCOTP), under the direction of OSD Program Support. CCOT-P is intended to help provide senior Department of Defense (DoD) leaders with comprehensive insight into the global availability, readiness and capabilities of the Total Force Mix. The CCOT-P will allow senior decision makers to quickly and accurately assess the impacts, risks and mitigating strategies for proposed changes to force/capabilities assignments, apportionments and allocations options, focusing specifically on contingency contractor planning. During Phase 2 of the program, conducted during fiscal year 2012, Sandia developed an electronic storyboard prototype of the Contingency Contractor Optimization Tool that can be used for communication with senior decision makers and other Operational Contract Support (OCS) stakeholders. Phase 3 used feedback from demonstrations of the electronic storyboard prototype to develop an engineering prototype for planners to evaluate. Sandia worked with the DoD and Joint Chiefs of Staff strategic planning community to get feedback and input to ensure that the engineering prototype was developed to closely align with future planning needs. The intended deployment environment was also a key consideration as this prototype was developed. Initial release of the engineering prototype was done on servers at Sandia in the middle of Phase 3. In 2013, the tool was installed on a production pilot server managed by the OUSD(AT&L) eBusiness Center. The purpose of this document is to specify the CCOT-P engineering prototype platform requirements as of May 2016. Sandia developed the CCOT-P engineering prototype using common technologies to minimize the likelihood of deployment issues. CCOT-P engineering prototype was architected and designed to be as independent as possible of the major deployment components such as the server hardware, the server operating system, the database, and the web server. This document describes the platform requirements, the architecture, and the implementation details of the CCOT-P engineering prototype.

42 ENGINEERING↗

DOE OSTI2018

Deployable sensor system using mesh networking and satellite communication

A sensor system may be configured for continuous operation in a low resource environment and/or in extreme environmental conditions. The sensor system may have sufficient processing capabilities to provide scientific computing for pre-processing, quality control, statistical analysis, event classification, data compression and corrections (e.g., spikes in the data), autonomous decisions and actions, triggering other nodes, and information assurance functions that provide data confidentiality, data integrity, authentication, and non-repudiation. The hardware may have both mesh networking and satellite and cellular communication capability, and may be available for relatively low cost. Such a network provides the flexibility to have potentially any number of nodes be completely independent from one another. Thus, the network may scale across a diverse terrain.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Deployable sensor system using mesh networking and satellite communication

A sensor system may be configured for continuous operation in a low resource environment and/or in extreme environmental conditions. The sensor system may have sufficient processing capabilities to provide scientific computing for pre-processing, quality control, statistical analysis, event classification, data compression and corrections (e.g., spikes in the data), autonomous decisions and actions, triggering other nodes, and information assurance functions that provide data confidentiality, data integrity, authentication, and non-repudiation. The hardware may have both mesh networking and satellite and cellular communication capability, and may be available for relatively low cost. Such a network provides the flexibility to have potentially any number of nodes be completely independent from one another. Thus, the network may scale across a diverse terrain.

Frigo, Janette↗

DOE OSTI2023

Control Systems Design for STS Accelerator

The Second Target Station (STS) Project will expand the capabilities of the existing Spallation Neutron Source (SNS), with a suite of neutron instruments optimized for long wavelengths. A new accelerator transport line will be built to deliver one out of four SNS pulses to the new target station. The Integrated Control Systems (ICS) will provide remote control, monitoring, OPI, alarms, and archivers for the accelerator systems, such as magnets power supply, vacuum devices, and beam instrumentation. The ICS will upgrade the existing Linac LLRF controls to allow independent operation of the FTS and STS and support different power levels of the FTS and STS proton beam. The ICS accelerator controls are in the phase of preliminary design for the control systems of magnet power supply, vacuum, LLRF, Timing, Machine protection system (MPS), and computing and machine network. The accelerator control systems build upon the existing SNS Machine Control systems, use the SNS standard hardware and EPICS software, and take full advantage of the performance gains delivered by the PPU Project at SNS.

Yan, Jay↗

DOE OSTI2024

MFANS 2024 - Formally Proving Characteristics of Cyber-Physical Systems

Cyber-physical systems (CPS) are engineered systems that rely on the smooth integration of computational algorithms and physical elements. This integration presents new challenges for verifying that systems will behave as expected. The goal of this presentation is to present current challenges and potential solutions for the formal verification of cyber-physical systems. For cyber systems, formal methods refer to systematically rigorous mathematical techniques employed in the specification, development, analysis, and verification of both software and hardware systems. Recent advancements in computer science have yielded sophisticated tools specifically designed to address challenges associated with formal methods in complex systems. These tools leverage various foundational concepts such as logic, formal languages, program semantics, type systems, type theory, and automata theory. A notable achievement in the application of formal methods is the seL4 microkernel, claimed to be the first general-purpose operating-system kernel to be verified. Its proof implies the absence of bugs and guarantees that the kernel meets specifications. For physical systems, dynamic and control theory has a history of using rigorous analytic techniques to prove functional correctness. Lyapunov, optimal, classical, modern, and robust control theories all provide rigorous mathematical methods both to analyze system performance and to design controller that can be guaranteed to meet certain objectives. Recent computational techniques like level set theory and reachability analysis provide assertions that a system's state will avoid unsafe regions. Even though success has been independently achieved for cyber systems and physical systems, the integration of such systems creates new challenges. In particular, there is an obvious discrepancy between finite-state machines and infinite-state systems, resulting in different approaches for modeling and analyzing these system. While it is possible to simulate hybrid systems, this provides only a demonstration of a performance and not proof. For hybrid systems, current formal methods and system analysis approaches typically require a workarounds to work on hybrid systems like CPS. This paper will outline the state of the art and limits of current practice for formally verifying CPS and will identify possible research directions that require attention.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2017

UPC++ Specification v1.0, Draft 4

UPC++ is a C++11 library providing classes and functions that support Asynchronous Partitioned Global Address Space (APGAS) programming. We are revising the library under the auspices of the DOE’s Exascale Computing Project, to meet the needs of applications requiring PGAS support. UPC++ is intended for implementing elaborate distributed data structures where communication is irregular or fine-grained. The UPC++ interfaces for moving non-contiguous data and handling memories with different optimal access methods are composable and similar to those used in conventional C++. The UPC++ programmer can expect communication to run at close to hardware speeds. The key facilities in UPC++ are global pointers, that enable the programmer to express ownership information for improving locality, one-sided communication, both put/get and RPC, futures and continuations. Futures capture data readiness state, which is useful in making scheduling decisions, and continuations provide for completion handling via callbacks. Together, these enable the programmer to chain together a DAG of operations to execute asynchronously as high-latency dependencies become satisfied.

97 MATHEMATICS AND COMPUTING↗