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297 records · Page 17

Comparison of TID Response and SEE Characterization of Single and Multi Level High Density NAND Flash Memories

Heavy ion single-event measurements and TID response for 8Gb commercial NAND flash memories are reported. Radiation results of multi-level flash technology are compared with results from single-level flash technology. In general, these commercial high density memories appear to be much less susceptible to SEE and have better TID response compared to older generations of flash memories. The charge pump survived up to 600 krads.

nonvolatile memory↗

Bayesian Statistical Models for Community Annoyance Survey Data

This paper demonstrates the use of two Bayesian statistical models to analyze single-event sonic boom exposure and human annoyance data from community response surveys. Each model is fit to data from a NASA pilot study.Unlike many community noise surveys, this study used a panel sample to collect multiple observations per participant instead of a single observation. Thus, a multilevel (also known as hierarchical or mixed-effects) model is used to account for the within-subject correlation in the panel sample data. This paper describes a multilevel logistic regression model and a multilevel ordinal regression model. The paper also proposes a method for calculating a summary dose-response curve from the multilevel models that represents the population. The two models’ summary dose-response curves are visually similar. However, their estimates differ when calculating the noise dose at a fixed percent highly annoyed.

Musical instruments↗

Radiation tests of highly scaled high density commercial nonvolatile NAND flash memories update 2009

Heavy ion single-event measurements on a variety of high density commercial NAND flash memories are reported. Three single event effect (SEE) phenomena are examined: single effect upsets (SEUs), single event functional interrupts (SEFIs), and catastrophic loss of ability to erase and program the device. Also, radiation results of multilevel flash technology are compared with results from single-level flash technology. These commercial high density memories appear to be much less susceptible to SEE and have better TID response compared to older generations of flash memories. The single-level devices are less sensitive to SEUs than multi-level devices. The charge pump in this study survived up to 600 krads. A new high current phenomenon in high density NAND flash memories is also discussed.

Nguyen, Duc N.↗

Robustness of Semi-Superjunction 4H-SiC Power DMOSFETs to Single-Event Burnout from Heavy Ion Bombardment

We compare the failure mechanism and performance of a silicon carbide (SiC) semi-superjunction (semi-SJ) power DMOSFET against pure SJ and conventional DMOSFET when struck by a single heavy ion. The Single-Event Burnout (SEB) failure mechanism was identified as the thermal runaway from second breakdown resulting in mesoplasma formation. The semi-SJ design shifts the mesoplasma location from the drift/substrate interface seen in the control device structures to a location along the center of the P-pillar and closer towards the DMOSFET surface, thus significantly improving the SEB threshold voltage. The SEB threshold voltage varies with pillar width and ratio of pillar thickness to drift layer thickness. A maximum value of SEB threshold voltage is reached when the pillar to drift layer ratio is 0.9 and the pillar width is 2.4 μm. The semi-SJ SEB/breakdown voltage ratio is 100% and 13% higher than the pure SJ and conventional DMOSFET, respectively. Using a new figure of merit (FOM), which accounts for the tradeoff between SEB threshold voltage and on-state performance, we find that the SiC semi-SJ DMOSFET achieves a FOM that is 1.8 and 8 times higher than SJ and conventional DMOSFET, respectively, making the semi-SJ a competitive candidate for radiation hardened applications.

SiC↗

Simulation-based Study of Single-Event Burnout in 4H-SiC High-Voltage Vertical Superjunction DMOSFET: Physical Failure Mechanism and Robustness vs. Performance Tradeoffs

We explore and elucidate physical failure mechanisms in a 4H-SiC, high voltage, superjunction (SJ) vertical DMOSFET from a single heavy ion strike using three-dimensional electro-thermal transient simulations. The single-event burnout (SEB) failure is thermal runaway from second breakdown, initiated by impact ionization and terminated with mesoplasma formation, at the center of the P-pillar/N+ substrate interface. We also demonstrate that the SEB performance of this SiC SJ DMOSFET is insensitive to the pillar width but sensitive to the strike location with ion strike at the P-pillar causing SEB at a lower blocking voltage than at the N-pillar. Compared to commercially available 1.2 kV blocking-rated non-SJ DMOSFETs, which have been demonstrated to survive SEB up to 525 V, the SJ DMOSFET increases SEB survival threshold voltage (VSEB) by a factor of 2.2, making it close to 1200 V, while the on-resistance is increased by only 11%. Using our recently developed figure of merit (FoM), which considers the trade-off between VSEB and on-state performance, we find that the SiC SJ DMOSFET achieves a FoM that is 14 times better, making it superior to conventional 1.2 kV SiC DMOSFETs for long-term radiation-tolerant operation in space applications.

Silicon Carbide↗