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At least 307 records · Page 17
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

PSEC5 Physical Verification

Ultra-Fast timing detectors, having a time resolution of 10pSec or less, are becoming increasingly important for many scientific disciplines, including High Energy Physics, Nuclear Physics, Medical Imaging and more. When developing ultra-fast detectors such as MCPs, LAPPDs, LGADs, SNSPDs, it is necessary to have access to a readout system that is low power, can support many channels and is cost effective. The PSEC5 chip was an application specific integrated circuit (ASIC) developed by the pioneering group of Prof. Henry Frisch at University of Chicago and micro electronic engineers at Fermi National Accelerator Laboratory. Three boards were designed, two to implement the readout system for an LAPPD and one to only characterize the PSEC1 chip. The main goal of the project shifted to setting up a testing environment to focus on the characterization of the chip. My student and I tested and characterized this ASIC using the third chip-on-board printed circuit board. Results show the successful fabrication and operation of some of the key building blocks and lead to the suggestions on modification for the second iteration of the chip.

Rico Aniles, H. D. [Unlisted]↗
DOE OSTI2025

Tiny Tapeout Laser Scan

Fault analysis of integrated circuits (ICs) is crucial for the understanding of the devices’ functionality. However, more traditional methods of probing and measuring signals are not possible for ICs due to their feature sizes going under the micron range.

Dominguez Rodriguez, Ever Joaquin [Sandia National↗
DOE OSTI2026

Pixel-Strip Module Testing and Performance Analysis for the CMS Phase-2 Outer Tracker Upgrade

In response to the demanding environment of the High-Luminosity Large Hadron Collider (HL-LHC), the Compact Muon Solenoid (CMS) Experiment's Outer Tracker is being replaced with a lighter, higher-granularity, radiation-tolerant silicon detector capable of providing tracking information directly to the Level-1 trigger system. The new Outer Tracker consists of Pixel-Strip (PS) and Strip-Strip (2S) transverse momentum (pT) modules, which are assembled and tested at, among other centers, Fermilab's Silicon Detector Facility. PS modules consist of a pixel sensor, a strip sensor, and multiple application-specific integrated circuits (ASICs). This poster studies the performance of MaPSAs, silicon macro-pixel sensors bump-bonded to 16 macro-pixel ASICS. It presents the testing procedures for MaPSAs and MaPSA-strip sensor sub-assemblies, as well as the results of calibration and performance studies of two PS modules before and after irradiation. These results assess the impact of irradiation on module performance, providing insight into the modules' expected performance in the HL-LHC environment.

Kimrey, Emerson [Scripps College]↗
DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗
DOE OSTI2025

Bare Module Testing for the CMS Vertex Detector Upgrade

The High-Luminosity LHC will continue exploring physics beyond the standard model with proton-proton collisions at ten times the luminosity of previous LHC runs. The physics program depends on precise measurements of charged particles near the beams. The CMS experiment will use layers of high-granularity hybrid silicon pixel detectors. Pixelation is achieved by bonding silicon to tiny electrodes, which are directly connected to the specially designed integrated circuit, CROCv2. Pixel detector components are in the pre-production phase, and evaluating prototypes of sensor-chip assemblies from different vendors provides quick feedback and improves reliability during production. This article presents the efforts to test the viability of bare detector assemblies using a manual probe station and electronic charge-injection methods.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2023

Editorial: Neuroscience, computing, performance, and benchmarks: Why it matters to neuroscience how fast we can compute

At the turn of the millennium the computational neuroscience community realized that neuroscience was in a software crisis: software development was no longer progressing as expected and reproducibility declined. The International Neuroinformatics Coordinating Facility (INCF) was inaugurated in 2007 as an initiative to improve this situation. The INCF has since pursued its mission to help the development of standards and best practices. In a community paper published this very same year, Brette et al. tried to assess the state of the field and to establish a scientific approach to simulation technology, addressing foundational topics, such as which simulation schemes are best suited for the types of models we see in neuroscience. In 2015, a Frontiers Research Topic “Python in neuroscience” by Muller et al. triggered and documented a revolution in the neuroscience community, namely in the usage of the scripting language Python as a common language for interfacing with simulation codes and connecting between applications. The review by Einevoll et al. documented that simulation tools have since further matured and become reliable research instruments used by many scientific groups for their respective questions. Open source and community standard simulators today allow research groups to focus on their scientific questions and leave the details of the computational work to the community of simulator developers. A parallel development has occurred, which has been barely visible in neuroscientific circles beyond the community of simulator developers: Supercomputers used for large and complex scientific calculations have increased their performance from ~10 TeraFLOPS (10 13 floating point operations per second) in the early 2000s to above 1 ExaFLOPS (10 18 floating point operations per second) in the year 2022. This represents a 100,000-fold increase in our computational capabilities, or almost 17 doublings of computational capability in 22 years. Moore's law (the observation that it is economically viable to double the number of transistors in an integrated circuit every other 18–24 months) explains a part of this; our ability and willingness to build and operate physically larger computers, explains another part. It should be clear, however, that such a technological advancement requires software adaptations and under the hood, simulators had to reinvent themselves and change substantially to embrace this technological opportunity. It actually is quite remarkable that—apart from the change in semantics for the parallelization—this has mostly happened without the users knowing. The current Research Topic was motivated by the wish to assemble an update on the state of neuroscientific software (mostly simulators) in 2022, to assess whether we can see more clearly which scientific questions can (or cannot) be asked due to our increased capability of simulation, and also to anticipate whether and for how long we can expect this increase of computational capabilities to continue.

biophysically detailed models↗
DOE OSTI2024

Neural network methods for radiation detectors and imaging

Recent advances in image data proccesing through deep learning allow for new optimization and performance-enhancement schemes for radiation detectors and imaging hardware. This enables radiation experiments, which includes photon sciences in synchrotron and X-ray free electron lasers as a subclass, through data-endowed artificial intelligence. We give an overview of data generation at photon sources, deep learning-based methods for image processing tasks, and hardware solutions for deep learning acceleration. Most existing deep learning approaches are trained offline, typically using large amounts of computational resources. However, once trained, DNNs can achieve fast inference speeds and can be deployed to edge devices. A new trend is edge computing with less energy consumption (hundreds of watts or less) and real-time analysis potential. While popularly used for edge computing, electronic-based hardware accelerators ranging from general purpose processors such as central processing units (CPUs) to application-specific integrated circuits (ASICs) are constantly reaching performance limits in latency, energy consumption, and other physical constraints. These limits give rise to next-generation analog neuromorhpic hardware platforms, such as optical neural networks (ONNs), for high parallel, low latency, and low energy computing to boost deep learning acceleration (LA-UR-23-32395).

edge computing↗
DOE OSTI2023

In Situ Study on Cu-to-Cu Thermal Compression Bonding

Cu-to-Cu thermal compression bonding (TCB) has emerged as a promising solution for ultrafine pitch packaging in 3D integrated circuit technologies. Despite the progress made by conventional Cu-to-Cu TCB methods in achieving good mechanical strength of the Cu bonds, the bonding processes generally require high temperature and high pressure, which may degrade the performance and reliability of the device. Therefore, it is imperative to investigate the processing parameters to understand the bonding mechanism and achieve effective TCB at a low temperature and low pressure. Here, we developed an in situ TCB technique inside a scanning electron microscope. The in situ TCB method enables a real-time observation of bonding development, which provides critical insights into how the texture and microstructure of Cu bumps may influence the creep and surface diffusion during the bonding process. This work features a strategy to advance our understanding of the bonding mechanisms and provides insight into tailoring the microstructure of Cu for bonding at a low temperature and low pressure.

36 MATERIALS SCIENCE↗
DOE OSTI2020

A New Concept for Kilotonne Scale Liquid Argon Time Projection Chambers

We develop a novel Time Projection Chamber (TPC) concept suitable for deployment in kilotonne-scale detectors, with a charge-readout system free from reconstruction ambiguities, and a robust TPC design that reduces high-voltage risks while increasing the coverage of the light-collection system and maximizing the active volume. This novel concept could be used as a far detector module in the Deep Underground Neutrino Experiment (DUNE). For the charge-readout system, we used the charge-collection pixels and associated application-specific integrated circuits currently being developed for the liquid argon (LAr) component of the DUNE Near Detector design, ArgonCube. In addition, we divided the TPC into a number of shorter drift volumes, reducing the total voltage used to drift the ionization electrons, and minimizing the stored energy per TPC. Segmenting the TPC also contains scintillation light, allowing for precise trigger localization and a more expansive light-readout system. Furthermore, the design opens the possibility of replacing or upgrading components. These augmentations could substantially improve the reliability and the sensitivity, particularly for low-energy signals, in comparison to traditional monolithic LArTPCs with projective-wire charge readouts.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Charge Transport Characteristics of Molecular Electronic Junctions Studied by Transition Voltage Spectroscopy

The field of molecular electronics is prompted by tremendous opportunities for using a single-molecule and molecular monolayers as active components in integrated circuits. Until now, a wide range of molecular devices exhibiting characteristic functions, such as diodes, transistors, switches, and memory, have been demonstrated. However, a full understanding of the crucial factors that affect charge transport through molecular electronic junctions should yet be accomplished. Remarkably, recent advances in transition voltage spectroscopy (TVS) elucidate that it can provide key quantities for probing the transport characteristics of the junctions, including, for example, the position of the frontier molecular orbital energy relative to the electrode Fermi level and the strength of the molecule–electrode interactions. These parameters are known to be highly associated with charge transport behaviors in molecular systems and can then be used in the design of molecule-based devices with rationally tuned electronic properties. This article highlights the fundamental principle of TVS and then demonstrates its major applications to study the charge transport properties of molecular electronic junctions.

36 MATERIALS SCIENCE↗
DOE OSTI2025

hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware

We present hls4ml, a free and open-source platform that translates machine learning (ML) models from modern deep learning frameworks into high-level synthesis (HLS) code that can be integrated into full designs for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). With its flexible and modular design, hls4ml supports a large number of deep learning frameworks and can target HLS compilers from several vendors, including Vitis HLS, Intel oneAPI and Catapult HLS. Together with a wider eco-system for software-hardware co-design, hls4ml has enabled the acceleration of ML inference in a wide range of commercial and scientific applications where low latency, resource usage, and power consumption are critical. In this paper, we describe the structure and functionality of the hls4ml platform. The overarching design considerations for the generated HLS code are discussed, together with selected performance results.

FOS: Computer and information sciences↗
DOE OSTI2020

A pixel detector ROIC with a 3-bit, 40 Msps synchronous ADC per pixel for HL LHC

The prototype Fermi Compact Muon Solenoid (CMS) Pixel (FCP130), manufactured in a 130 nm process, is a readout integrated circuit (ROIC) designed for the High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 48 × 160 pixels, each 100 × 30 μm2 in size. Each pixel contains a charge sensitive preamplifier with self-biasing leakage current compensation, eight auto-zero comparators and a Gray code encoder for a 3-bit flash-type ADC. The total power consumption is approximately 24 μW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 80 e- with threshold dispersion < 110 e-RMS, which allows an in-time threshold setting of ~ 1000 e-.

43 PARTICLE ACCELERATORS↗
DOE OSTI2020

Gain balanced nonlinear optical interferometer

A nonlinear fiber interferometer is disclosed suitable for fiber sensor and other applications. A first nonlinear fiber section amplifies probe and conjugate sidebands of a pump through four-wave mixing. A second section introduces a phase shift to be measured, for example from a sensor. A third nonlinear fiber section amplifies with phase-sensitive gain to increase signal-to-noise ratio. Based on phase-sensitive output power of probe and/or conjugate components, the phase shift can be measured. Superior performance can be obtained by balancing gain between the (first and third) nonlinear sections. Non-fiber, for example photonic integrated circuit, embodiments are disclosed. Differential sensing, alternative detection schemes, sensing applications, associated methods, and other variations are disclosed.

42 ENGINEERING↗
DOE OSTI2020

SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators

Next generation systems, such as edge devices, will have to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. This paper discusses the SODA synthesizer, an automated open source high-level ML framework-to-Verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets based on the LLVM infrastructure. The SODA synthesizers will allow implementing optimal designs by combining templated and fully tunable IPs and macros, and fully custom components generated through high-level synthesis. All these components will be provided through an extendable resource library, characterized with both commercial and open source logic design flows. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimension

Minutoli, Marco↗
DOE OSTI2021

Cryogenic Electronics development for High Energy Physics

In the quest to study the fundamental nature of matterand the universe, High Energy Physics (HEP) experimentsoften operate in extreme conditions that lie well outside thestandard operating range of integrated circuits. Two prominentexamples of such extreme environments are the irradiationlevels experienced at high luminosity colliders, as well asoperation at cryogenic temperatures. Cryogenic electronicsis a broad term that encompasses circuits operating at temperatures below the standard operating limit (-55°C in the caseof military grade electronics), all the way down to millikelvin,as in the case of superconducting circuits. Cryogenic circuitshave a long history and have found applications in abroad spectrum of applications, such as infrared focal planearrays, PET, quantum science. While CMOS circuits have beenreliably operated at deep cryogenic temperatures (<4.2K),this article focuses on applications down to liquid Nitrogen(77K), and provides an overview on the design considerations,benefits, and unique challenges pertaining to cryogenic CMOSICs for large HEP experiments.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

High-frequency vacuum electronic device

A self-assembling element fabricated using integrated circuit techniques may provide a small diameter helical conductor surrounding an electron beam for the construction of a vacuum electronic device such as a traveling-wave tube for terahertz scale signal.

van der Weide, Daniel W.↗
DOE OSTI2021

Electroabsorption optical modulator

An electroabsorption modulator that operates based on electroabsorption of a surface plasmon polariton mode is improved by various structural changes and/or selection of different materials. For example, at least a portion of the waveguide may be made to be conductive, e.g., by doping. Also, layers that make up the modulator structure may be placed along sides of waveguides in addition to or instead of simply on the top thereof. High permittivity gate dielectric materials may be employed. Also, materials other than ITO may be employed as a transparent conductor. Such an improved plasmonic electroabsorption modulator can be fabricated using standard semiconductor processing techniques and may be integrated with standard photonic integrated circuits, including silicon photonics and compound semiconductor-based platforms. Advantageously, high-speed, low-voltage operation over a wide spectrum of wavelengths may be achieved.

Wood, Michael↗
DOE OSTI2021

Method and apparatus for mitigating row hammer attacks

An integrated circuit includes an aggressor wordline cache and logic that determines a candidate upper adjacent address and a candidate lower adjacent address of a target memory row corresponding to a read request to memory. When at least one of the candidate upper adjacent address or the candidate lower adjacent address are determined to be a victim row, the logic checks the aggressor wordline cache for a cache hit for the target memory row. When there is a cache hit in the aggressor wordline cache, the logic sends a corresponding cache line as a response to the read request, otherwise the logic causes a read of content from the memory. In certain examples, the logic includes a stored bit array and a hash function-based filter, which determines whether any of the candidate upper adjacent address and the candidate lower adjacent address are victim rows represented in the stored bit array.

SeyedzadehDelcheh, SeyedMohammad↗