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NASA NTRS1997

Sequence information signal processor for local and global string comparisons

A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software. Each sequence can be assigned different deletion and insertion weight functions. Each processor is provided with a similarity measure device which is independently variable. Thus, each processor can contribute to maximum value score calculation using a different similarity measure.

Peterson, John C.↗

NASA NTRS2008

Group-III Nitride Field Emitters

Field-emission devices (cold cathodes) having low electron affinities can be fabricated through lattice-mismatched epitaxial growth of nitrides of elements from group III of the periodic table. Field emission of electrons from solid surfaces is typically utilized in vacuum microelectronic devices, including some display devices. The present field-emission devices and the method of fabricating them were developed to satisfy needs to reduce the cost of fabricating field emitters, make them compatible with established techniques for deposition of and on silicon, and enable monolithic integration of field emitters with silicon-based driving circuitry. In fabricating a device of this type, one deposits a nitride of one or more group-III elements on a substrate of (111) silicon or other suitable material. One example of a suitable deposition process is chemical vapor deposition in a reactor that contains plasma generated by use of electron cyclotron resonance. Under properly chosen growth conditions, the large mismatch between the crystal lattices of the substrate and the nitride causes strains to accumulate in the growing nitride film, such that the associated stresses cause the film to crack. The cracks lie in planes parallel to the direction of growth, so that the growing nitride film becomes divided into microscopic growing single-crystal columns. The outer ends of the fully-grown columns can serve as field-emission tips. By virtue of their chemical compositions and crystalline structures, the columns have low work functions and high electrical conductivities, both of which are desirable for field emission of electrons. From examination of transmission electron micrographs of a prototype device, the average column width was determined to be about 100 nm and the sharpness of the tips was determined to be characterized by a dimension somewhat less than 100 nm. The areal density of the columns was found to about 5 x 10(exp 9)/sq cm . about 4 to 5 orders of magnitude greater than the areal density of tips in prior field-emission devices. The electric field necessary to turn on the emission current and the current per tip in this device are both lower than in prior field-emission devices, such that it becomes possible to achieve longer operational lifetime. Moreover, notwithstanding the lower current per tip, because of the greater areal density of tips, it becomes possible to achieve greater current density averaged over the cathode area. The thickness of the grown nitride film (equivalently, the length of the columns) could lie between about 0.5 microns and a few microns; in any event, a thickness of about 1 micron is sufficient and costs less than do greater thicknesses. It may be possible to grow nitride emitter columns on glass or other substrate materials that cost less than silicon does. What is important in the choice of substrate material is the difference between the substrate and nitride crystalline structures. Inasmuch as the deposition process is nondestructive, an ability to grow emitter columns on a variety of materials would be advantageous in that it would facilitate the integration of field-emitter structures onto previously processed integrated circuits.

Bensaoula, Abdelhak↗

NASA NTRS1982

On implementing self-checking microprocessors

A simple and general model of the interfaces and check circuits used for comparing and detecting faults in a pair of 16-bit processors is described, and problems encountered in the application of TI 9900 processors are discussed. The greatest incompatibility is found to lie between the rollback structures of the CPUs and the interface and check logic (ICL) model. The ICL model generates a reset when an error is detected, and a rollback is expected to occur when it is released. The TI 9900 requires a reset of minimum duration, and after release goes through an initialization cycle, obtains rollback parameters from fixed memory locations, and executes the rollback, consistent with the ICL. The ICL is relatively simple, having a complexity equivalent to fewer than 1000 gates.

Rennels, D. A.↗

NASA NTRS2011

Binary-Signal Recovery

Binary communication through long cables, opto-isolators, isolating transformers, or repeaters can become distorted in characteristic ways. The usual solution is to slow the communication rate, change to a different method, or improve the communication media. It would help if the characteristic distortions could be accommodated at the receiving end to ease the communication problem. The distortions come from loss of the high-frequency content, which adds slopes to the transitions from ones to zeroes and zeroes to ones. This weakens the definition of the ones and zeroes in the time domain. The other major distortion is the reduction of low frequency, which causes the voltage that defines the ones or zeroes to drift out of recognizable range. This development describes a method for recovering a binary data stream from a signal that has been subjected to a loss of both higher-frequency content and low-frequency content that is essential to define the difference between ones and zeroes. The method makes use of the frequency structure of the waveform created by the data stream, and then enhances the characteristics related to the data to reconstruct the binary switching pattern. A major issue is simplicity. The approach taken here is to take the first derivative of the signal and then feed it to a hysteresis switch. This is equivalent in practice to using a non-resonant band pass filter feeding a Schmitt trigger. Obviously, the derivative signal needs to be offset to halfway between the thresholds of the hysteresis switch, and amplified so that the derivatives reliably exceed the thresholds. A transition from a zero to a one is the most substantial, fastest plus movement of voltage, and therefore will create the largest plus first derivative pulse. Since the quiet state of the derivative is sitting between the hysteresis thresholds, the plus pulse exceeds the plus threshold, switching the hysteresis switch plus, which re-establishes the data zero to one transition, except now at the logic levels of the receiving circuit. Similarly, a transition from a one to a zero will be the most substantial and fastest minus movement of voltage and therefore will create the largest minus first derivative pulse. The minus pulse exceeds the minus threshold, switching the hysteresis switch minus, which re-establishes the data one to zero transition. This innovation has a large increase in tolerance for the degradation of the binary pattern of ones and zeroes, and can reject the introduction of noise in the form of low frequencies that can cause the voltage pattern to drift up or down, and also higher frequencies that are beyond the recognizable content in the binary transitions.

Griebeler, Elmer L.↗

NASA NTRS1995

Formal development of a clock synchronization circuit

This talk presents the latest stage in formal development of a fault-tolerant clock synchronization circuit. The development spans from a high level specification of the required properties to a circuit realizing the core function of the system. An abstract description of an algorithm has been verified to satisfy the high-level properties using the mechanical verification system EHDM. This abstract description is recast as a behavioral specification input to the Digital Design Derivation system (DDD) developed at Indiana University. DDD provides a formal design algebra for developing correct digital hardware. Using DDD as the principle design environment, a core circuit implementing the clock synchronization algorithm was developed. The design process consisted of standard DDD transformations augmented with an ad hoc refinement justified using the Prototype Verification System (PVS) from SRI International. Subsequent to the above development, Wilfredo Torres-Pomales discovered an area-efficient realization of the same function. Establishing correctness of this optimization requires reasoning in arithmetic, so a general verification is outside the domain of both DDD transformations and model-checking techniques. DDD represents digital hardware by systems of mutually recursive stream equations. A collection of PVS theories was developed to aid in reasoning about DDD-style streams. These theories include a combinator for defining streams that satisfy stream equations, and a means for proving stream equivalence by exhibiting a stream bisimulation. DDD was used to isolate the sub-system involved in Torres-Pomales' optimization. The equivalence between the original design and the optimized verified was verified in PVS by exhibiting a suitable bisimulation. The verification depended upon type constraints on the input streams and made extensive use of the PVS type system. The dependent types in PVS provided a useful mechanism for defining an appropriate bisimulation.

Miner, Paul S.↗

NASA NTRS1993

Algorithms for high-speed universal noiseless coding

This paper provides the basic algorithmic definitions and performance characterizations for a high-performance adaptive noiseless (lossless) 'coding module' which is currently under separate developments as single-chip microelectronic circuits at two NASA centers. Laboratory tests of one of these implementations recently demonstrated coding rates of up to 900 Mbits/s. Operation of a companion 'decoding module' can operate at up to half the coder's rate. The functionality provided by these modules should be applicable to most of NASA's science data. The hardware modules incorporate a powerful adaptive noiseless coder for 'standard form' data sources (i.e., sources whose symbols can be represented by uncorrelated nonnegative integers where the smaller integers are more likely than the larger ones). Performance close to data entries can be expected over a 'dynamic range' of from 1.5 to 12-15 bits/sample (depending on the implementation). This is accomplished by adaptively choosing the best of many Huffman equivalent codes to use on each block of 1-16 samples. Because of the extreme simplicity of these codes no table lookups are actually required in an implementation, thus leading to the expected very high data rate capabilities already noted.

Rice, Robert F.↗

NASA NTRS2013

New Class of Flow Batteries for Terrestrial and Aerospace Energy Storage Applications

Future sustainable energy generation technologies such as photovoltaic and wind farms require advanced energy storage systems on a massive scale to make the alternate (green) energy options practical. The daunting requirements of such large-scale energy systems such as long operating and cycle life, safety, and low cost are not adequately met by state-of-the-art energy storage technologies such as vanadium flow cells, lead-acid, and zinc-bromine batteries. Much attention is being paid to redox batteries specifically to the vanadium redox battery (VRB) due to their simplicity, low cost, and good life characteristics compared to other related battery technologies. NASA is currently seeking high-specific- energy and long-cycle-life rechargeable batteries in the 10-to-100-kW range to support future human exploration missions, such as planetary habitats, human rovers, etc. The flow batteries described above are excellent candidates for these applications, as well as other applications that propose to use regenerative fuel cells. A new flow cell technology is proposed based on coupling two novel electrodes in the form of solvated electron systems (SES) between an alkali (or alkaline earth) metal and poly aromatic hydrocarbons (PAH), separated by an ionically conducting separator. The cell reaction involves the formation of such SES with a PAH of high voltage in the cathode, while the alkali (or alkaline earth metal) is reduced from such an MPAH complex in the anode half-cell. During recharge, the reactions are reversed in both electrodes. In other words, the alkali (alkaline earth) metal ion simply shuttles from one M-PAH complex (SES) to another, which are separated by a metal-ion conducting solid or polymer electrolyte separator. As an example, the concept was demonstrated with Li-naphthalene//Li DDQ (DDQ is 2,3-Dichloro-5,6-dicyano- 1,4-benzoquinone) separated by lithium super ion conductor, either ceramic or polymer (solid polymer or gel polymer) electrolytes. The reactants are Li-naphthalene dissolved in tetrahydrofuran (THF) with a lithium salt of 1M LiBF4 (lithium tetra fluoroborate) in the anode compartment, and DDQ again dissolved in THF and also containing 1M LiBF4 salt in the cathode half-cell. The solid electrolyte separator used in the first set of experiments is a ceramic solid electrolyte, available from a commercial source. The open circuit voltage of the cells is close to 3.0 V, as expected from the individual half-cell voltages of Li-naphthalene and Li-DDQ. Upon discharge, the cell shows steady discharge voltage of 2.7 V, which confirms that the electrochemical processes do involve lithium ion shuttling from the anodic compartment to the cathode half-cell. The reversibility or rechargeability is demonstrated by charging the partially discharged cells (i.e., with lithium present in the DDQ half). Once again, a steady voltage close to 3.0 V was observed during charge, indicating that the system is quite reversible. In the subsequent concept-demonstration studies, the ceramic electrolyte has been replaced with a gel polymer electrolyte, e.g., PVDF-HFP (poly vinylene difluoride hexafluoropropene) gel, which has several advantages such as high ionic conductivity (almost comparable to liquid electrolyte and about 2 orders of magnitude better than the ceramic equivalent), lower cost, and possibly higher chemical stability at the anode. In addition, it can be bonded to the electrode by thermal fusion to form membrane electrode assemblies (MEAs), as is done in fuel cells.

Bugga, Ratnakumar V.↗

NASA NTRS2019

Development of a High-Propellant Throughput Small Spacecraft Electric Propulsion System to Enable Lower Cost NASA Science Missions

This paper describes recent progress at the NASA Glenn Research Center (GRC) in the development and demonstration of an integrated high-propellant throughput small spacecraft electric propulsion (HT-SSEP) system based on a Hall-effect thruster. A center-mounted cathode and an innovative magnetic circuit topology were implemented in the design of the Hall-effect thruster to achieve high-propellant throughput, high performance, and efficient packaging. To minimize technical risk, the HT-SSEP development approach sought to limit design features and materials to those with a clear path-to-flight. A propellant throughput capability of greater than 100 kg at a minimum thruster efficiency of 50% was targeted. The proof-of-concept NASA-H64M laboratory model (LM) thruster was designed, fabricated, and tested at GRC in fiscal year 2018. The thruster development leveraged heritage Hall-effect thruster design and manufacturing processes wherever appropriate. Recent NASA advances in Hall-effect thruster technology were also leveraged. A scalable discharge power supply (DPS) capable of powering the H64M-LM was developed, then demonstrated as part of an integrated system test. The DPS uses commercial off-the-shelf components with spaceflight equivalents. A keeper supply with DC ignitor was breadboarded, then demonstrated with a laboratory cathode. Finally, feed system trade studies were performed to ascertain what feed system architecture might be appropriate for an HT-SSEP system. This paper details the motivations for the project, the development approach, the chosen sub-system architectures, design considerations, and test results.

Benavides, Gabriel F.↗

NASA NTRS2019

Development of a High-Propellant Throughput Small Spacecraft Electric Propulsion System to Enable Lower Cost NASA Science Missions

Benavides, Gabriel F.↗

NASA NTRS2019

Development of a High-Propellant Throughput Small Spacecraft Electric Propulsion System (HT-SSEP) to Enable Lower Cost NASA Science Missions

Discusses progress at the NASA Glenn Research Center (GRC) in the development and demonstration of an integrated high-propellant throughput small spacecraft electric propulsion (HT-SSEP) system based on a Hall-effect thruster. A center-mounted cathode and an innovative magnetic circuit topology were implemented in the design of the Hall-effect thruster to achieve high-propellant throughput, high performance, and efficient packaging. To minimize technical risk, the HT-SSEP development approach sought to limit design features and materials to those with a clear path-to-flight. A propellant throughput capability of greater than 100 kilograms at a minimum thruster efficiency of 50 percent was targeted. The proof-of-concept NASA-H64M laboratory model (LM) thruster was designed, fabricated, and tested at GRC in fiscal year 2018. The thruster development leveraged heritage Hall-effect thruster design and manufacturing processes wherever appropriate. Recent NASA advances in Hall-effect thruster technology were also leveraged. A scalable discharge power supply (DPS) capable of powering the H64M-LM was developed, then demonstrated as part of an integrated system test. The DPS uses commercial off-the-shelf components with spaceflight equivalents. A keeper supply with DC ignitor was breadboarded, then demonstrated with a laboratory cathode. Finally, feed system trade studies were performed to ascertain what feed system architecture might be appropriate for an HT-SSEP system. This paper details the motivations for the project, the development approach, the chosen sub-system architectures, design considerations, and test results.

Benavides, Gabriel↗

NASA NTRS1994

P/N InP solar cells on Ge wafers

Indium phosphide (InP) P-on-N one-sun solar cells were epitaxially grown using a metalorganic chemical vapor deposition process on germanium (Ge) wafers. The motivation for this work is to replace expensive InP wafers, which are fragile and must be thick and therefore heavy, with less expensive Ge wafers, which are stronger, allowing use of thinner, lighter weight wafers. An intermediate InxGs1-xP grading layer starting as In(0.49)Ga(0.51) at the GaAs-coated Ge wafer surface and ending as InP at the top of the grading layer (backside of the InP cell) was used to attempt to bend some of the threading dislocations generated by lattice-mismatch between the Ge wafer and InP cell so they would be harmlessly confined in this grading layer. The best InP/Ge cell was independently measured by NASA-Lewis with a one-sun 25 C AMO efficiently measured by NASA-Lewis with a one-circuit photocurrent 22.6 mA/sq cm. We believe this is the first published report of an InP cell grown on a Ge wafer. Why get excited over a 9 percent InP/Ge cell? If we look at the cell weight and efficiency, a 9 percent InP cell on an 8 mil Ge wafer has about the same cell power density, 118 W/kg (BOL), as the best InP cell ever made, a 19 percent InP cell on an 18 mil InP wafer, because of the lighter Ge wafer weight. As cell panel materials become lighter, the cell weight becomes more important, and the advantage of lightweight cells to the panel power density becomes more important. In addition, although InP/Ge cells have a low beginning-of-life (BOL) efficiency due to dislocation defects, the InP/Ge cells are very radiation hard (end-of-life power similar to beginning-of-life). We have irradiated an InP/Ge cell with alpha particles to an equivalent fluence of 1.6 x 10(exp 16) 1 MeV electrons/sq cm and the efficiency is still 83 percent of its BOL value. At this fluence level, the power output of these InP/Ge cells matches the GaAs/Ge cell data tabulated in the JPL handbook. Data are presented indicating InP/Ge has more power output than GaAs/Ge cells at fluences in excess of this value.

Wojtczuk, Steven↗

NASA NTRS1980

Superconducting bearings for application in cryogenic experiments in space

Linear superconducting magnetic bearings suitable for use in a proposed orbital equivalence principle experiment and for general application in space were developed and tested. Current flows in opposite directions in adjacent superconducting wires arranged parallel to the axis of a cylinder. This configuration provides maximum stiffness radially while allowing the test mass to move freely along the cylinder axis. In a space application, the wires are extended to cover the entire perimeter of the cylinder: for the earth-based tests it was desirable to use only the bottom half. Control of the axial position of the test mass is by small control coils which may be positioned inside or outside the main bearing. The design is suitable for application to other geometries where maximum stiffness is desired. A working model scaled to operate in a 1-g environment was perfected approximate solutions for the bearings were developed. A superconducting transformer method of charging the magnets for the bearing, and a position detector based on a SQUID magnetometer and associated superconducting circuit were also investigated.

Everitt, C. W. F.↗

NASA NTRS2012

Downsampling Photodetector Array with Windowing

In a photon counting detector array, each pixel in the array produces an electrical pulse when an incident photon on that pixel is detected. Detection and demodulation of an optical communication signal that modulated the intensity of the optical signal requires counting the number of photon arrivals over a given interval. As the size of photon counting photodetector arrays increases, parallel processing of all the pixels exceeds the resources available in current application-specific integrated circuit (ASIC) and gate array (GA) technology; the desire for a high fill factor in avalanche photodiode (APD) detector arrays also precludes this. Through the use of downsampling and windowing portions of the detector array, the processing is distributed between the ASIC and GA. This allows demodulation of the optical communication signal incident on a large photon counting detector array, as well as providing architecture amenable to algorithmic changes. The detector array readout ASIC functions as a parallel-to-serial converter, serializing the photodetector array output for subsequent processing. Additional downsampling functionality for each pixel is added to this ASIC. Due to the large number of pixels in the array, the readout time of the entire photodetector is greater than the time between photon arrivals; therefore, a downsampling pre-processing step is done in order to increase the time allowed for the readout to occur. Each pixel drives a small counter that is incremented at every detected photon arrival or, equivalently, the charge in a storage capacitor is incremented. At the end of a user-configurable counting period (calculated independently from the ASIC), the counters are sampled and cleared. This downsampled photon count information is then sent one counter word at a time to the GA. For a large array, processing even the downsampled pixel counts exceeds the capabilities of the GA. Windowing of the array, whereby several subsets of pixels are designated for processing, is used to further reduce the computational requirements. The grouping of the designated pixel frame as the photon count information is sent one word at a time to the GA, the aggregation of the pixels in a window can be achieved by selecting only the designated pixel counts from the serial stream of photon counts, thereby obviating the need to store the entire frame of pixel count in the gate array. The pixel count se quence from each window can then be processed, forming lower-rate pixel statistics for each window. By having this processing occur in the GA rather than in the ASIC, future changes to the processing algorithm can be readily implemented. The high-bandwidth requirements of a photon counting array combined with the properties of the optical modulation being detected by the array present a unique problem that has not been addressed by current CCD or CMOS sensor array solutions.

Patawaran, Ferze D.↗

NASA NTRS1992

Multi-access laser communications terminal

The Optical Multi-Access (OMA) Terminal is capable of establishing up to six simultaneous high-data-rate communication links between low-Earth-orbit satellites and a host satellite at synchronous orbit with only one 16-inch-diameter antenna on the synchronous satellite. The advantage over equivalent RF systems in space weight, power, and swept volume is great when applied to NASA satellite communications networks. A photograph of the 3-channel prototype constructed under the present contract to demonstrate the feasibility of the concept is presented. The telescope has a 10-inch clear aperture and a 22 deg full field of view. It consists of 4 refractive elements to achieve a telecentric focus, i.e., the focused beam is normal to the focal plane at all field angles. This feature permits image pick-up optics in the focal plane to track satellite images without tilting their optic axes to accommodate field angle. The geometry of the imager-pick-up concept and the coordinate system of the swinging arm and disk mechanism for image pick-up are shown. Optics in the arm relay the telescope focus to a communications and tracking receiver and introduce the transmitted beacon beam on a path collinear with the receive path. The electronic circuits for the communications and tracking receivers are contained on the arm and disk assemblies and relay signals to an associated PC-based operator's console for control of the arm and disk motor drive through a flexible cable which permits +/- 240 deg travel for each arm and disk assembly. Power supplies and laser transmitters are mounted in the cradle for the telescope. A single-mode fiber in the cable is used to carry the laser transmitter signal to the arm optics. The promise of the optical multi-access terminal towards which the prototype effort worked is shown. The emphasis in the prototype development was the demonstration of the unique aspect of the concept, and where possible, cost avoidance compromises were implemented in areas already proven on other programs. The design details are described in section 2, the prototype test results in section 3, additional development required in section 4, and conclusions in section 5.

Source record↗

NASA NTRS1987

Rupture testing for the quality control of electrodeposited copper interconnections in high-speed, high-density circuits

Printed Wiring Multilayer Board (PWMLB) structures for high speed, high density circuits are prone to failure due to the microcracking of electrolytic copper interconnections. The failure can occur in the foil that makes up the inner layer traces or in the plated through holes (PTH) deposit that forms the layer to layer interconnections. It is shown that there are some distinctive differences in the quality of Type E copper and that these differences can be detected before its use in a PWMLB. It is suggested that the strength of some Type E copper can be very low when the material is hot and that it is the use of this poor quality material in a PWMLB that results in PTH and inner layer microcracking. Since the PWMLB failure in question are induced by a thermal stress, and since the poorer grades of Type E materials used in these structures are susceptible to premature failure under thermal stress, the use of elevated temperature rupture and creep rupture testing is proposed as a means for screening copper foil, or its PTH equivalent, in order to eliminate the problem of Type E copper microcracking in advanced PWMLBs.

Zakraysek, Louis↗

NASA NTRS2003

Block QCA Fault-Tolerant Logic Gates

Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits. The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and Hybrid VLSI/QCA Architecture for Computing FFTs (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantummechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Heretofore, researchers have recognized two major obstacles to realization of QCA-based logic gates: One is the need for (and the difficulty of attaining) operation of QCA circuitry at room temperature or, for that matter, at any temperature above a few Kelvins. It has been theorized that room-temperature operation could be made possible by constructing QCA as molecular-scale devices. However, in approaching the lower limit of miniaturization at the molecular level, it becomes increasingly imperative to overcome the second major obstacle, which is the need for (and the difficulty of attaining) high precision in the alignments of adjacent QCA in order to ensure the correct interactions among the quantum dots.

Firjany, Amir↗

NASA NTRS2003

Bit-Serial Adder Based on Quantum Dots

A proposed integrated circuit based on quantum-dot cellular automata (QCA) would function as a bit-serial adder. This circuit would serve as a prototype building block for demonstrating the feasibility of quantum-dots computing and for the further development of increasingly complex and increasingly capable quantum-dots computing circuits. QCA-based bit-serial adders would be especially useful in that they would enable the development of highly parallel and systolic processors for implementing fast Fourier, cosine, Hartley, and wavelet transforms. The proposed circuit would complement the QCA-based circuits described in "Implementing Permutation Matrices by Use of Quantum Dots" (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42 and "Compact Interconnection Networks Based on Quantum Dots" (NPO-20855), which appears elsewhere in this issue. Those articles described the limitations of very-large-scale-integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCA-based signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes. To enable a meaningful description of the proposed bit-serial adder, it is necessary to further recapitulate the description of a quantum-dot cellular automation from the first-mentioned prior article: A quantum-dot cellular automaton contains four quantum dots positioned at the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantum-mechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Again, for reasons too complex to describe here, in order to ensure accuracy and timeliness of the output of a QCA array, it is necessary to resort to an adiabatic switching scheme in which the QCA array is divided into subarrays, each controlled by a different phase of a multiphase clock signal. In this scheme, each subarray is given time to perform its computation, then its state is frozen by raising its inter-dot potential barriers and its output is fed as the input to the successor subarray. The successor subarray is kept in an unpolarized state so it does not influence the calculation of preceding subarray. Such a clocking scheme is consistent with pipeline computation in the sense that each different subarray can perform a different part of an overall computation. In other words, QCA arrays are inherently suitable for pipeline and, moreover, systolic computations. This sequential or pipeline aspect of QCA would be utilized in the proposed bit-serial adders.

Fijany, Amir↗

NASA NTRS1995

Recent Developments in Quantum-Well Infrared Photodetectors

Intrinsic infrared (IR) detectors in the long wavelength range (8-20 Am) are based on an optically excited interband transition, which promotes an electron across the band gap (E(sub g)) from the valence band to the conduction band as shown. These photoelectrons can be collected efficiently, thereby producing a photocurrent in the external circuit. Since the incoming photon has to promote an electron from the valence band to the conduction band, the energy of the photon (h(sub upsilon)) must be higher than the E(sub g) of the photosensitive material. Therefore, the spectral response of the detectors can be controlled by controlling the E(sub g) of the photosensitive material. Examples for such materials are Hg(1-x), Cd(x), Te, and Pb(1-x), Sn(x), Te, in which the energy gap can be controlled by varying x. This means detection of very-long-wavelength IR radiation up to 20 microns requires small band gaps down to 62 meV. It is well known that these low band gap materials, characterized by weak bonding and low melting points, are more difficult to grow and process than large-band gap semiconductors such as GaAs. These difficulties motivate the exploration of utilizing the intersub-band transitions in multiquantum well (MQW) structures made of more refractory large-band gap semiconductors. The idea of using MQW structures to detect IR radiation can be explained by using the basic principles of quantum mechanics. The quantum well is equivalent to the well-known particle in a box problem in quantum mechanics, which can be solved by the time independent Schroudiner equation.

Gunapala, S. D.↗