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Circuit voltage output is reduced by voltage equivalent to ampere resistance drop of nonlogarithmic resistances of practical diodes; therefore, output is same as circuit using ideal diode. Circuit applies to meter and electronic recorder movements, and improves performance of radiation detectors and several microbiological monitoring devices
Improved rotary transformer for Inductosyn (or equivalent) shaft-position-indicating circuit has pair of ferrite cores instead of the solid-iron cores. Designed with view toward decreasing excitation power (to maximum allowable 2 W) supplied to shaft-position-indicating circuit to increase its output signal and make tracking system less vulnerable to electromagnetic interference.
New circuit leakage reduced by shunting current through saturated input at operational-amplifier follower already part of Howland, or equivalent, current source. Typical application is in circuit of germanium resistance thermometer in cryogenic system.
Digital pulse-width-modulation circuit provides programmable duration from 1 microsecond to full on, at repetition rate of 1 kHz. Designed for use in controlling CO2 laser, also used in applications in which precision and flexibility of digital control of pulse durations needed. Circuit incorporates low-power Schottky transistor/transistor-logic (TTL) devices in critical high-speed parts. Designed in TTL to make it compatible with Pro-Log 7914 (or equivalent) decoder input/output (I/O) utility printed-circuit card.
This paper is concerned with the application of optics to digital computing. A Hughes liquid crystal light valve is used as an active optical element where a weak light beam can control a strong light beam with either a positive or negative gain characteristic. With this device as the central element the ability to produce bistable states from which different types of flip-flop can be implemented is demonstrated. In this paper, some general comments are first presented on digital computing as applied to optics. This is followed by a discussion of optical implementation of various types of flip-flop. These flip-flops are then used in the design of optical equivalents to a few simple sequential circuits such as shift registers and accumulators. As a typical sequential machine, a schematic layout for an optical binary temporal integrator is presented. Finally, a suggested experimental configuration for an optical master-slave flip-flop array is given.
Parametrized and random unitary (or orthogonal) n-qubit circuits play a central role in quantum information. As such, one could naturally assume that circuits implementing symplectic transformations would attract similar attention. However, this is not the case, as $\mathbb{SP}(d/2)$—the group of d × d unitary symplectic matrices—has thus far been overlooked. In this work, we aim at starting to fill this gap. We begin by presenting a universal set of generators $\mathcal{G}$ for the symplectic algebra $\mathfrak{sp}(d/2)$, consisting of one- and two-qubit Pauli operators acting on neighboring sites in a one-dimensional lattice. Here, we uncover two critical differences between such set, and equivalent ones for unitary and orthogonal circuits. Namely, we find that the operators in $\mathcal{G}$ cannot generate arbitrary local symplectic unitaries and that they are not translationally invariant. We then review the Schur–Weyl duality between the symplectic group and the Brauer algebra, and use tools from Weingarten calculus to prove that Pauli measurements at the output of Haar random symplectic circuits can converge to Gaussian processes. As a by-product, such analysis provides us with concentration bounds for Pauli measurements in circuits that form t-designs over $\mathbb{SP}(d/2)$. To finish, we present tensor-network tools to analyze shallow random symplectic circuits, and we use these to numerically show that computational-basis measurements anti-concentrate at logarithmic depth.
In a breakthrough work, Bravyi, Gosset, and König (BGK) [Science 362, 308 (2018)] unconditionally proved that constant-depth quantum circuits are more powerful than their classical counterparts. Here, their result is equivalent to saying that a particular family of constant-depth quantum circuits takes classical circuits at least Ω(logn) depth to “simulate,” in a certain sense. In our paper, we formalize their sense of simulation, which we call “possibilistic simulation” or “p-simulation,” and construct explicit classical circuits that can p-simulate any depth-d quantum circuit with Clifford and t T-gates in depth O(d+t). Our classical circuits use {NOT,AND,OR} gates of fan-in ≤ 2.
The reliability of solder joints in the solar cell metallization-interconnect system influences the lifetime of photovoltaic modules. Two field-aged modules-one with Sn 62 Pb 36 Ag 2 solder at the solder joints (Solarex MSX 60), and the other with the standard Sn 60 Pb 40 solder (Siemens M55)-were subjected to a modified thermal cycling (TC) test of IEC 61215. Three sections in each module were maintained at 85 degrees C, 95 degrees C, and 105 degrees C during the 15-minute high temperature dwell time. Current equivalent to the module short-circuit current was injected through the module when the chamber temperature was above 25 degrees C to simulate regular field operation. This novel approach aims to induce thermomechanical fatigue (TMF) at the solder joints and intermetallic compound (IMC) formation at the metal/solder interfaces. The activation energy (E a ) for solder bond degradation was calculated based on the series resistance (R s ) increase in TC testing rather than power drop to avoid the effect of confounding variables. Module-level R s increase in MSX 60 module after TC800 cycles and in M55 module after TC400 cycles was 1.22% and 183.7%, respectively. The E a determined for the module with 2wt% Ag is 0.24 eV and for that with the standard solder is 0.27 eV. The solder bond degradation seems to have been driven by TMF rather than IMC formation for both modules.
Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.
A special-purpose computer code for a deformable-mirror adaptive-optics control system transmits pixel-registered control from (1) a personal computer running software that generates the control data to (2) a circuit board with 128 digital-to-analog converters (DACs) that generate voltages to drive the deformable-mirror actuators. This program reads control-voltage codes from a text file, then sends them, via the computer s parallel port, to a circuit board with four AD5535 (or equivalent) chips. Whereas a similar prior computer program was capable of transmitting data to only one chip at a time, this program can send data to four chips simultaneously. This program is in the form of C-language code that can be compiled and linked into an adaptive-optics software system. The program as supplied includes source code for integration into the adaptive-optics software, documentation, and a component that provides a demonstration of loading DAC codes from a text file. On a standard Windows desktop computer, the software can update 128 channels in 10 ms. On Real-Time Linux with a digital I/O card, the software can update 1024 channels (8 boards in parallel) every 8 ms.
Using a control variable, the functionality of Polymorphic circuits can be modified, making them adaptable and useful for reconfiguring circuit behavior — all the way from gate level to system level. State-of-the art polymorphic circuits are based on custom non-linear circuit design or emerging devices such as ambipolar FET, configurable magnetic devices etc. While some of these approaches are inefficient in performance, others involve exotic devices. The Crosstalk computing based polymorphic circuits offer a fresh perspective. In Crosstalk, the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit the programmable Boolean logic behavior. This approach relies on the coupling between metal lines and not on the transistors for computing, resulting in better scalability, security by obscurity, and fault tolerance by reconfiguration. Our novel approach is backed by the mathematical formulation that conveys the rationale to generalize and achieve a wide variety of polymorphic circuits. Our experiments, including design, simulation, and Power Performance Area (PPA) characterization results indicate that crosstalk circuits provide significant improvement in transistor count (about 3x), switching energy (2x), and speed (1.5x) for polymorphic logic circuits. In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. Our scalability study uses Open Source 7 nm PDK, considers all process variation aspects and accommodates worst-case scenarios. The study results for various benchmark circuits show that the Crosstalk technology is a viable alternative to CMOS for digital logic implementations below 10 nm, having 48% density, 57% power, and 10% performance gains over equivalent CMOS counterparts. Finally, we compare Crosstalk Polymorphic Circuit design technique with similar approaches described in related works and discuss its features and constraints.
Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.
Here unitary evolution under a time-dependent Hamiltonian is a key component of simulation on quantum hardware. Synthesizing the corresponding quantum circuit is typically done by breaking the evolution into small time steps, also known as Trotterization, which leads to circuits the depth of which scales with the number of steps. When the circuit elements are limited to a subset of SU(4) - or equivalently, when the Hamiltonian may be mapped onto free fermionic models - several identities exist that combine and simplify the circuit. Based on this, we present an algorithm that compresses the Trotter steps into a single block of quantum gates using algebraic relations between adjacent circuit elements. This results in a fixed depth time evolution for certain classes of Hamiltonians. We explicitly show how this algorithm works for several spin models, and demonstrate its use for adiabatic state preparation of the transverse field Ising model.
Current loop circuitry replaced Wheatstone bridge circuitry to signal-condition strain gage transducers in more than 350 data channels for two different test programs at NASA Dryden Flight Research Center. The uncorrected test data from current loop circuitry had a lower noise level than data from comparable Wheatstone bridge circuitry, were linear with respect to gage-resistance change, and were uninfluenced by varying lead-wire resistance. The current loop channels were easier for the technicians to set up, verify, and operate than equivalent Wheatstone bridge channels. Design choices and circuit details are presented in this paper in addition to operational experience.
Proton testing of linear circuits has identified devices where significantly more damage occurs at equivalent total dose levels with protons than tests with gamma rays.
An approach to predict the susceptibility of digital systems to signal disturbances is described. Electrical disturbances on a digital system's input and output lines can be induced by activities and conditions including static electricity, lightning discharge, electromagnetic interference (EMI), and electromagnetic pulsation (EMP). The electrical signal disturbances employed for the susceptibility study were limited to nondestructive levels, i.e., the system does not sustain partial or total physical damage and reset and/or reload brings the system to an operational status. The front-end transition from the electrical disturbances to the equivalent digital signals was accomplished by computer-aided circuit analysis. The super-sceptre (system for circuit evaluation of transient radiation effects) programs was used. Gate models were developed according to manufacturers' performance specifications and parameters resulting from construction processes characteristic of the technology. Digital simulation at the gate and functional level was employed to determine the impact of the abnormal signals on system performance and to study the propagation characteristics of these signals through the system architecture. Example results are included for an Intel 8080 processor configuration.
This paper describes an approach to predicting the susceptibility of digital systems to signal disturbances. Electrical disturbances on a digital system's input and output lines can be induced by activities and conditions including static electricity, lightning discharge, Electromagnetic Interference (EMI) and Electromagnetic Pulsation (EMP). The electrical signal disturbances employed for the susceptibility study were limited to nondestructive levels, i.e., the system does not sustain partial or total physical damage and reset and/or reload will bring the system to an operational status. The front-end transition from the electrical disturbances to the equivalent digital signals was accomplished by computer-aided circuit analysis. The Super-Sceptre (system for circuit evaluation of transient radiation effects) Program was used. Gate models were developed according to manufacturers' performance specifications and parameters resulting from construction processes characteristic of the technology. Digital simulation at the gate and functional level was employed to determine the impact of the abnormal signals on system performance and to study the propagation characteristics of these signals through the system architecture. Example results are included for an Intel 8080 processor configuration.
A method for modeling switching-converter power stages is developed, whose starting point is the unified state-space representation of the switched networks and whose end result is either a complete state-space description or its equivalent small-signal low-frequency linear circuit model. A new canonical circuit model is proposed, whose fixed topology contains all the essential input-output and control properties of any dc-to-dc switching converter, regardless of its detailed configuration, and by which different converters can be characterized in the form of a table conveniently stored in a computer data bank to provide a useful tool for computer aided design and optimization. The new canonical circuit model predicts that, in general, switching action introduces both zeros and poles into the duty ratio to output transfer function in addition to those from the effective filter network.