HPC4Mfg with Samsung: Making semiconductor devices cool through HPC ab initio simulations
For decades, the semiconductor technology has followed the Moore’s law, making newer devices more powerful and energy efficient. Recently, however, it has reached a point where the performance and the energy efficiency of the device do not improve with the shrinking device size. One of the fundamental reasons of this deviation from the past trend is the interconnect resistance, which becomes larger with the shrinking size. The devices size is so small that the quantum mechanical effects can no longer be ignored and the traditional continuum simulation tools such as TCAD become inadequate. In this project, Samsung Semiconductor Inc. and Lawrence Berkeley National Laboratory has collaborated to perform first of kind device-scale ab initio simulations to optimize materials and interconnect morphology to minimize interconnect resistance. We have tested the use of LS3DF method and the PEtot_trans approach on top of the folded spectrum method (FSM) Escan code to calculate the scattering state, and to study various effects influence the interconnect conductivity. We found that, the LS3DF can be used to calculate such metallic system. On the other hand, the use of Escan code to solve the linear equation is not practical due to the slow convergence. We have implemented a Chebyshev filter technique to calculate a few hundred eigen states near the scattering state energy E, then use these eigen states as preconditioner to solve the linear equation. We have used this approach to study the different factors which affect the interconnect conductivity, including the shape, the point defect, the temperature, and the grain boundary.