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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 307 records · Page 17
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Modernization efforts for the R -Matrix code SAMMY [Abstract]

The R-Matrix code SAMMY is a widely used nuclear data evaluation code focused on the resolved range, which includes corrections for experimental effects. The code is still mostly written in Fortran 77, and uses a memory management system suitable for the time of its initial writing (1984). A modernization effort is under way to bring the code in-line with modern software development practices. A continuous-integration testing framework was added, automating the large existing set of test cases. It is run on every commit. The memory management was updated to current standard practices suitable for modern software analysis tools. The code can be obtained from https://code.ornl.gov/RNSD/SAMMY. The resonance parameters and covariance information are now stored in C++ objects shared by SAMMY and AMPX, the processing code that generates nuclear data libraries for SCALE. This allows for easier maintenance and access to the resonance parameters inside and outside of SAMMY. This feature is already used by accessing and changing parameters in memory in the Bayesian Monte Carlo Evaluation Framework for Cross Sections Nuclear Data and Integral Benchmark Experiments project, Further plans include the switch to the ENDF reading and writing routines in AMPX, as these routines are more robust, easier to maintain, and support more features. Of note here is support for the new GNDS format. Previously it wasn’t easy to share the full covariance matrix for evaluations containing more than one isotope due to limitations on the ENDF format; this is now supported in GNDS. The data are currently available in a binary SAMMY format and can be exported to GNDS to make them more widely available and sharable. The next step will be to use the same resonance processing code at 0K in AMPX and SAMMY as one of the available Reich-Moore R-Matrix formalism. The first step toward this goal is to isolate the reconstruction into a module that takes resonance parameters as its input and does not depend on SAMMY global parameters. This goal has been achieved and it should now be possible to more easily change the resonance formalism and add enhancements as the Phenomenological R-Matrix parameterization of direct, doorway, and compound nuclear reactions discussed elsewhere on this conference. This concerted modernization and enhancement effort provides multiple advantages to the nuclear data community. It will allow parameter optimization using enhanced formalisms, including experimental effects, that better match complex experimental data. Then those evaluated parameters can immediately be passed off to AMPX to be reconstructed with the exact same cross section model and be put into a data library for subsequent testing using SCALE and the Valid Benchmark suite or other suitable benchmark suites.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
NASA NTRS1974

Quasi-perfect FIFO: Synchronous or asynchronous with application in controller design for the UNICON laser memory

The first-in-first-out memory buffer (FIFO), is an elastic digital memory whose main application is in data buffering between devices operating at different rates. Data written into the top is moved autonomously down toward the bottom of the FIFO to the lowest unoccupied location, and data read from the bottom of the FIFO will cause data from the top to move autonomously down toward the bottom. The FIFO is available in MOS LSI asynchronous form with data rate in the 1 MHz region. The FIFO described yields a simple high-speed iterative implementation, either synchronous of asynchronous. Because of this simple iterative structure, the FIFO is expandable in both number of words and bits per word, and it is attractive from the viewpoint of integrated-circuit production. For the synchronous FIFO, a model was built and successfully used in the controller for the UNICON laser memory. For the asynchronous FIFO, a model was built and also successfully used in a high-performance magnetic tape controller.

Lim, R. S.↗
NASA NTRS2017

How Much is Remembered as a Function of Presentation Modality?

According to a widespread claim often used for teaching recommendations, students remember 10 percent of what they read, 20 percent of what they hear, 30 percent of what they see, and 50 percent of what they see and hear. Clearly, the percentages cannot be correct, and there is no empirical evidence even for the ordering. To investigate the ordering, we used a laboratory paradigm that has already revealed some findings regarding the ordering of modalities for remembering information. In this paradigm, subjects are given messages instructing them to move in a grid of four stacked matrices by clicking a computer mouse. The current experiment compared 3 modalities presented either once, see (visual arrows), hear (auditory words), read (visual words); twice in succession, see see, hear hear, read read; or in two different successive modalities, see hear, hear see, see read, read see, hear read, read hear. We found better performance for messages presented twice than for those presented once, regardless of modality. For the twice-presented messages performance varied as a function of the second modality, with best performance for see and worst for read.

information↗
DOE OSTI2026

Probing boron vacancy defects in hBN via single spin relaxometry

Spin defects in solids offer promising platforms for quantum sensing and memory due to their long coherence times and optical addressability. Here, we integrate a single nitrogen-vacancy (NV) center in diamond with scanning probe microscopy to detect, read out, and spatially map spin-based quantum sensors at the nanoscale. Using the boron vacancy ($V$$^{–}_{B}$) center in hexagonal boron nitride—an emerging two-dimensional spin system—as a model, we detect its electron spin resonance indirectly via changes in the spin relaxation time (T 1 ) of a nearby NV center, eliminating the need for optical excitation or fluorescence detection of the $V$$^{–}_{B}$. Cross-relaxation between NV and $V$$^{–}_{B}$ ensembles significantly reduces NV T1, enabling quantitative nanoscale mapping of defect densities beyond the optical diffraction limit and clear resolution of hyperfine splitting in isotopically enriched h 10 B 15 N. Our method demonstrates interactions between spin sensors in 3D and 2D materials, establishing NV centers as versatile probes for characterizing otherwise inaccessible spin defects.

Quantum metrology↗
DOE OSTI2025

SULI Deliverables Using: Python-B1500 [Slides]

A new electrical setup for testing ECRAM devices is described in this presentation. This presentation details the background of ECRAM devices, how the B1500 is used to program ECRAM devices, and the python GUI that was created for controlling the B1500. ECRAM devices are a form of non-volatile memory. The stored data is the resistance between two of the terminals on the device. Using only the B1500, the ECRAM devices can be programmed and the state read out. This creates a simple, logical testing setup. The overall setup was successful, ECRAM devices could easily be programmed and measured. However, there is still room for improvement. Specifically, in the creation of an automated “Program” feature and a “Data Collection” feature. These features will require additional advances in the understanding of ECRAM devices but will greatly automate and improve the current data collection and application of ECRAM devices.

42 ENGINEERING↗
NASA NTRS1985

Six micrometer period wide-gap permalloy magnetic bubble devices

This report describes the progress made toward the goal of developing a 1 Mbit bubble memory chip, based on a 6 micron period wide-gap permalloy technology. Characterization of the functions showed that the guard-rail, generator, swap, write-line, read-line and after several revisions, the replicator and the expander-detector performed acceptably in preliminary testing. Several investigations were initiated to solve the problem of low minor loop yield. A dual-spacing process, which allows the minor loop propagation elements to be more tightly coupled to the garnet film was developed. Several new propagate structures, intended to be more tolerant of small defects were also conceived.

Chirovsky, L. M. F.↗
NASA NTRS1984

The role of knowledge structures in fault diagnosis

The use of human memory and knowledge structures to direct fault diagnosis performance was investigated. The performances of 20 pilots with instrument flight ratings were studied in a fault diagnosis task. The pilots were read a scenario which described flight conditions under which the symptoms which are indicative of a problem were detected. They were asked to think out loud as they requested and interpreted various pieces of information to diagnose the cause of the problem. Only 11 of the 20 pilots successfully diagnosed the problem. Pilot performance on this fault diagnosis task was modeled in the use of domain specific knowledge organized in a frame system. Eighteen frames, with a common structure, were necessary to account for the data from all twenty subjects.

Smith, P. J.↗
NASA NTRS2003

TID, SEE and radiation induced failures in advanced flash memories

We report on TID and SEE tests of multi-level and higher density flash memories. Stand-by currents and functionality tests were used to characterize the response of radiation-induced failures. The radiation-induced failures can be categorized as followings: SEU read errors during irradiation, stuck-bit read errors verified post-irradiation, write errors, erase failures, multiple upsets, and single-event latch up.

Scheick, Leif Z.↗
DOE OSTI2022

Access Patterns and Performance Behaviors of Multi-layer Supercomputer I/O Subsystems under Production Load

Scientific computing workloads at HPC facilities have been shifting from traditional numerical simulations to AI/ML applications for training and inference while processing and producing ever-increasing amounts of scientific data. To address the growing need for increased storage capacity, lower access latency, and higher bandwidth, emerging technologies such as non-volatile memory are integrated into supercomputer I/O subsystems. With these emerging trends, we need a better understanding of the multilayer supercomputer I/O systems and ways to use these subsystems efficiently. In this work, we study the I/O access patterns and performance characteristics of two representative supercomputer I/O subsystems. Through an extensive analysis of year-long I/O logs on each system, we report new observations in I/O reads and writes, unbalanced use of storage system layers, and new trends in user behaviors at the HPC I/O middleware stack.

Bez, JL↗
NASA NTRS1988

File-Format Program For Transferable Output ASCII Data

TOAD utilities machine-independent and require minimal central memory. Transferable Output ASCII Data (TOAD) file-format computer program facilitates transfer of data files from one computer installation to another. TOAD files preferred type and record length, easy to edit, read, and write on magnetic tape or transfer across communications networks. Applications programs write TOAD files directly and conform to all ANSI FORTRAN 77 standards.

Bingle, Bradford↗
DOE OSTI2021

Design Space Exploration of Ferroelectric Tunnel Junction Toward Crossbar Memories

We perform a simulation-based analysis on the potential of emerging ferroelectric tunnel junctions (FTJs) as a memory device for crossbar arrays. Though FTJs are promising due to their low power switching characteristics compared to other emerging technologies, the greatest challenge for FTJs is the tradeoff between integration density and read performance. Our analysis highlights the need to co-optimize the ferroelectric thickness of the FTJ and read/write voltages to achieve proper functionality at large array sizes. Our analysis shows that FTJ-based crossbar achieves 93% higher sense margin at isoread power of 116 nW (per bit), but this FTJ design comes at a cost of 9.28× higher write power at isowrite time of 250 ns. In response, we study the potential tradeoffs of design points outside the feasible region to understand what device characteristics are desired to overcome such challenges.

Jao, Nicholas↗
NASA NTRS2004

Four-Channel PC/104 MIL-STD-1553 Circuit Board

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

Cox, Gary L.↗
DOE OSTI2025

The ETROC2 as the Final Version for CMS Endcap Timing Layer (ETL) Upgrade

The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD (Low Gain Avalanche Diodes) silicon devices, read out by ETROCs for precision timing measurement with down to ~30 ps timing resolution per track. The ETROC is designed to handle a 16 x 16 pixel cell matrix, with each pixel being 1.3 mm x 1.3 mm to match the LGAD sensor pixel size. The front-end design for preamplifier and discriminator has been specifically optimized for the reduced LGAD signals, with enough flexibilities to meet the ETL specific needs for time resolution, power budget and radiation profile. The ETROC chip is implemented in a commercial 65nm CMOS process. Each channel consists of a preamplifier, a discriminator, a TDC used for TOA (Time Of Arrival) and TOT (Time Over Threshold) measurements, and a memory for data storage and readout. An in-pixel auto threshold calibration is included, along with a self-testing pattern generator. The TOT is used for time-walk correction of the TOA measurement. The detailed hit information (TOA and TOT) from each cell will be read out from a local circular buffer after each Level-1 Accept (about 1 MHz). In addition, a charge injection circuit is implemented to allow for testing and calibration. For more detailed monitoring of the signal pulses, waveform sampling circuits are included for one pixel. The clock distribution is based on a 16x16 H-tree design with a shielding structure to alleviate potential interference. The global peripheral circuits include a PLL, a phase shifter, an I2C slave controller, a fast control block, a global readout, and a data driver along with an efuse and temperature sensor. The ETROC builds event data frames for each L1A selected event and is also capable of providing L1 trigger information for user-defined delayed hits. The main design challenge is how to extract precision timing information from the small LGAD signals in the presence of high irradiation fluence, while keeping the power consumption and digital activity low. The ETL design goal for the time resolution of 50 ps per hit is required to achieve a 35 ps arrival time measurement for a MIP particle, which has its track registered in two ETL disk layers. The LGAD contribution is known to be about 30 ps, this means that the jitter from the ETROC has to be kept below 40 ps. The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL and now becomes the final version. The ETROC2 chips have been extensively tested. We will present here new testing results including the bump bonding yield improvement study, the time walk correction (TWC) generality study with one pixel TWC applying to all pixels, the final SEU testing using both heavy ion and proton beam, more beam test studies including different sensors, and readiness for the ETROC2 production for CMS ETL upgrade.

Liu, Tiehui [Fermilab] (ORCID:0009000765225605)↗
DOE OSTI2020

Battery Monitoring System

The component that is powered by the battery pack being monitored is a valuable asset and must be in working condition at all times. Battery chemistry and characteristics have a major role in how to evaluate the state of the battery. The battery monitoring system has many parts that lead to an accurate battery reading. The components consist of a coulomb counting device, end of life voltage detection, a consideration of use for a real-time clock (RTC), temperature sensor, and non-volatile random-access memory (NVRAM). The combination of these elements allows the monitoring system to be highly reliant. Moving forward a better implementation of the ideas in this paper and further testing should ensure a high-quality battery monitoring system.

25 ENERGY STORAGE↗
NASA NTRS1988

Programmable Synaptic Arrays For Electronic Neural Networks

High resistances prevent hotspots in parallel input and output operation. Nonvolatile computer memory combines ultrahigh storage density with extremely-low power dissipation. Accommodates about 1 billion bits in square centimeter of surface area. Bit written with expenditure of less than 1 nanojoule of energy and read with even lower energy. Developed for parallel input and output operation.

Thakoor, Anilkumar P.↗
NASA NTRS2011

Experiment in Onboard Synthetic Aperture Radar Data Processing

Single event upsets (SEUs) are a threat to any computing system running on hardware that has not been physically radiation hardened. In addition to mandating the use of performance-limited, hardened heritage equipment, prior techniques for dealing with the SEU problem often involved hardware-based error detection and correction (EDAC). With limited computing resources, software- based EDAC, or any more elaborate recovery methods, were often not feasible. Synthetic aperture radars (SARs), when operated in the space environment, are interesting due to their relevance to NASAs objectives, but problematic in the sense of producing prodigious amounts of raw data. Prior implementations of the SAR data processing algorithm have been too slow, too computationally intensive, and require too much application memory for onboard execution to be a realistic option when using the type of heritage processing technology described above. This standard C-language implementation of SAR data processing is distributed over many cores of a Tilera Multicore Processor, and employs novel Radiation Hardening by Software (RHBS) techniques designed to protect the component processes (one per core) and their shared application memory from the sort of SEUs expected in the space environment. The source code includes calls to Tilera APIs, and a specialized Tilera compiler is required to produce a Tilera executable. The compiled application reads input data describing the position and orientation of a radar platform, as well as its radar-burst data, over time and writes out processed data in a form that is useful for analysis of the radar observations.

Holland, Matthew↗
NASA NTRS1985

Dynamic-RAM Data Storage Unit

Dynamic random-access-memory (RAM) data delay and storage unit developed to insure data received from satellite is stored and not lost when satellite is not within range of ground station. Stores 256K of serial data, with independent read and write capability.

Sturman, J. C.↗