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Proton irradiation tests were performed on the Actel CKJ911 prototype Field Programmable Gate Array (FPGA) at the Indian University Cyclotron facility. The devices, tests, and results are discussed.
The rapid growth of SmallSat and CubeSat missions at NASA has necessitated a re-evaluation of communication and remote-sensing architectures. Novel designs for CubeSat-sized single-board computers can now include larger Field-Programmable Gate Arrays (FPGAs) and faster System-on-Chip (SoCs) devices. These components substantially improve onboard processing capabilities so that varying subsystems no longer require an independent processor. By replacing individual Radio Frequency (RF) systems with a single software-defined radio (SDR) and processor, mission designers have greater control over reliability, performance, and efficiency. The presented architecture combines individual processing systems into a single design and establishes a modular SDR architecture capable of both remote-sensing and communication applications. This new approach based on a multi-input multi-output (MIMO) SDR features a scalable architecture optimized for Size, Weight, Power, and Cost (SWaP-C), with sufficient noise performance and phase-coherence to enable both remote-sensing and navigation applications, while providing a communication solution for simultaneous S-band and X-band transmission. This SDR design is developed around the NASA CubeSat Card Standard (CS2) that provides the required modularity through simplified backplane and interchangeable options for multiple radiation-hardened/tolerant processors. This architecture provides missions with a single platform for high-rate communication and a future platform to develop cognitive radio systems.
This paper presents work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuits (ASIC). FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. The developed interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry.
PARC, a Xerox Company, is developing a low-cost system of peel-and-stick wireless sensors that will enable widespread building environment sensor deployment with the potential to deliver up to 30% energy savings. The system is embodied by a set of RF hubs that provide power to automatically located sensor nodes, and relay data wirelessly to the building management system (BMS). The sensor nodes are flexible electronic labels powered by rectified RF energy transmitted by an RF hub and can contain multiple printed and conventional sensors. The system design overcomes limitations in wireless sensors related to power delivery, lifetime, and cost by eliminating batteries and photovoltaic devices. Sensor localization is performed automatically by the inclusion of a programmable multidirectional antenna array in the RF hub. Comparison of signal strengths while the RF beam is swept allows for sensor localization, reducing installation effort and enabling automatic recommissioning of sensors that have been relocated, overcoming a significant challenge in building operations. PARC has already demonstrated wireless power and temperature data transmission up to a distance of 20m with less than one minute between measurements, using power levels well within the FCC regulation limits in the 902-928 MHz ISM band. The sensor’s RF energy harvesting antenna achieves high performance with dimensions below 5cm x 9cm.
Computation in biological neural circuits arises from the interplay of nonlinear temporal responses and spatially distributed dynamic network interactions. Replicating this richness in hardware has remained challenging, as most neuromorphic devices emulate only isolated neuron- or synapse-like functions. Here we introduce an integrated neuromorphic computing platform in which both nonlinear spatiotemporal processing and programmable memory are realized within a single perovskite nickelate material system. By engineering symmetric and asymmetric hydrogenated NdNiO 3 junction devices on the same wafer, we combine ultrafast, proton-mediated transient dynamics with stable multilevel resistance states. Networks of symmetric NdNiO 3 junctions exhibit emergent spatial interactions mediated by proton redistribution, while each node simultaneously provides short-term temporal memory, enabling nanosecond-scale operation with an energy cost of ~0.2 nJ per input. When interfaced with asymmetric output units serving as reconfigurable long-term weights, these networks allow both feature transformation and linear classification in the same material system. Leveraging these emergent interactions, the platform enables real-time pattern recognition and achieves high accuracy in spoken digit classification and early seizure detection, outperforming temporal-only or uncoupled architectures. These results position protonic nickelates as a compact, energy-efficient, CMOS-compatible platform that integrates processing and memory for scalable intelligent hardware.
Analysis of electrical noise in vanadium oxide electrochemical random access memory devices and its potential for application in a Bayesian neural network
Irreparable chemical damage to redox-active monomers, oligomers, and polymers (i.e. redoxmers) limits the lifetime of energy storage devices (e.g. redox flow batteries) by causing electrode and membrane fouling, as well as irreversible capacity loss. To predictably restore device and materials performance, it is desirable to add programmed destruction capabilities into these damage-prone materials. Here, we report the use of triggerable retrograde reactions to achieve programmable end-of-life function in redoxmers. Retrograde reactions are intended to break up damaged redoxmer materials into more soluble small-molecule constituents to prevent irreparably fouling battery interfaces. We investigated the redox-triggered mesolytic cleavage of homobenzylic ethers (HBEs) for this purpose. Combining experimental methods with simulations, we probed the influence of ring substituents on the programmable bond-scission behavior of HBEs. Variation of para-substituents on the HBEs allowed us to modify the oxidation potential, degradation pathway, and electrochemical mechanisms of the generated products. Given its ideal oxidation potential, we selected the para-methoxy-based HBE as the cleavage scaffold and integrated it with dialkoxybenzene, TEMPO, viologen, and para-nitrobenzene redox centers for compatibility, bulk deconstruction, and electrode defouling tests. Upon applying a high oxidation potential, the redox-active pendant is cleaved from the backbone via HBE bonds; of the four redox centers tested, three of them remained fully redox active. Viologen-appended redox active polymers with HBE linkers were cleaved to fully separate the redox centers from the backbone. Polymer-filmed electrodes were partially restored following HBE oxidation defouling. Here these studies highlight the co-design of new materials functions for developing sustainable energy storage materials.
The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing, mitigation evaluation (embedded and user-implemented), unreliable design and its affects to SEE Data, testing flushable architectures versus non-flushable architectures, intellectual property core (IP Core) test and evaluation (addresses embedded and user-inserted), heavy-ion energy and linear energy transfer (LET) selection, proton versus heavy-ion testing, fault injection, mean fluence to failure analysis, and mission specific system-level single event upset (SEU) response prediction. Most sections within the guidelines manual provide information regarding best practices for test structure and test system development. The scope of this manual addresses academic versus mission specific device evaluation and visibility enhancement in IP Core testing.
Simulation of radar returns, full-duplex systems, and signal repeaters require hundreds of ns of programmable broadband radio frequency (RF) delay in the signal path to simulate large distances in the case of radar returns, for signal cancellation in full-duplex, and for isolation from reflections in signal repeaters. However, programmable broadband RF delay has been limited to ones of ns due to challenges in miniaturization with low loss and low power consumption. In this work, we present a 0.2–2 GHz digitally programmable RF delay element based on a time-interleaved multistage switched-capacitor (TIMS-SC) approach. The proposed approach enables hundreds of ns of broadband RF delay by employing sample time expansion in multiple stages of switched-capacitor storage elements. Further, the delay element was implemented in a 45 nm SOI CMOS process and achieves a 2.55–448.6 ns programmable delay range with < 0.12% delay variation across 1.8 GHz of bandwidth at maximum delay, 2.42 ns programmable delay steps, and 330 ns/mm 2 area efficiency. Through the proposed approach, the device shows minimal delay change across a -40 °C to 85 °C temperature range and < 0.25 dB gain variation across delay settings. The device achieves 26 dB gain, 7.4 dB noise figure, and consumes 74 mW from a 1 V supply with an active area of 1.36 mm 2 .
A method for bandwidth-efficient processing of video imagery to be viewed by the teleoperator of a remotely-operated vehicle on which the camera is mounted is described. The method comprises image coding, transmission, and reconstruction. It is assumed that the transmission bandpass is the limiting factor rather than encoding/decoding schemata; that image coding and reconstruction will be done within the general abilities of the NASA/TI Programmable Remapper; and that the ratio of retained local detail to the operator's visual resolution is held constant throughout the large-field image that is seen. Novel features include that the compression and reconstruction address certain characteristics of the human visual system, that two-way communication controls a moving 'fovea' in the transformation, and that resolution varies over the image. Conventional motivations accommodated include the Cartesian raster-scan nature of available imagers and display devices and a need for low bandwidth in the image transmission. Unique image processing hardware, NASA's Programmable Remapper, allows demonstration of the method. Once refined, the technology could be adapted to special purpose imagers and display devices, or otherwise to dedicated image processing hardware.
Low-current multilevel programmability with inherent non-volatility and high stability of resistance states is required for both multi-bit memory storage and deep learning accelerators but is difficult to achieve. Here, in a resistive switching system, this work realizes >512 (>9 bits) distinct non-volatile conductance levels with stable retention for each state with current levels down to the nanoampere range, highly promising for potential integration with small processing nodes with ultra-low power consumption requirements. This is achieved by demonstrating a new thin film design concept that encompasses three key features: an ultra-thin epitaxial oxygen ionic switching layer that provides a tunable energy barrier at the bottom electrode, an overcoat amorphous layer that acts as an ion migration barrier for stable state retention, and a partial conductive filament as a localized electronic transport channel to the epitaxial switching layer. A large dynamic resistance range of up to seven orders of magnitude is achieved with reset-free transitions among intermediate states, and programmability is demonstrated with ultra-fast (20 ns) pulses. Artificial neural network (ANN) simulations, based on the experimental performance and its non-idealities, demonstrate close-to-ideal inference accuracies for various Modified National Institute of Standards and Technology (MNIST) data sets.
An acoustically coupled frequency selective radio frequency (RF) device is provided. The device includes a piezoelectric substrate overlain by a plurality of electrodes. The device further includes a pair of RF input terminals at least one of which is electrically connected to at least one of the electrodes, and a pair of output RF terminals, at least one of which is electrically connected to at least one other of the electrodes. At least one of the electrodes is electromechanically reconfigurable between a state in which it is closer to a face of the piezoelectric substrate and at least one state in which it is farther from the face of the piezoelectric substrate.
A primary science goal of the 6.5 m James Webb Space Telescope is to characterize the epoch of initial galaxy formation, observing the early universe as the first stars and galaxies formed. This program will be accomplished using a combination of multi-band imaging and spectroscopic measurements of large numbers of faint galaxies. Since these objects are in general sparse on the sky, a multi object spectrometer is required to enable this critical scientific investigation. We have developed a microshutter array which is to be used as a high contrast, remotely programmable field selector for the Near Infrared Spectrometer (NIRSpec) on JWST. This device allows slits to be opened at the locations of selected galaxies in the field of view, and blocks sources and background light from the rest of the field. The first flight design devices have been built and were tested. These first generation of devices were used to demonstrate performance and flight readiness. Devices of the same design will be delivered to ESA for installation into the NIRSpec instrument.
The James Webb Space Telescope, scheduled to replace the Hubble in 2013, must simultaneously observe hundreds of faint galaxies. This requirement has led to the development of a programmable transmission mask which can be adapted to admit light with arbitrary pattern of galaxies into its spectrograph. This programmable mask will contain a large array of micro-electromechanical (MEMs) devices called MicroShutters. These microscopic shutters physically open and close like the shutter on a camera, except each shutter is microscopic in size and an array 365 by 171 is used to select the objects under spectroscopic observation at a given time, and to block the unwanted background light from other areas. NASA developed and is currently refining the exceptionally difficult process of manufacturing these shutters. This paper describes how the authors used LabVIEW FPGA and a reconfigurable I/O board to control the shutters in a test chamber and how the flexibility of the system allows us to continue to modify the control algorithms as NASA optimizes the performance of the MicroShutter arrays.
The James Webb Space Telescope, scheduled to replace the Hubble in 2013, must simultaneously observe hundreds of faint galaxies. This requirement has led to the development of a programmable transmission mask which can be adapted to admit light from an arbitrary pattern of galaxies into its spectrograph. This programmable mask will contain a large array of micro-electromechanical (MEMs) devices called MicroShutters. These microscopic shutters physically open and close like the shutter on a camera, except each shutter is microscopic in size and an array 365 by 171 is used to select the objects under spectroscopic observation at a given time, and to block the unwanted background light from other areas. NASA developed and is currently refining the exceptionally difficult process of manufacturing these shutters. This paper describes how the authors used LabVIEW FPGA and a reconfigurable I/O board to control the shutters in a test chamber and how the flexibility of the system allows us to continue to modify the control algorithms as NASA optimizes the performance of the MicroShutter arrays.
Due to requirements for reduced size and weight, use of grid array packages in space applications has become common place. To meet the requirement of high reliability and high number of I/Os, ceramic column grid array packages (CCGA) were selected for major electronic components used in next MARS Rover mission (specifically high density Field Programmable Gate Arrays). ABSTRACT The probability of removal and replacement of these devices on the actual flight printed wiring board assemblies is deemed to be very high because of last minute discoveries in final test which will dictate changes in the firmware. The questions and challenges presented to the manufacturing organizations engaged in the production of high reliability electronic assemblies are, Is the reliability of the PWBA adversely affected by rework (removal and replacement) of the CGA package? and How many times can we rework the same board without destroying a pad or degrading the lifetime of the assembly? To answer these questions, the most complex printed wiring board assembly used by the project was chosen to be used as the test vehicle, the PWB was modified to provide a daisy chain pattern, and a number of bare PWB s were acquired to this modified design. Non-functional 624 pin CGA packages with internal daisy chained matching the pattern on the PWB were procured. The combination of the modified PWB and the daisy chained packages enables continuity measurements of every soldered contact during subsequent testing and thermal cycling. Several test vehicles boards were assembled, reworked and then thermal cycled to assess the reliability of the solder joints and board material including pads and traces near the CGA. The details of rework process and results of thermal cycling are presented in this paper.
A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redundancy mode, the programmable functional elements are identical and are programmed identically so the voters produce an output corresponding to the majority of inputs that agree. In a split mode, each voter selects a particular programmable functional element output as the output of the voter. Therefore, in the split mode, the programmable functional elements can perform different functions, operate independently, and/or be connected together to process different parts of the same problem.
This paper presents our work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuit (ASIC) applications. FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. Our interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry. Our Interposer focuses on the needs of Micro Semi’s RTG4 FPGA. We developed the interposer using COTS embedded foil capacitors. The Interposer is customized to the capacitance requirements for each of the FPGA banks. We evaluated three foil manufactures Oak Mitsui, 3M and TDK. The three different designs were evaluated, but we will focus on the Oak-Mitsui based Interposer that we constructed and tested. Through simulations, we validate the horizontal and vertical interconnect inductances, that FPGA decoupling requirements are met. The use of the interposer results in an overall reduction in our Printed Wiring Board (PWB) area.