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Results for “PROCESSOR”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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A REVIEW OF TRIGGER AND ONLINE PROCESSORS AT SLAC
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THE SLAC SCANNER PROCESSOR: A FASTBUS MODULE FOR DATA COLLECTION AND PROCESSING
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The 3081/E Processor and Its On-Line Use
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THE 3081/E EMULATOR: A PROCESSOR FOR USE IN ONLINE AND OFFLINE ARRAYS
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SLAC SCANNER PROCESSOR APPLICATIONS IN THE DATA ACQUISITION SYSTEM FOR THE UPGRADED MARK-II DETECTOR
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ANALYZING GIGAHERTZ BUNCH LENGTH INSTABILITIES WITH A DIGITAL SIGNAL PROCESSOR
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A Longitudinal Multibunch Feedback System Using Parallel Digital Signal Processors
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Automatic Waveguide Processor
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Instruction Manual for Proportional Wire Chamber Memory Processor (SLAC 135-078)
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Double Buffering for MCDRAM on Second Generation Intel Xeon Phi Processors with OpenMP.
Abstract not provided.
Performance on Trinity Phase 2 (a Cray XC40 utilizing Intel Xeon Phi processors) with Acceptance-Applications and Benchmarks.
Abstract not provided.
Performance tuning to close Ninja gap for Accelerator Physics Emulation System (APES) on Intel Xeon Phi processors
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Performance on Trinity Phase 2 (a Cray XC40 utilizing Intel Xeon Phi processors) with Acceptance Applications and Benchmarks.
Abstract not provided.
Double Buffering for MCDRAM on Second Generation Intel Xeon Phi Processors with OpenMP.
Abstract not provided.
Towards Scalable Characterization of Noisy Intermediate-Scale Quantum Information Processors.
Abstract not provided.
Ultra-low power processor-in-memory architecture
An apparatus including a memory array comprising a plurality of rows and a plurality of columns. A switch electrically connects to a particular row of the plurality of rows of the memory array per cycle. An energy storage unit is electrically connected to the memory array through the switch, wherein the energy storage unit is electrically connected in a series with an effective capacitance between ground and the particular row of the plurality of rows of the memory array to which the switch is connected to recycle energy from the memory array.