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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 307 records · Page 17
All sourcesNASA NTRSDOE OSTI
NASA NTRS1993

Behavioral model simulation studies of an image compressor

The high initial cost of prototype Very Large Scaled Integrated (VLSI) parts requires that sufficient verifications be made to eliminate design errors before actually producing the prototypes. Logic simulation is the means by which the VLSI engineer can ensure that the design will function properly. The computer time required for logic simulation can be reduced through the use of behavioral models. Behavioral models, however, require time to write and verify and they do not always produce a dramatic speed up in logic simulation time. This paper presents a study of behavioral modeling aimed at discovering which circuit types benefit most from the use of behavioral models for logic simulation.

Madani, Navid↗
NASA NTRS1988

Noise-margin limitations on gallium-arsenide VLSI

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

Long, Stephen I.↗
NASA NTRS1991

A verification logic representation of indeterministic signal states

The integration of modern CAD tools with formal verification environments require translation from hardware description language to verification logic. A signal representation including both unknown state and a degree of strength indeterminacy is essential for the correct modeling of many VLSI circuit designs. A higher-order logic theory of indeterministic logic signals is presented.

Gambles, J. W.↗
NASA NTRS1997

Fundamental Hardware Design in PVS

The development of Programmable Logic Devices (PLDs) has introduced programming as a primary tool in the development of digital circuits. This work attempts to create a generic verification environment in which designs can be specified and verified using the Prototype Verification System (PVS). This is accomplished by providing library support for general hardware constructs. The environment is intended for use with any PLD and any PLD programming language. The goal of the environment is to allow the easy translation of digital designs to PVS and provide sufficient support to make verification possible without a great deal of effort.

Leathrum, James F., Jr.↗
NASA NTRS1974

Investigation of rank 2 and higher output feedback for pole placement

A common feature of several pole placement techniques is discussed and the use of a dyadic feedback matrix is presented. The limitation of this design is examined and a design involving output feedback matrices of Rank greater than one is developed as a logical extension of the dyadic feedback design. An example is presented to illustrate the design procedure.

Sridhar, B.↗
NASA NTRS1990

A fail-safe CMOS logic gate

This paper reports a design technique to make Complex CMOS Gates fail-safe for a class of faults. Two classes of faults are defined. The fail-safe design presented has limited fault-tolerance capability. Multiple faults are also covered.

Bobin, V.↗
NASA NTRS1987

A VLSI architecture of a binary updown counter

A pipeline binary updown counter with many bits is developed which can be used in a variety of applications. One such application includes the design of a digital correlator for very long baseline interferometry (VLBI). The advantage of the presently conceived approach over the previous techniques is that the number of logic operations involved in the design of the binary updown counter can be reduced substantially. The architecture design using these methods is regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

Reed, I. S.↗
NASA NTRS1994

Fuzzy self-learning control for magnetic servo system

It is known that an effective control system is the key condition for successful implementation of high-performance magnetic servo systems. Major issues to design such control systems are nonlinearity; unmodeled dynamics, such as secondary effects for copper resistance, stray fields, and saturation; and that disturbance rejection for the load effect reacts directly on the servo system without transmission elements. One typical approach to design control systems under these conditions is a special type of nonlinear feedback called gain scheduling. It accommodates linear regulators whose parameters are changed as a function of operating conditions in a preprogrammed way. In this paper, an on-line learning fuzzy control strategy is proposed. To inherit the wealth of linear control design, the relations between linear feedback and fuzzy logic controllers have been established. The exercise of engineering axioms of linear control design is thus transformed into tuning of appropriate fuzzy parameters. Furthermore, fuzzy logic control brings the domain of candidate control laws from linear into nonlinear, and brings new prospects into design of the local controllers. On the other hand, a self-learning scheme is utilized to automatically tune the fuzzy rule base. It is based on network learning infrastructure; statistical approximation to assign credit; animal learning method to update the reinforcement map with a fast learning rate; and temporal difference predictive scheme to optimize the control laws. Different from supervised and statistical unsupervised learning schemes, the proposed method learns on-line from past experience and information from the process and forms a rule base of an FLC system from randomly assigned initial control rules.

Tarn, J. H.↗
NASA NTRS2001

An introduction to the Gilgamesh PIM architecture

The focus of the work conducted is on a class of structures made possible by the merger of logic and memory. Processing In Memory (PIM) extends the design space much farther by closely associating the logic with the memory interface to realize innovative structures never previously possible and thus exposing entirely new opportunities for computer architecture.

Gilgamesh PIM CMOS↗
NASA NTRS1991

Phase-lock-loop application for fiber optic receiver

Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.

Ruggles, Stephen L.↗
NASA NTRS1973

On the Design and Test of a Liquid Injection Electric Thruster

A liquid injection electric thruster (LINJET) was designed and tested. The results of the tests were very encouraging with thruster performance levels well in excess of design goals. Supporting activities to the engine design and test included a five-million pulse life test on the main capacitor, a 46-million pulse test on the trigger electronics, design and fabrication of a zero resistance torque connector for use with the torsional pendulum thrust stand, design and fabrication of a logic box for control of engine firing, and a physical and chemical properties characterization of the perfluorocarbon propellant. While the results were encouraging, testing was limited, as many problems existed with the design. The most significant problem was involved with excessive propellant flow which contributed to false triggering and shorting. Low power active thermal control of the propellant storage cavity, coupled with a re-evaluation of the injection ring pore size and area exposed to the main capacitor discharge are areas that should be investigated should this design be carried forward.

Jones, T. A.↗
NASA NTRS1981

Architecture for VLSI design of Reed-Solomon encoders

The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

Liu, K. Y.↗
NASA NTRS1981

A high capacity satellite switched TDMA microwave switch matrix

A description is given of the conceptual design of a high-capacity satellite switched-time division multiple access (SS-TDMA) microwave switch matrix fabricated with GaAs monolithic microwave integrated circuits (MMICs), including integration of both microwave and control logic circuits into the monolithic design. The technology required for a 30/20 GHz communications system includes an on-board SS-TDMA switch matrix. A conceptual design study that has been completed for a wideband, high-capacity (typically 100 x 100) channel switch matrix using technology anticipated for 1987 is described, noting that the study resulted in a switch matrix design concept using a coupled crossbar architecture implemented with MMIC. The design involves basic building block MMIC, permitting flexible growth and efficient wraparound redundancy to increase reliability.

Cory, B. J.↗
NASA NTRS1988

Fault diagnosis in orbital refueling operations

Usually, operation manuals are provided for helping astronauts during space operations. These manuals include normal and malfunction procedures. Transferring operation manual knowledge into a computerized form is not a trivial task. This knowledge is generally written by designers or operation engineers and is often quite different from the user logic. The latter is usually a compiled version of the former. Experiments are in progress to assess the user logic. HORSES (Human - Orbital Refueling System - Expert System) is an attempt to include both of these logics in the same tool. It is designed to assist astronauts during monitoring and diagnosis tasks. Basically, HORSES includes a situation recognition level coupled to an analytical diagnoser, and a meta-level working on both of the previous levels. HORSES is a good tool for modeling task models and is also more broadly useful for knowledge design. The presentation is represented by abstract and overhead visuals only.

Boy, Guy A.↗
NASA NTRSDate not supplied

Design Analysis for Lunar Safe Haven Concepts

NASA’s plan to return humans to the lunar surface faces many challenges, especially in the sustained phases of the Artemis program. In combination with a habitat, a Lunar Safe Haven (LSH) would provide additional protection to crew, electronics, and equipment from the hazards of the space environment such as radiation, thermal extremes, micrometeoroids, and lunar dust. Influenced by the NASA Artemis program goals, the Lunar Safe Haven Study defined the high-level requirements, outlined the trade space for a LSH concept, and evaluated a set of concepts using a decision analysis structure. This paper will provide additional detail for two concepts that were designed and evaluated during the LSH study, the logic behind the choices, and some of the main driving design parameters.

lunar↗
NASA NTRS1993

Development of Miniaturized Optimized Smart Sensors (MOSS) for space plasmas

The cost of space plasma sensors is high for several reasons: (1) Most are one-of-a-kind and state-of-the-art, (2) the cost of launch to orbit is high, (3) ruggedness and reliability requirements lead to costly development and test programs, and (4) overhead is added by overly elaborate or generalized spacecraft interface requirements. Possible approaches to reducing costs include development of small 'sensors' (defined as including all necessary optics, detectors, and related electronics) that will ultimately lead to cheaper missions by reducing (2), improving (3), and, through work with spacecraft designers, reducing (4). Despite this logical approach, there is no guarantee that smaller sensors are necessarily either better or cheaper. We have previously advocated applying analytical 'quality factors' to plasma sensors (and spacecraft) and have begun to develop miniaturized particle optical systems by applying quantitative optimization criteria. We are currently designing a Miniaturized Optimized Smart Sensor (MOSS) in which miniaturized electronics (e.g., employing new power supply topology and extensive us of gate arrays and hybrid circuits) are fully integrated with newly developed particle optics to give significant savings in volume and mass. The goal of the SwRI MOSS program is development of a fully self-contained and functional plasma sensor weighing 1 lb and requiring 1 W. MOSS will require only a typical spacecraft DC power source (e.g., 30 V) and command/data interfaces in order to be fully functional, and will provide measurement capabilities comparable in most ways to current sensors.

Young, D. T.↗