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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 307 records · Page 17
All sourcesNASA NTRSDOE OSTI
NASA NTRS1977

A four digit memory-mapped display

A circuit for interfacing the JOLT (TM) microprocessor to four digital displays was designed and fabricated. Circuit operation and test program are described and presented in detail.

Smith, R. E.↗
NASA NTRS1994

Monolithic Optical-To-Electronic Receiver

Monolithic optoelectronic integrated circuit converts multiplexed digital optical signals into electrical signals, separates, and distributes them to intended destinations. Developed to deliver phase and amplitude commands to monolithic microwave integrated circuits (MMIC's) at elements of millimeter-wave phased-array antenna from single optical fiber driven by external array controller. Also used in distribution of high-data-rate optical communications in local-area networks (LAN's). Notable features include options for optical or electrical clock inputs; outputs for raw data, addresses, and instructions for diagnosis; and optical-signal-detection circuit used to reduce power consumption by 80 percent between data-transmission times. Chip fabricated by processes available at many major semiconductor foundries. Distribution of digital signals in aircraft, automobiles, and ships potential application.

Kunath, Richard↗
DOE OSTI2024

Data-Driven Digital Twin for Reliability Assessment of DC/DC Buck Converter

In commercial applications, the operation of DC/DC converters significantly impacts overall system performance and long-term reliability. This study introduces a data-driven digital twin (DT) approach for estimating critical degradation parameters of DC/DC BUCK converter under steady-state condition. Initially, a circuit-level MATLAB/Simulink digital model (DM C ) is refined against a hardware prototype’s switching model dataset using offline particle swarm optimization. The optimized digital model’s steady-state response is then verified with its average model response while varying the duty and load. Subsequently, degradation profiles are imposed on the inductor, capacitor, MOSFET in the DMC. A large dataset is generated from this model, allowing training, validation, and testing of machine learning (ML) models for component health regression tasks. The proposed method employs random forest ML models, achieving impressive regression results with a squared R value as high as 0.99978 and a root mean square error of 4.2× 10 –6 . The method is further validated on a medium power level DC/DC BUCK prototype with varying load conditions, and includes the analysis of MOSFET’s on-resistance under degradation conditions. This data-driven DT method shows promise for identifying parasitic degradation and ohmic loss parameters, enhancing converter reliability assessments in a non-invasive, generalized, and computationally efficient manner.

14 SOLAR ENERGY↗
NASA NTRS1988

Burst-Locked Oscillator Avoids Side Lock

Counting circuit corrects errors when side lock occurs. Digital error-detection-and-correction circuit in color-television oscillator circuit provides synchronization when color-burst frequency drifts outside normal tolerance. Digital side-lock-prevention circuit used in television color-burst phase-lock-loop oscillator provides greater tolerance of off-frequency signals than crystal-controlled oscillators.

Dischert, Robert A.↗
NASA NTRS1996

Analog current mode analog/digital converter

An improved subranging or comparator circuit is provided for an analog-to-digital converter. As a subranging circuit, the circuit produces a residual signal representing the difference between an analog input signal and an analog of a digital representation. This is achieved by subdividing the digital representation into two or more parts and subtracting from the analog input signal analogs of each of the individual digital portions. In another aspect of the present invention, the subranging circuit comprises two sets of differential input pairs in which the transconductance of one differential input pair is scaled relative to the transconductance of the other differential input pair. As a consequence, the same resistor string may be used for two different digital-to-analog converters of the subranging circuit.

Hadidi, Khayrollah↗
NASA NTRS1991

New dynamic FET logic and serial memory circuits for VLSI GaAs technology

The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.

Eldin, A. G.↗
NASA NTRS1972

Circuit performance of a parasitic-loading digital speed controller for a 400-hertz turbine-driven alternator

Parasitic speed controllers are used in space power electrical generating systems to maintain the speed of the turbine-driven alternators within specified limits. Selected subcircuits for a solid state parasitic-loading speed controller were assembled and tested. The test results as obtained to date consist of the performance evaluation of the frequency reference and the period counter subcircuits. These circuits performed as expected.

Ryan, J. P.↗
NASA NTRS1994

QPPM receiver for free-space laser communications

A prototype receiver developed at NASA Lewis Research Center for direct detection and demodulation of quaternary pulse position modulated (QPPM) optical carriers is described. The receiver enables dual-channel communications at 325-Megabits per second (Mbps) per channel. The optical components of the prototype receiver are briefly described. The electronic components, comprising the analog signal conditioning, slot clock recovery, matched filter and maximum likelihood data recovery circuits are described in more detail. A novel digital symbol clock recovery technique is presented as an alternative to conventional analog methods. Simulated link degradations including noise and pointing-error induced amplitude variations are applied. The bit-error-rate performance of the electronic portion of the prototype receiver under varying optical signal-to-noise power ratios is found to be within 1.5-dB of theory. Implementation of the receiver as a hybrid of analog and digital application specific integrated circuits is planned.

Budinger, J. M.↗
NASA NTRS2007

Calibration Test Set for a Phase-Comparison Digital Tracker

An apparatus that generates four signals at a frequency of 7.1 GHz having precisely controlled relative phases and equal amplitudes has been designed and built. This apparatus is intended mainly for use in computer-controlled automated calibration and testing of a phase-comparison digital tracker (PCDT) that measures the relative phases of replicas of the same X-band signal received by four antenna elements in an array. (The relative direction of incidence of the signal on the array is then computed from the relative phases.) The present apparatus can also be used to generate precisely phased signals for steering a beam transmitted from a phased antenna array. The apparatus (see figure) includes a 7.1-GHz signal generator, the output of which is fed to a four-way splitter. Each of the four splitter outputs is attenuated by 10 dB and fed as input to a vector modulator, wherein DC bias voltages are used to control the in-phase (I) and quadrature (Q) signal components. The bias voltages are generated by digital-to-analog- converter circuits on a control board that receives its digital control input from a computer running a LabVIEW program. The outputs of the vector modulators are further attenuated by 10 dB, then presented at high-grade radio-frequency connectors. The attenuation reduces the effects of changing mismatch and reflections. The apparatus was calibrated in a process in which the bias voltages were first stepped through all possible IQ settings. Then in a reverse interpolation performed by use of MATLAB software, a lookup table containing 3,600 IQ settings, representing equal amplitude and phase increments of 0.1 , was created for each vector modulator. During operation of the apparatus, these lookup tables are used in calibrating the PCDT.

Boas, Amy↗
NASA NTRS1994

Low-Power CMOS Digital Autocorrelator Spectrometer

Prototype digital autocorrelator spectrometer circuit designed and built as assembly of few very-large-scale integrated (VLSI) complementary metal oxide/semiconductor (CMOS) circuit chips. Spectrometer contains 128 frequency channels and operates at clock rate of as much as 40 MHz. Total dc power needed is only 6 W. Digital autocorrelator spectrometer consists of four 32-channel autocorrelator chips that collectively produce 128-point spectrum of input signal as computed by use of Fourier transform.

Chandra, Kumar M.↗
NASA NTRS1987

Parallel Analog-to-Digital Image Processor

Proposed integrated-circuit network of many identical units convert analog outputs of imaging arrays of x-ray or infrared detectors to digital outputs. Converter located near imaging detectors, within cryogenic detector package. Because converter output digital, lends itself well to multiplexing and to postprocessing for correction of gain and offset errors peculiar to each picture element and its sampling and conversion circuits. Analog-to-digital image processor is massively parallel system for processing data from array of photodetectors. System built as compact integrated circuit located near local plane. Buffer amplifier for each picture element has different offset.

Lokerson, D. C.↗
NASA NTRS1993

Circuit and method for producing a flexible reference voltage

A flexible reference voltage circuit includes a circuit for producing a first digital signal representative of a range of reference voltage levels; a circuit for producing a second digital signal representative of a selected reference voltage level within the range of reference voltage levels; an adder for adding the first and second digital signals to produce a third digital signal; and a digital to analog converter for providing an output voltage in response to the third digital signal. The method of producing a flexible reference voltage performed by the circuit is also claimed. The invention can be used with a differential protection circuit to provide a series of trip level ranges, with a series of selectable trip levels in each range. This is accomplished in a high accuracy circuit which is relatively simple to construct, thereby minimizing size and complexity of the current sensor module, in differential protection applications, or the circuitry, if used in a power system controller. Standard digital logic components can be used to perform the necessary range/level decoding.

Thornton, Roger D.↗
NASA NTRS1993

The NT digital micro tape recorder

The description of an audio recorder may at first glance seem out of place in a conference which has been dedicated to the discussion of the technology and requirements of mass data storage. However, there are several advanced features of the NT system which will be of interest to the mass storage technologist. Moreover, there are a sufficient number of data storage formats in current use which have evolved from their audio counterparts to recommend a close attention to major innovative introductions of audio storage formats. While the existing analog micro-cassette recorder has been (and will continue to be) adequate for various uses, there are significant benefits to be gained through the application of digital technology. The elimination of background tape hiss and the availability of two relatively wide band channels (for stereo recording), for example, would greatly enhance listenability and speech intelligibility. And with the use of advanced high-density recording and LSI circuit technologies, a digital micro recorder can realize unprecedented compactness with excellent energy efficiency. This is what was accomplished with the NT-1 Digital Micro Recorder. Its remarkably compact size contributes to its portability. The high-density NT format enables up to two hours of low-noise digital stereo recording on a cassette the size of a postage stamp. Its highly energy-efficient mechanical and electrical design results in low power consumption; the unit can be operated up to 7 hours (for continuous recording) on a single AA alkaline battery. Advanced user conveniences include a multifunction LCD readout. The unit's compactness and energy-efficiency, in particular, are attributes that cannot be matched by existing analog and digital audio formats. The size, performance, and features of the NT format are of benefit primarily to those who desire improved portability and audio quality in a personal memo product. The NT Recorder is the result of over ten years of intensive, multi-disciplinary research and development. What follows is a discussion of the technologies that have made the NT possible: (1) NT format mechanics, (2) NT media, (3) NT circuitry and board.

Sasaki, Toshikazu↗