Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “Circuit simulation”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 307 records · Page 17
All sourcesNASA NTRSDOE OSTI
NASA NTRS1991

Test and evaluation of the generalized gate logic system simulator

The results of the initial testing of the Generalized Gate Level Logic Simulator (GGLOSS) are discussed. The simulator is a special purpose fault simulator designed to assist in the analysis of the effects of random hardware failures on fault tolerant digital computer systems. The testing of the simulator covers two main areas. First, the simulation results are compared with data obtained by monitoring the behavior of hardware. The circuit used for these comparisons is an incomplete microprocessor design based upon the MIL-STD-1750A Instruction Set Architecture. In the second area of testing, current simulation results are compared with experimental data obtained using precursors of the current tool. In each case, a portion of the earlier experiment is confirmed. The new results are then viewed from a different perspective in order to evaluate the usefulness of this simulation strategy.

Miner, Paul S.↗
NASA NTRS1987

HSPICE modelling of a solar array circuit controlled by a fet switch

This paper presents a method of modeling a solar array circuit controlled by a hexfet switch on HSPICE. HSPICE models are developed for the solar array current voltage (IV) characteristic and the IRF150 hexfet. Computer simulations are made to verify rate of current change at the load. The equivalent LC circuit for the same current control is modeled to show savings in weight and power in choosing the fet switch over an LC circuit.

Cox, Deanna D.↗
NASA NTRS2001

A Comparison of Three-Dimensional Simulations of Traveling-Wave Tube Cold-Test Characteristics Using CST MICROWAVE STUDIO and MAFIA

Previously, it was shown that MAFIA (solutions of Maxwell's equations by the Finite Integration Algorithm), a three-dimensional simulation code, can be used to produce accurate cold-test characteristics including frequency-phase dispersion, interaction impedance, and attenuation for traveling-wave tube (TWT) slow-wave structures. In an effort to improve user-friendliness and simulation time, a model was developed to compute the cold-test parameters using the electromagnetic field simulation software package CST MICROWAVE STUDIO (MWS). Cold-test parameters were calculated for several slow-wave circuits including a ferruled coupled-cavity, a folded waveguide, and a novel finned-ladder circuit using both MWS and MAFIA. Comparisons indicate that MWS provides more accurate cold-test data with significantly reduced simulation times. Both MAFIA and MWS are based on the finite integration (FI) method; however, MWS has several advantages over MAFIA. First, it has a Windows based interface for PC operation, making it very user-friendly, whereas MAFIA is UNIX based. MWS uses a new Perfect Boundary Approximation (PBA), which increases the accuracy of the simulations by avoiding stair step approximations associated with MAFIA's representation of structures. Finally, MWS includes a Visual Basic for Applications (VBA) compatible macro language that enables the simulation process to be automated and allows for the optimization of user-defined goal functions, such as interaction impedance.

Chevalier, C. T.↗
NASA NTRS1991

Testing interconnected VLSI circuits in the Big Viterbi Decoder

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Onyszchuk, I. M.↗
NASA NTRS1992

Recent advances in superconducting-mixer simulations

Over the last few years, considerable progress have been made in the development of techniques for fabricating high-quality superconducting circuits, and this success, together with major advances in the theoretical understanding of quantum detection and mixing at millimeter and submillimeter wavelengths, has made the development of CAD techniques for superconducting nonlinear circuits an important new enterprise. For example, arrays of quasioptical mixers are now being manufactured, where the antennas, matching networks, filters and superconducting tunnel junctions are all fabricated by depositing niobium and a variety of oxides on a single quartz substrate. There are no adjustable tuning elements on these integrated circuits, and therefore, one must be able to predict their electrical behavior precisely. This requirement, together with a general interest in the generic behavior of devices such as direct detectors and harmonic mixers, has lead us to develop a range of CAD tools for simulating the large-signal, small-signal, and noise behavior of superconducting tunnel junction circuits.

Withington, S.↗
NASA NTRS2011

Characteristics of Radio-Frequency Circuits Utilizing Ferroelectric Capacitors

Ferroelectric capacitors, most commonly used in memory circuits and variable components, were studied in simple analog radio-frequency circuits such as the RLC resonator and Colpitts oscillator. The goal was to characterize the RF circuits in terms of frequency of oscillation, gain, etc, using ferroelectric capacitors. Frequencies of oscillation of both circuits were measured and studied a more accurate resonant frequency can be obtained using the ferroelectric capacitors. Many experiments were conducted and data collected. A model to simulate the experimental results will be developed. Discrepancies in gain and frequency in these RF circuits when conventional capacitors are replaced with ferroelectric ones were studied. These results will enable circuit designers to anticipate the effects of using ferroelectric components in their radio- frequency applications.

Eskridge, Michael↗
NASA NTRS1981

Life test of a nickel cadmium battery with a protection/reconditioning circuit

Results are discussed for a Ni-Cd battery test over a period of 8 years, 2 months and 44,213 simulated low Earth orbits. The battery cells were protected against overdischarge and reversal at discharge rates up to 25 amperes (1.25C) by a battery protection and reconditioning circuit. The circuit performed flawlessly during the test, and proved its value, both as a battery reconditioner and a cell protection device. Battery cell failures are also discussed. The test demonstrated the viability of using Ni-Cd batteries at depth-of-discharge up to 25 percent for over 5 years in a low Earth orbit.

Lanier, J. R., Jr.↗
NASA NTRS1971

Operating manual: Fast response solar array simulator

The fast response solar array simulator (FRSAS) is a universal solar array simulator which features an AC response identical to that of a real array over a large range of DC operating points. In addition, short circuit current (I sub sc) and open circuit voltage (V sub oc) are digitally programmable over a wide range for use not only in simulating a wide range of array sizes, but also to simulate (I sub sc) and (V sub oc) variations with illumination and temperature. A means for simulation of current variations due to spinning is available. Provisions for remote control and monitoring, automatic failure sensing and warning, and a load simulator are also included.

Vonhatten, R.↗
NASA NTRS2004

Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration

Current techniques in evolutionary synthesis of analogue and digital circuits designed at transistor level have focused on achieving the desired functional response, without paying sufficient attention to issues needed for a practical implementation of the resulting solution. No silicon fabrication of circuits with topologies designed by evolution has been done before, leaving open questions on the feasibility of the evolutionary circuit design approach, as well as on how high-performance, robust, or portable such designs could be when implemented in hardware. It is argued that moving from evolutionary 'design-for experimentation' to 'design-for-implementation' requires, beyond inclusion in the fitness function of measures indicative of circuit evaluation factors such as power consumption and robustness to temperature variations, the addition of certain evaluation techniques that are not common in conventional design. Several such techniques that were found to be useful in evolving designs for implementation are presented; some are general, and some are particular to the problem domain of transistor-level logic design, used here as a target application. The example used here is a multifunction NAND/NOR logic gate circuit, for which evolution obtained a creative circuit topology more compact than what has been achieved by multiplexing a NAND and a NOR gate. The circuit was fabricated in a 0.5 mum CMOS technology and silicon tests showed good correspondence with the simulations.

digital circuits designs↗
NASA NTRS1966

Rectilinear accelerometer possesses self- calibration feature

Rectilinear accelerometer operates from an ac source with a phase-sensitive ac voltage output proportional to the applied accelerations. The unit includes an independent circuit for self-test which provides a sensor output simulating an acceleration applied to the sensitive axis of the accelerometer.

Henderson, R. B.↗
NASA NTRS1975

A simulation analysis of phase processing circuitry in the Ohio University Omega receiver prototype

A FORTRAN IV simulation study of the all-digital phase-processing circuitry is described. A digital phase-lock loop (DPLL) forms the heart of the Omega navigation receiver prototype, and through the DPLL, the phase of the 10.2 KHz Omega signal was estimated when the true signal phase is contaminated with noise. The DPLL uses a frequency synthesizer as the reference oscillator. The synthesizer is composed of synchronous rate multipliers (SRM's) driven by a temperature-compensated crystal oscillator, and the use of the SRM's in this application introduces phase jitter which degrades system performance. Simulation of the frequency synthesizer discussed was to analyze the circuits on a bit-by-bit level in order to evaluate the overall design, to see easily the effects of proposed design changes prior to actual breadboarding, to determine the optimum integration time for the DPLL in an environment typical of general aviation conditions, and to quantify the phase error introduced by the SRM synthesizer and examine its effect on the system.

Palkovic, R. A.↗
NASA NTRS1978

The recalculation of the original pulse produced by a partial discharge

The loads on a dielectric or an insulation arrangement cannot be precisely rated without properly assessing the manner in which a pulse produced by a partial discharge is transmitted from the point of the event to the point where it is recorded. A number of analytical and graphic methods are presented, and computer simulations are used for specific cases of a few measurement circuits. It turns out to be possible to determine the effect of each circuit element and thus make some valid corrections.

Tanasescu, F.↗
NASA NTRS1985

The development of an interim generalized gate logic software simulator

A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.

Mcgough, J. G.↗
NASA NTRS1986

High efficiency crystalline silicon solar cells

A review of the entire research program since its inception ten years ago is given. The initial effort focused on the effects of impurities on the efficiency of silicon solar cells to provide figures of maximum allowable impurity density for efficiencies up to about 16 to 17%. Highly accurate experimental techniques were extended to characterize the recombination properties of the residual imputities in the silicon solar cell. A numerical simulator of the solar cell was also developed, using the Circuit Technique for Semiconductor Analysis. Recent effort focused on the delineation of the material and device parameters which limited the silicon efficiency to below 20% and on an investigation of cell designs to break the 20% barrier. Designs of the cell device structure and geometry can further reduce recombination losses as well as the sensitivity and criticalness of the fabrication technology required to exceed 20%. Further research is needed on the fundamental characterization of the carrier recombination properties at the chemical impurity and physical defect centers. It is shown that only single crystalline silicon cell technology can be successful in attaining efficiencies greater than 20%.

Sah, C. Tang↗
NASA NTRS1988

Refined Transistor Model For Simulation Of SEU

Equivalent base resistance added. Theoretical study develops equations for parameters of Gummel-Poon model of bipolar junction transistor: includes saturation current, amplification factors, charging times, knee currents, capacitances, and resistances. Portion of study concerned with base region goes beyond Gummel-Poon analysis to provide more complete understanding of transistor behavior. Extended theory useful in simulation of single-event upset (SEU) caused in logic circuits by cosmic rays or other ionizing radiation.

Zoutendyk, John A.↗
NASA NTRS1987

Performance of GaAs and silicon concentrator cells under 37 MeV proton irradiation

Gallium arsenide concentrator cells from three sources and silicon concentrator cells from one source were exposed to 37 MeV protons at fluences up to 2.8 x 10 to the 12th protons/sq cm. Performance data were taken after several fluences, at two temperatures (25 and 80 C), and at concentration levels from 1 to about 150 x AMO. Data at one sun and 25 C were taken with an X-25 xenon lamp solar simulator. Data at concentration were taken using a pulsed solar simulator with the assumption of a linear relationship between short circuit current and irradiance. The cells are 5 x 5 mm with a 4-mm diameter illuminated area.

Curtis, Henry B.↗
NASA NTRS1992

Aerodynamic roughness measured in the field and simulated in a wind tunnel

This study evaluates how well values of aerodynamic surface roughness, z sub 0, measured over scale models in wind tunnels correlate with values of z sub 0 measured at full scale in the field. A field experiment was conducted in which values of z sub 0 and u* (wind friction speed) were measured over three arrays of non-erodible roughness elements on a dry lake bed. Wind profiles were measured by ten anemometers on a 15 m mast under thermally neutral atmospheric conditions. Values of z sub 0 increased from .00014 m (dry lake bed only) to .026 m with increasing roughness element density. The three roughness element arrays were simulated at 1/10 and 1/20 scale in an open-circuit atmospheric boundary-layer wind tunnel. Velocities were measured with a boundary-layer pitot-tube rake from the same relative position within the scale model arrays as the anemometers were relative to the field arrays. Each array at each scale was sampled three times at five freestream velocities. Average values of z sub 0 for each model array at each scale were compared with full-scale values of z sub 0 obtained in the field. The field vs. wind tunnel correspondence of z sub 0 is found to be z sub 0 field = 0.2661 x (z sub(0 model) x scale(exp -1))exp .8159.

Sullivan, Robert↗