A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors [Poster]
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Quinn, A.↗
SEARCH · Engineering Papers
Results for “'CMOS',”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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A Soft-Error Hardened by Design MicroprocessorImplemented in Bulk 12-nm FINFET CMOS.
Abstract not provided.
Clark, Lawrence↗
Energy Efficient Deep Neural Network Processing: Digital CMOS Limits and Prospects for Analog In-Memory Computing.
Abstract not provided.
Marinella, Matthew↗
The Role of Bipolar Amplification in the SET Response of Narrowband RF Amplifiers Using SOI CMOS.
Abstract not provided.
Teng, Jeffrey W↗
Integrating atomic layer doping (ALDo) with CMOS circuitry for reduced contact resistance.
Abstract not provided.
Anderson, Evan↗
Summary of Recent Total Ionizing Dose Testing on GF 12LP CMOS Technology.
Abstract not provided.
Barnaby, Hugh↗
The CMOS Pseudo-Thyristor: A Zero-Static Current Circuit for Pixelized Detector Front-End Stage
These slides present robotics work at Fermilab and how new robotic technologies are introduced at the lab to encourage better reporting practices within the soft robotic community.
72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
Piezo-optomechanical Control of SiliconPhotonic Resonator with CMOS Compatibility
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Talcott, Gina↗
Radiation Effects on Performance of hybrid CMOS Imagers
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Looker, Quinn Michael↗
Characterization of Hot-carrier Enhanced Pixels for Out-of-band CMOS Camera
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Spotnitz, Matthew Emerson↗
Cryogenic high-speed transmitter and receiver circuits in advanced CMOS technology for quantum computing and technology
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Pacini, Diego↗
Predictive Quantum Transport Simulations for State-of-the-art and Beyond CMOS Device Technologies
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Mendez Granado, Juan Pedro [Sandia National Labora↗
Co-Design of Carbon Nanotube Photon Detectors Integrated on CMOS
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Leonard, Francois [Sandia National Laboratories (S↗
Rad-Hard Beyond CMOS Reservoir Computing with Continual Learning [Poster]
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Wells, William [Savannah River National Laboratory↗
High-performance low-power CMOS memories using silicon-on-sapphire technology.
MOS/silicon-on-sapphire (SOS) technology is shown to permit the realization of large-scale integrated arrays that combine the best features of monolithic bipolar and MOS technologies. The perfect isolation and reduced capacitance of SOS technology make possible static MOS circuits with nearly an order-of-magnitude improvement in speed and dynamic power dissipation over their monolithic counterparts. CMOS/SOS memory arrays have been fabricated with speeds comparable to TTL bipolar memory arrays even when operated at TTL compatible levels. Quiescent power dissipation of two described arrays is typically less than 1 microwatt/bit. The SOS/MOS technology is compatible with both aluminum and self-aligned silicon-gate processing.
Boleky, E. J.↗
CMOS array design automation techniques
A low cost, quick turnaround technique for generating custom metal oxide semiconductor arrays using the standard cell approach was developed, implemented, tested and validated. Basic cell design topology and guidelines are defined based on an extensive analysis that includes circuit, layout, process, array topology and required performance considerations particularly high circuit speed.
Ramondetta, P.↗
Prediction and measurement results of radiation damage to CMOS devices on board spacecraft
All the currently available results of the flight experiment for all the individually instrumented 130 transistors, relating to both biased and unbiased n- and p-channel RCA and -channel AMI devices were presented. The predictions of dose levels based on a detailed analysis of the space radiation environment as encountered by Explorer-55 and calculated by one dimensional slab geometry, and three dimensional spherical geometry were cited.
Stassinopoulos, E. G.↗