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At least 289 records · Page 16

Apparatus and Method for Cold Welding Thin Wafers to Hard Substrates

An apparatus for coating and bonding parts in a vacuum includes a floating mount assembly holding one part and applying a bonding load to the parts. A pivoting mount assembly holds one part and is pivoted between a coating position and a bonding position. At least one coating source is provided for depositing a thin film of a metal onto a surface of each of the parts to improve the cold weld between the two parts. A restraining lever controls the application of the bonding load to the parts. The coating and bonding process occurs in a vacuum chamber with a single set-up.

Oeftering, Richard C.↗

On-Wafer Characterization of Millimeter-Wave Antennas for Wireless Applications

The paper demonstrates a de-embedding technique and a direct on-substrate measurement technique for fast and inexpensive characterization of miniature antennas for wireless applications at millimeter-wave frequencies. The technique is demonstrated by measurements on a tapered slot antenna (TSA). The measured results at Ka-Band frequencies include input impedance, mutual coupling between two TSAs and absolute gain of TSA.

Simons, Rainee N.↗

Fabrication of Pop-up Detector Arrays on Si Wafers

High sensitivity is a basic requirement for a new generation of thermal detectors. To meet the requirement, close-packed, two-dimensional silicon detector arrays have been developed in NASA Goddard Space Flight Center. The goal of the task is to fabricate detector arrays configured with thermal detectors such as infrared bolometers and x-ray calorimeters to use in space fliGht missions. This paper focuses on the fabrication and the mechanical testing of detector arrays in a 0.2 mm pixel size, the smallest pop-up detectors being developed so far. These array structures, nicknamed "PUDS" for "Pop-Up Detectors", are fabricated on I pm thick, single-crystal, silicon membranes. Their designs have been refined so we can utilize the flexibility of thin silicon films by actually folding the silicon membranes to 90 degrees in order to obtain close-packed two-dimensional arrays. The PUD elements consist of a detector platform and two legs for mechanical support while also serving as electrical and thermal paths. Torsion bars and cantilevers connecting the detector platform to the legs provide additional flexures for strain relief. Using micro-electromechanical structure (MEMS) fabrication techniques, including photolithography, anisotropic chemical etching, reactive-ion etching, and laser dicing, we have fabricated PLTD detector arrays of fourteen designs with a variation of four parameters including cantilever length, torsion bar length and width, and leg length. Folding tests were conducted to test mechanical stress distribution for the array structures. We obtained folding yields and selected optimum design parameters to reach minimal stress levels. Computer simulation was also employed to verify mechanical behaviors of PUDs in the folding process. In addition, scanning electron microscopy was utilized to examine the flatness of detectors and the alignment of detector pixels in arrays. The fabrication of thermistors and heaters on the pop-up detectors is under way, preparing us for the next step of the experiment, the thermal test.

Li, Mary J.↗

Oxygen Impurities and Defects in Epitaxial Layer SiC and SiC Wafer Characterized by Room and Low Temperatures FTIR

SiC as a highly promising semiconducting material has received increasing attention in the last decade. The impurities such as oxygen and hydrogen have a great effect in electronic properties of semiconducting materials. In this study, the FTIR spectra were measured at room temperature (25 C) and low temperature (-70 C) for an n-type SiC substrate, a p-type epitaxial layer SiC, and patterned Ta on a p-type epitaxial layer SiC sample. The oxygen related IR peaks were measured for all three samples at room and low temperatures. The peak at 1105 cm(exp -1) is the result of a substitutional carbon and a interstitial oxygen in SiC. The concentration of the impurity oxygen increases in the SiC epitaxial layer during the CVD and electron beam processes. For the n-type SiC substrate, this peak does not appear. The peak at 905 cm(exp -1) exists in the IR spectra only for two epitaxial layer on p-type SiC substrate samples. This peak is related to oxygen vacancy centers in SiC, which are introduced in the CVD epitaxial growth process. At low temperature, the peak at 1105 cm(exp -1) shifts down and the peak at 905 cm(exp -1) shifts up for the epitaxial layer SiC samples. It can be explained that, at low temperatures, the stress increases due to the distorted bonds. The study shows that FTIR is a very effective method to evaluate low concentration impurities in SiC.

Lu, W. J.↗

Cosmic-ray Detector with Interdigitated-Finger Pixels for two-dimensional Position Information from a Singel Wafer Side

This paper describes a type of cosmic ray detector for isotopic and energy detection of energetic nuclei which derives both dimensions of position information from one side of the detector. This simplifies the required readout electronics, since only one precision amplifier connected to the other side is required for an accurate detection of the energy loss.

Cosmic-Ray Detector↗

The effect of integration of Strontium-Bismuth-Tantalate capacitors onto SOI wafers

We report for the first time the successful integration of Strontium-Bismuth-Tantalate ferroelectric capacitors on an SOI Substrate. We have verified that the unique processing requirements of SBT capacitors does not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.

SOI↗

The Effect of Integration of Strontium-Bismuth-Tantalate Capacitors onto SOI Wafers

We report for the first time the successful integration of Strontium-Bismuth-Tantalate ferroelectric capacitors on an SOI Substrate. We have verified that the unique processing requirements of SBT capacitors does not affect the properties of the surrounding FD-SOI transistors, and, conversely, we have verified that the SOI processing does not affect the quality of the SBT capacitors.

memory↗

Wafer bonded virtual substrate and method for forming the same

A method of forming a virtual substrate comprised of an optoelectronic device substrate and handle substrate comprises the steps of initiating bonding of the device substrate to the handle substrate, improving or increasing the mechanical strength of the device and handle substrates, and thinning the device substrate to leave a single-crystal film on the virtual substrate such as by exfoliation of a device film from the device substrate. The handle substrate is typically Si or other inexpensive common substrate material, while the optoelectronic device substrate is formed of more expensive and specialized electro-optic material. Using the methodology of the invention a wide variety of thin film electro-optic materials of high quality can be bonded to inexpensive substrates which serve as the mechanical support for an optoelectronic device layer fabricated in the thin film electro-optic material.

Atwater, Jr., Harry A.↗

Wafer bonded epitaxial templates for silicon heterostructures

A heterostructure device layer is epitaxially grown on a virtual substrate, such as an InP/InGaAs/InP double heterostructure. A device substrate and a handle substrate form the virtual substrate. The device substrate is bonded to the handle substrate and is composed of a material suitable for fabrication of optoelectronic devices. The handle substrate is composed of a material suitable for providing mechanical support. The mechanical strength of the device and handle substrates is improved and the device substrate is thinned to leave a single-crystal film on the virtual substrate such as by exfoliation of a device film from the device substrate. An upper portion of the device film exfoliated from the device substrate is removed to provide a smoother and less defect prone surface for an optoelectronic device. A heterostructure is epitaxially grown on the smoothed surface in which an optoelectronic device may be fabricated.

Atwater, Harry A., Jr.↗

HEMT Amplifiers and Equipment for their On-Wafer Testing

Power amplifiers comprising InP-based high-electron-mobility transistors (HEMTs) in coplanar-waveguide (CPW) circuits designed for operation at frequencies of hundreds of gigahertz, and a test set for onwafer measurement of their power levels have been developed. These amplifiers utilize an advanced 35-nm HEMT monolithic microwave integrated-circuit (MMIC) technology and have potential utility as local-oscillator drivers and power sources in future submillimeter-wavelength heterodyne receivers and imaging systems. The test set can reduce development time by enabling rapid output power characterization, not only of these and similar amplifiers, but also of other coplanar-waveguide power circuits, without the necessity of packaging the circuits.

Fung, King man↗