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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 289 records · Page 16
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Silicone Resins for Vat Polymerization Printing

This paper reviews research of silicone-based resins for vat polymerization printing (VPP). Silicone resins are used commonly in other 3D printing technologies because of their desirable properties. Silicones are chemically inert, oxidatively, and thermally stable, and have the lowest glass transition temperature of any polymer. Creating silicone resins processable by VPP is challenging because VPP requires low viscosity liquid resin that quickly photopolymerizes. This review will summarize VPP technologies, resin chemistries, and recent research of silicone VPP resins.

36 MATERIALS SCIENCE↗
NASA NTRS1972

Design, processing, and testing of lsi arrays for space station

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Lile, W. R.↗
NASA NTRS1981

Low cost solar array project cell and module formation research area: Process research of non-CZ silicon material

Liquid diffusion masks and liquid applied dopants to replace the CVD Silox masking and gaseous diffusion operations specified for forming junctions in the Westinghouse baseline process sequence for producing solar cells from dendritic web silicon were investigated. The baseline diffusion masking and drive processes were compared with those involving direct liquid applications to the dendritic web silicon strips. Attempts were made to control the number of variables by subjecting dendritic web strips cut from a single web crystal to both types of operations. Data generated reinforced earlier conclusions that efficiency levels at least as high as those achieved with the baseline back junction formation process can be achieved using liquid diffusion masks and liquid dopants. The deliveries of dendritic web sheet material and solar cells specified by the current contract were made as scheduled.

Source record↗
NASA NTRS1977

Silicon solar cells by high-speed low-temperature processing

A new method for silicon solar cell fabrication is being developed around ion implantation and pulsed electron beam techniques. Cells are fabricated totally in a vacuum environment at room temperature. Major reductions result in the time, energy consumption, and waste material generation associated with solar cell production. Cells to date have exhibited air mass zero efficiencies exceeding 10 percent.

Kirkpatrick, A. R.↗
NASA NTRS1995

Initial results for the silicon monolithically interconnected solar cell product

This proprietary technology is based on AstroPower's electrostatic bonding and innovative silicon solar cell processing techniques. Electrostatic bonding allows silicon wafers to be permanently attached to a thermally matched glass superstrate and then thinned to final thicknesses less than 25 micron. These devices are based on the features of a thin, light-trapping silicon solar cell: high voltage, high current, light weight (high specific power) and high radiation resistance. Monolithic interconnection allows the fabrication costs on a per watt basis to be roughly independent of the array size, power or voltage, therefore, the cost effectiveness to manufacture solar cell arrays with output powers ranging from milliwatts up to four watts and output voltages ranging from 5 to 500 volts will be similar. This compares favorably to conventionally manufactured, commercial solar cell arrays, where handling of small parts is very labor intensive and costly. In this way, a wide variety of product specifications can be met using the same fabrication techniques. Prototype solar cells have demonstrated efficiencies greater than 11%. An open-circuit voltage of 5.4 volts, fill factor of 65%, and short-circuit current density of 28 mA/sq cm at AM1.5 illumination are typical. Future efforts are being directed to optimization of the solar cell operating characteristics as well as production processing. The monolithic approach has a number of inherent advantages, including reduced cost per interconnect and increased reliability of array connections. These features make this proprietary technology an excellent candidate for a large number of consumer products.

Dinetta, L. C.↗
DOE OSTI2023

Phonon-Assisted Auger-Meitner Recombination in Silicon from First Principles

Here, we present a consistent first-principles methodology to study both direct and phonon-assisted Auger-Meitner recombination (AMR) in indirect-gap semiconductors that we apply to investigate the microscopic origin of AMR processes in silicon. Our results are in excellent agreement with experimental measurements and show that phonon-assisted contributions dominate the recombination rate in both n-type and p-type silicon, demonstrating the critical role of phonons in enabling AMR. We also decompose the overall rates into contributions from specific phonons and electronic valleys to further elucidate the microscopic origins of AMR. Our results highlight potential pathways to modify the AMR rate in silicon via strain engineering.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS2011

Cryo-Etched Black Silicon for Use as Optical Black

Stray light reflected from the surface of imaging spectrometer components in particular, the spectrometer slit degrade the image quality. A technique has been developed for rapid, uniform, and cost-effective black silicon formation based on inductively coupled plasma (ICP) etching at cryogenic temperatures. Recent measurements show less than 1-percent total reflectance from 350 2,500 nm of doped black silicon formed in this way, making it an excellent option for texturing of component surfaces for reduction of stray light. Oxygen combines with SF6 + Si etch byproducts to form a passivation layer atop the Si when the etch is performed at cryogenic temperatures. Excess flow of oxygen results in micromasking and the formation of black silicon. The process is repeatable and reliable, and provides control over etch depth and sidewall profile. Density of the needles can be controlled to some extent. Regions to be textured can be patterned lithographically. Adhesion is not an issue as the nanotips are part of the underlying substrate. This is in contrast to surface growth/deposition techniques such as carbon nanotubes (CNTs). The black Si surface is compatible with wet processing, including processing with solvents, the textured surface is completely inorganic, and it does not outgas. In radiometry applications, optical absorbers are often constructed using gold black or CNTs. This black silicon technology is an improvement for these types of applications.

Yee, Karl Y.↗
DOE OSTI2024

Modeling Reversible Volume Change in Automotive Battery Cells with Porous Silicon Oxide-Graphite Composite Anodes

Automotive battery manufacturers are working to improve the individual cell and overall pack design by increasing durability, performance, and range, while reducing cost, and active material volume change is a key aspect that needs to be considered during this design process. Recently, silicon oxide-graphite composite anodes are being explored to increase total anode capacity while maintaining a tolerable amount of cell level reversible volume expansion due to the relatively lower reversible volume change of the silicon oxide compared to pure battery grade or metallurgical grade silicon. To predict the blended anode response and contribution to the overall cell volume change, we integrated the mechanical behavior of the individual active materials with the multi-species, multi-reaction model to predict the state-of-lithiation of the active materials in the cell at a given potential. The resulting simulations illustrate the tradeoff in volume change between the silicon oxide and the graphite during cell operation. This type of modeling approach will allow designers to virtually consider the impact of cell level and pack level design changes on overall system mechanical performance for automotive and grid storage applications, namely that relatively small addition of silicon containing materials can drive a significant increase in the volume change at the cell level, as demonstrated by the 5 wt% addition of silicon oxide accounting for half of the overall volume change in the cell.

Garrick, Taylor R. (ORCID:0000000322518129)↗
DOE OSTI2024

Fracture Dynamics in Silicon Anode Solid-State Batteries

Solid-state batteries (SSBs) with silicon anodes could enable improved safety and energy density compared to lithium-ion batteries. However, degradation arising from the massive volumetric changes of silicon anodes during cycling is not well understood in solid-state systems. Here, we use operando X-ray computed microtomography to reveal micro- to macro-scale chemo-mechanical degradation processes of silicon anodes in SSBs. Mud-type channel cracks driven by biaxial tensile stress form across the electrode during delithiation. We also find detrimental cracks at the silicon/ solid electrolyte interface that form due to local reaction competition between neighboring domains of different sizes. Continuum phase-field damage modeling quantifies stress-driven channel cracking and shows that the lithiated silicon stress state is critical for determining the extent of interfacial fracture. This work reveals the mechanisms that govern SSBs compared to conventional lithium-ion batteries and provides guidelines for engineering chemomechanically resilient electrodes for high-energy batteries.

25 ENERGY STORAGE↗
DOE OSTI2020

Ionization Yield in Silicon for eV-Scale Electron-Recoil Processes

The development of single charge resolving, macroscopic silicon detectors has opened a window into rare processes at the O(eV) scale. In order to reconstruct the energy of a given event, or model the charge signal obtained for a given amount of energy absorbed by the electrons in a detector, an accurate charge yield model is needed. In this paper we review existing measurements of charge yield in Silicon, focusing in particular on the region below 1 keV. We highlight a calibration gap between 12-50 eV (referred to as the "UV-gap") and employ a phenomenological model of impact ionization to explore the likely charge yield in this energy regime. Finally, we explore the impact of variations in this model on a test case, that of dark matter scattering off electrons, to illustrate the scientific impact of uncertainties in charge yield.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1981

Processing experiments on non-Czochralski silicon sheet

A program is described which supports and promotes the development of processing techniques which may be successfully and cost-effectively applied to low-cost sheets for solar cell fabrication. Results are reported in the areas of process technology, cell design, cell metallization, and production cost simulation.

Pryor, R. A.↗
NASA NTRS2012

Controlled Directional Solidification of Aluminum - 7 wt Percent Silicon Alloys: Comparison Between Samples Processed on Earth and in the Microgravity Environment Aboard the International Space Station

An overview of the international "MIcrostructure Formation in CASTing of Technical Alloys" (MICAST) program is given. Directional solidification processing of metals and alloys is described, and why experiments conducted in the microgravity environment aboard the International Space Station (ISS) are expected to promote our understanding of this commercially relevant practice. Microstructural differences observed when comparing the aluminum - 7 wt% silicon alloys directionally solidified on Earth to those aboard the ISS are presented and discussed.

Grugel, Richard N.↗
NASA NTRS1988

Improved "Green" Forming Of Silicon Nitride

Advanced processing techniques reduce incidence of critical flaws. Critical flaws reduced by processing of powders to avoid organic and metallic contamination and combination of colloidal techniques with innovative slurry-pressing technique avoiding agglomeration. Silicon nitride considered for many applications ranging from components of turbine engines to industrial heat exchangers.

Freedman, Marc R.↗
NASA NTRS1995

Separation and Detection of Toxic Gases with a Silicon Micromachined Gas Chromatography System

A miniature gas chromatography (GC) system was designed and fabricated using silicon micromachining and integrated circuit (IC) processing techniques. The silicon micromachined gas chromatography system (SMGCS) is composed of a miniature sample injector that incorporates a 10 microliter sample loop; a 0.9 meter long, rectangular shaped (300 micrometer width and 10 micrometer height) capillary column coated with a 0.2 micrometer thick copper phthalocyanine (CuPc) stationary phase; and a dual detector scheme based upon a CuPc-coated chemiresistor and a commercially available 125 micrometer diameter thermal conductivity detector (TCD) bead. Silicon micromachining was employed to fabricate the interface between the sample injector and the GC column, the column itself, and the dual detector cavity. A novel IC thin-film processing technique was developed to sublime the CuPc stationary phase coating on the column walls that were micromachined in the host silicon wafer substrate and Pyrex (r) cover plate, which were then electrostatically bonded together. The SMGCS can separate binary gas mixtures composed of parts-per-million (ppm) concentrations of ammonia (NH3) and nitrogen dioxide (NO2) when isothermally operated (55-80 degrees C). With a helium carrier gas and nitrogen diluent, a 10 microliter sample volume containing ammonia and nitrogen dioxide injected at 40 psi ((2.8 x 10(exp 5)Pa)) can be separated in less than 30 minutes.

Kolesar, Edward S.↗
NASA NTRS2002

High-Power, High-Frequency Si-Based (SiGe) Transistors Developed

Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.

Ponchak, George E.↗
NASA NTRS2003

Process for Smoothing an Si Substrate after Etching of SiO2

A reactive-ion etching (RIE) process for smoothing a silicon substrate has been devised. The process is especially useful for smoothing those silicon areas that have been exposed by etching a pattern of holes in a layer of silicon dioxide that covers the substrate. Applications in which one could utilize smooth silicon surfaces like those produced by this process include fabrication of optical waveguides, epitaxial deposition of silicon on selected areas of silicon substrates, and preparation of silicon substrates for deposition of adherent metal layers. During etching away of a layer of SiO2 that covers an Si substrate, a polymer becomes deposited on the substrate, and the substrate surface becomes rough (roughness height approximately equal to 50 nm) as a result of over-etching or of deposition of the polymer. While it is possible to smooth a silicon substrate by wet chemical etching, the undesired consequences of wet chemical etching can include compromising the integrity of the SiO2 sidewalls and undercutting of the adjacent areas of the silicon dioxide that are meant to be left intact. The present RIE process results in anisotropic etching that removes the polymer and reduces height of roughness of the silicon substrate to less than 10 nm while leaving the SiO2 sidewalls intact and vertical. Control over substrate versus sidewall etching (in particular, preferential etching of the substrate) is achieved through selection of process parameters, including gas flow, power, and pressure. Such control is not uniformly and repeatably achievable in wet chemical etching. The recipe for the present RIE process is the following: Etch 1 - A mixture of CF4 and O2 gases flowing at rates of 25 to 75 and 75 to 125 standard cubic centimeters per minute (stdcm3/min), respectively; power between 44 and 55 W; and pressure between 45 and 55 mtorr (between 6.0 and 7.3 Pa). The etch rate lies between approximately equal to 3 and approximately equal to 6 nm/minute. Etch 2 - O2 gas flowing at 75 to 125 stdcm3/min, power between 44 and 55 W, and pressure between 50 and 100 mtorr (between 6.7 and 13.3 Pa).

Turner, Tasha↗