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At least 289 records · Page 16

Programs for analysis and resizing of complex structures

The paper describes the PARS (Programs for Analysis and Resizing of Structures) system. PARS is a user oriented system of programs for the minimum weight design of structures modeled by finite elements and subject to stress, displacement, flutter and thermal constraints. The system is built around SPAR - an efficient and modular general purpose finite element program, and consists of a series of processors that communicate through the use of a data base. An efficient optimizer based on the Sequence of Unconstrained Minimization Technique (SUMT) with an extended interior penalty function and Newton's method is used. Several problems are presented for demonstration of the system capabilities.

Haftka, R. T.↗

A Loran-C prototype navigation receiver for general aviation

Investigations have been conducted regarding the techniques required for Loran-C navigation with application to the general-aviation pilot. The goal has been to produce prototype equipment for flight evaluation which will provide enroute navigation in both latitude-longitude and rho-theta coordinates and to evaluate the nonprecision approach capabilities of such equipment. In connection with the considered project, a prototype Loran-C receiver has been flight-tested using a variety of flight paths, with and without simultaneous ground radar position data collection. Attention is given to a receiver overview, an antenna preamplifier/coupler, the Loran-C receiver RF processor, the tracking loop hardware, tracking loop programming, video output, the laboratory and flight evaluation, and work currently in progress.

Lilley, R. W.↗

Advanced information processing system - Status report

The Advanced Information Processing System (AIPS) is designed to provide a fault tolerant and damage tolerant data processing architecture for a broad range of aerospace vehicles. The AIPS architecture also has attributes to enhance system effectiveness such as graceful degradation, growth and change tolerance, integrability, etc. Two key building blocks being developed by the AIPS program are a fault and damage tolerant processor and communication network. A proof-of-concept system is now being built and will be tested to demonstrate the validity and performance of the AIPS concepts.

Brock, L. D.↗

Elevated temperature crack growth

The purpose is to determine the ability of currently available P-I integrals to correlate fatigue crack propagation under conditions that simulate the turbojet engine combustor liner environment. The utility of advanced fracture mechanics measurements will also be evaluated during the course of the program. To date, an appropriate specimen design, a crack displacement measurement method, and boundary condition simulation in the computational model of the specimen were achieved. Alloy 718 was selected as an analog material based on its ability to simulate high temperature behavior at lower temperatures. Tensile and cyclic tests were run at several strain rates so that an appropriate constitutive model could be developed. Suitable P-I integrals were programmed into a finite element post-processor for eventual comparison with experimental data.

Malik, S. N.↗

Parallel Inferencing For Rule-Based Expert Systems

Improved approach to development of expert-system computer programs increases speed of execution on parallel processors; that is, on multiple coordinated computers operating simultaneously, each on different part of problem. Based on detection and analysis of hidden parallelism in knowledge bases (collections of "if...then..." rules) and exploitation of this parallelism to maximize speed of execution on parallel processors connected to each other in hypercube configuration.

Schwuttke, Ursula M.↗

Computer simulation of water reclamation processors

The development of detailed simulation models of water reclamation processors based on the ASPEN PLUS simulation program is discussed. Individual models have been developed for vapor compression distillation, vapor phase catalytic ammonia removal, and supercritical water oxidation. These models are used for predicting the process behavior. Particular attention is given to methodology which is used to complete this work, and the insights which are gained by this type of model development.

Fisher, John W.↗

Eigensystem realization algorithm user's guide forVAX/VMS computers: Version 931216

The eigensystem realization algorithm (ERA) is a multiple-input, multiple-output, time domain technique for structural modal identification and minimum-order system realization. Modal identification is the process of calculating structural eigenvalues and eigenvectors (natural vibration frequencies, damping, mode shapes, and modal masses) from experimental data. System realization is the process of constructing state-space dynamic models for modern control design. This user's guide documents VAX/VMS-based FORTRAN software developed by the author since 1984 in conjunction with many applications. It consists of a main ERA program and 66 pre- and post-processors. The software provides complete modal identification capabilities and most system realization capabilities.

Pappa, Richard S.↗

Controlling accesses to a branch prediction unit for sequences of fetch groups

An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI. When each of the specified number of fetch groups is fetched and prepared for execution, the sequential fetch logic prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group.

Yalavarti, Adithya↗

Edge delamination of composite laminates subject to combined tension and torsional loading

Delamination is a common failure mode of laminated composite materials. Edge delamination is important since it results in reduced stiffness and strength of the laminate. The tension/torsion load condition is of particular significance to the structural integrity of composite helicopter rotor systems. Material coupons can easily be tested under this type of loading in servo-hydraulic tension/torsion test stands using techniques very similar to those used for the Edge Delamination Tensile Test (EDT) delamination specimen. Edge delamination of specimens loaded in tension was successfully analyzed by several investigators using both classical laminate theory and quasi-three dimensional (Q3D) finite element techniques. The former analysis technique can be used to predict the total strain energy release rate, while the latter technique enables the calculation of the mixed-mode strain energy release rates. The Q3D analysis is very efficient since it produces a three-dimensional solution to a two-dimensional domain. A computer program was developed which generates PATRAN commands to generate the finite element model. PATRAN is a pre- and post-processor which is commonly used with a variety of finite element programs such as MCS/NASTRAN. The program creates a sufficiently dense mesh at the delamination crack tips to support a mixed-mode fracture mechanics analysis. The program creates a coarse mesh in those regions where the gradients in the stress field are low (away from the delamination regions). A transition mesh is defined between these regions. This program is capable of generating a mesh for an arbitrarily oriented matrix crack. This program significantly reduces the modeling time required to generate these finite element meshes, thus providing a realistic tool with which to investigate the tension torsion problem.

Hooper, Steven J.↗

Autonomous space processor for orbital debris advanced design project in support of solar system exploration

This paper is regarding a project in the Advanced Design Program at the University of Arizona. The project is named the Autonomous Space Processor for Orbital Debris (ASPOD) and is a NASA/Universities Space Research Association (USRA) sponsored design project. The development of ASPOD and the students' abilities in designing and building a prototype spacecraft are the ultimate goals of this project. This year's focus entailed the development of a secondary robotic arm and end-effector to work in tandem with an existent arm in the removal of orbital debris. The new arm features the introduction of composite materials and a linear drive system, thus producing a light-weight and more accurate prototype. The main characteristic of the end-effector design is that it incorporates all of the motors and gearing internally, thus not subjecting them to the harsh space environment. Furthermore, the arm and the end-effector are automated by a control system with positional feedback. This system is composed of magnetic and optical encoders connected to a 486 PC via two servo-motor controller cards. Programming a series of basic routines and sub-routines has allowed the ASPOD prototype to become more autonomous. The new system is expected to perform specified tasks with a positional accuracy of 0.5 cm.

Ramohalli, Kumar↗

Programming the Navier-Stokes computer: An abstract machine model and a visual editor

The Navier-Stokes computer is a parallel computer designed to solve Computational Fluid Dynamics problems. Each processor contains several floating point units which can be configured under program control to implement a vector pipeline with several inputs and outputs. Since the development of an effective compiler for this computer appears to be very difficult, machine level programming seems necessary and support tools for this process have been studied. These support tools are organized into a graphical program editor. A programming process is described by which appropriate computations may be efficiently implemented on the Navier-Stokes computer. The graphical editor would support this programming process, verifying various programmer choices for correctness and deducing values such as pipeline delays and network configurations. Step by step details are provided and demonstrated with two example programs.

Middleton, David↗

Mark 3 correlator hardware and software

The Mark 3 correlator system is described in some detail. The correlator system is based on a modular philosophy. Each correlator module independently processes the data from one track pair. Therefore, 28 modules are necessary to complete a full one baseline processor and 84 modules for a full 3 baseline processor. Each correlator module has two interfaces: (1) data and clock from each of the two tracks to be correlated and (2) Computer Automated Measurement and Control (CAMAC) dataway interface to the computer. The processor is organized around the IEEE CAMAC standard architecture, housing 15 correlator modules in each of 6 crates. This allows one pass processing of a full 3 baseline 28 track observation or a 6 baseline (4 station) 14 track observation. The correlator architecture allows easy expansion for up to 8 stations. The computer system is an HP 1000 system utilizing a 16 bit minicomputer with disc and tape peripherals. The processing software is also organized in a modular fashion with many independent but cooperative programs controlling the operation of the Mark 3 processor. Processing time through the correlator is normally real time or faster, with graphics displays providing real time monitor and control of the processing operation.

Whitney, A. R.↗

The Automated Instrumentation and Monitoring System (AIMS) reference manual

Whether a researcher is designing the 'next parallel programming paradigm,' another 'scalable multiprocessor' or investigating resource allocation algorithms for multiprocessors, a facility that enables parallel program execution to be captured and displayed is invaluable. Careful analysis of execution traces can help computer designers and software architects to uncover system behavior and to take advantage of specific application characteristics and hardware features. A software tool kit that facilitates performance evaluation of parallel applications on multiprocessors is described. The Automated Instrumentation and Monitoring System (AIMS) has four major software components: a source code instrumentor which automatically inserts active event recorders into the program's source code before compilation; a run time performance-monitoring library, which collects performance data; a trace file animation and analysis tool kit which reconstructs program execution from the trace file; and a trace post-processor which compensate for data collection overhead. Besides being used as prototype for developing new techniques for instrumenting, monitoring, and visualizing parallel program execution, AIMS is also being incorporated into the run-time environments of various hardware test beds to evaluate their impact on user productivity. Currently, AIMS instrumentors accept FORTRAN and C parallel programs written for Intel's NX operating system on the iPSC family of multi computers. A run-time performance-monitoring library for the iPSC/860 is included in this release. We plan to release monitors for other platforms (such as PVM and TMC's CM-5) in the near future. Performance data collected can be graphically displayed on workstations (e.g. Sun Sparc and SGI) supporting X-Windows (in particular, Xl IR5, Motif 1.1.3).

Yan, Jerry↗

Power processing methodology

Discussion of the interim results of a program to investigate the feasibility of formulating a methodology for the modeling and analysis of aerospace electrical power processing systems. The object of the total program is to develop a flexible engineering tool which will allow the power processor designer to effectively and rapidly assess and analyze the tradeoffs available by providing, in one comprehensive program, a mathematical model, an analysis of expected performance, simulation, and a comparative evaluation with alternative designs. This requires an understanding of electrical power source characteristics and the effects of load control, protection, and total system interaction.

Fegley, K. A.↗

C-MOS array design techniques: SUMC multiprocessor system study

The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units.

Clapp, W. A.↗

Transputer parallel processing at NASA Lewis Research Center

The transputer parallel processing lab at NASA Lewis Research Center (LeRC) consists of 69 processors (transputers) that can be connected into various networks for use in general purpose concurrent processing applications. The main goal of the lab is to develop concurrent scientific and engineering application programs that will take advantage of the computational speed increases available on a parallel processor over the traditional sequential processor. Current research involves the development of basic programming tools. These tools will help standardize program interfaces to specific hardware by providing a set of common libraries for applications programmers. The thrust of the current effort is in developing a set of tools for graphics rendering/animation. The applications programmer currently has two options for on-screen plotting. One option can be used for static graphics displays and the other can be used for animated motion. The option for static display involves the use of 2-D graphics primitives that can be called from within an application program. These routines perform the standard 2-D geometric graphics operations in real-coordinate space as well as allowing multiple windows on a single screen.

Ellis, Graham K.↗

Project Report: Automatic Sequence Processor Software Analysis

The Mission Planning and Sequencing (MPS) element of Multi-Mission Ground System and Services (MGSS) provides space missions with multi-purpose software to plan spacecraft activities, sequence spacecraft commands, and then integrate these products and execute them on spacecraft. Jet Propulsion Laboratory (JPL) is currently is flying many missions. The processes for building, integrating, and testing the multi-mission uplink software need to be improved to meet the needs of the missions and the operations teams that command the spacecraft. The Multi-Mission Sequencing Team is responsible for collecting and processing the observations, experiments and engineering activities that are to be performed on a selected spacecraft. The collection of these activities is called a sequence and ultimately a sequence becomes a sequence of spacecraft commands. The operations teams check the sequence to make sure that no constraints are violated. The workflow process involves sending a program start command, which activates the Automatic Sequence Processor (ASP). The ASP is currently a file-based system that is comprised of scripts written in perl, c-shell and awk. Once this start process is complete, the system checks for errors and aborts if there are any; otherwise the system converts the commands to binary, and then sends the resultant information to be radiated to the spacecraft.

sequencing↗

A generic fine-grained parallel C

With the present availability of parallel processors of vastly different architectures, there is a need for a common language interface to multiple types of machines. The parallel C compiler, currently under development, is intended to be such a language. This language is based on the belief that an algorithm designed around fine-grained parallelism can be mapped relatively easily to different parallel architectures, since a large percentage of the parallelism has been identified. The compiler generates a FORTH-like machine-independent intermediate code. A machine-dependent translator will reside on each machine to generate the appropriate executable code, taking advantage of the particular architectures. The goal of this project is to allow a user to run the same program on such machines as the Massively Parallel Processor, the CRAY, the Connection Machine, and the CYBER 205 as well as serial machines such as VAXes, Macintoshes and Sun workstations.

Hamet, L.↗