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At least 289 records · Page 16

Neuromorphic Graph Algorithms: Cycle Detection, Odd Cycle Detection, and Max Flow

Neuromorphic computing is poised to become a promising computing paradigm in the post Moore’s law era due to its extremely low power usage and inherent parallelism. Spiking neural networks are the traditional use case for neuromorphic systems, and have proven to be highly effective at machine learning tasks such as control problems. More recently, neuromorphic systems have been applied outside of the arena of machine learning, primarily in the field of graph algorithms. Neuromorphic systems have been shown to perform graph algorithms faster and with lower power consumption than their traditional (GPU/CPU) counterparts, and are hence an attractive option for a co-processing unit in future high performance computing systems, where graph algorithms play a critical role. In this paper, we present a neuromorphic implementation of cycle detection, odd cycle detection, and the Ford-Fulkerson max-flow algorithm. We further evaluate the performance of these implementations using the NEST neuromorphic simulator by using spike counts and simulation time as proxies for energy consumption and run time. In addition to gains inherent in neuromorphic systems, we show that within the neuromorphic implementations early stopping criteria can be implemented to further improve performance.

Kay, Bill↗

SwitchX : Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars

Memristive crossbars can efficiently implement Binarized Neural Networks (BNNs) wherein the weights are stored in high-resistance states (HRS) and low-resistance states (LRS) of the synapses. We propose SwitchX mapping of BNN weights onto ReRAM crossbars such that the impact of crossbar non-idealities, that lead to degradation in computational accuracy, are minimized. Essentially, SwitchX maps the binary weights in such a manner that a crossbar instance comprises of more HRS than LRS synapses. We find BNNs mapped onto crossbars with SwitchX to exhibit better robustness against adversarial attacks than the standard crossbar mapped BNNs, the baseline. Finally, we combine SwitchX with state-aware training (that further increases the feasibility of HRS states during weight mapping) to boost the robustness of a BNN on hardware. We find that this approach yields stronger defense against adversarial attacks than adversarial training, a state-of the-art software defense. We perform experiments on a VGG16 BNN with benchmark datasets (CIFAR-10, CIFAR-100 and TinyImagenet) and use Fast Gradient Sign Method (ϵ = 0.05 to 0.3) and Projected Gradient Descent (ϵ = $\frac{2}{255}$ to $\frac{32}{255}$, α = $\frac{2}{255}$) adversarial attacks. We show that SwitchX combined with state-aware training can yield upto ~35% improvements in clean accuracy and ~6–16% in adversarial accuracies against conventional BNNs. Furthermore, an important by-product of SwitchX mapping is increased crossbar power savings, owing to an increased proportion of HRS synapses, which is furthered with state-aware training. We obtain upto ~21–22% savings in crossbar power consumption for state-aware trained BNN mapped via SwitchX on 16 × 16 and 32 × 32 crossbars using the CIFAR-10 and CIFAR-100 datasets.

97 MATHEMATICS AND COMPUTING↗

Understanding GPU Memory Corruption at Extreme Scale: The Summit Case Study

GPU memory corruption and in particular double-bit errors (DBEs) remain one of the least understood aspects of HPC system reliability. Albeit rare, their occurrences always lead to job termination and can potentially cost thousands of node-hours, either from wasted computations or as the overhead from regular checkpointing needed to minimize the losses. As supercomputers and their components simultaneously grow in scale, density, failure rates, and environmental footprint, the efficiency of HPC operations becomes both an imperative and a challenge. We examine DBEs using system telemetry data and logs collected from the Summit supercomputer, equipped with 27,648 Tesla V100 GPUs with 2nd-generation high-bandwidth memory (HBM2). Using exploratory data analysis and statistical learning, we extract several insights about memory reliability in such GPUs. We find that GPUs with prior DBE occurrences are prone to experience them again due to otherwise harmless factors, correlate this phenomenon with GPU placement, and suggest manufacturing variability as a factor. On the general population of GPUs, we link DBEs to short- and long-term high power consumption modes while finding no significant correlation with higher temperatures. We also show that the workload type can be a factor in memory’s propensity to corruption.

Oles, Vlad↗

ChemComp: A Compilation Framework for Computing with Chemical Reaction Networks

The acceleration of scientific computation, data analytics, and artificial intelligence is driving a surge in computational requirements. Yet, state-of-the-art high-performance computing systems are approaching physical limitations that impede further significant improvements in energy efficiency. As we move towards post-exascale computing systems, innovative approaches are necessary to overcome this barrier in power consumption. Novel analog and hybrid digital-analog architectures hold promise for enhancing energy efficiency by several orders of magnitude. Biochemical computation stands out among the various solutions being explored due to its potential to enable new classes of devices with immense computational capabilities. These devices can capitalize on the inherent efficacy of biological cells in solving optimization problems and are scalable through increasing reaction system size or vessel capacity, potentially satisfying scientific computing's high-performance requirements. Nonetheless, several theoretical and practical limitations persist, including problem formulation and mapping to chemical reaction networks (CRNs) and implementation of actual CRN devices. In this paper, we propose a framework for biochemical computation using systems chemistry. We present the initial components of our approach: an abstract chemical reaction dialect implemented as a multi-level intermediate representation (MLIR) compiler extension and a pathway to represent mathematical problems with CRNs. To showcase the potential of this approach, we emulate a simplified chemical reservoir device. This work lays the groundwork for leveraging chemistry's computing potential in creating energy-efficient, high-performance computing systems tailored to contemporary computational needs.

artificial intelligence↗

A Global Perspective on Supercomputer Power Provisioning: Case Studies from United States and Europe

Electrical provisioning in high performance computing is transitioning from simple nameplate Thermal Design Power (TDP) models to more nuanced approaches based on expected electrical load. This paper captures current power provisioning strategies across six international supercomputing centers and seven systems, three of which (Lumi, Summit, Sierra) were in the top 10 of the Top500 list at the time of data collection1. We present longitudinal and summary data of actual power consumption as well as a discussion of how each site approached the question of provisioning. We conclude with a discussion on future directions of hardware overprovisioning and its implications for machine and electrical utilization.

Patki, Tapasya [Lawrence Livermore National Labora↗

Performance Impact and Trade-Offs for Tuning Key Architectural Parameters on CPU+GPU Systems

In this work, we performed an initial design space exploration of an accelerated processing unit (APU)—a hybrid CPU+GPU architecture that integrates both compute units (CUs) and memory into a unified system. This integration aims to reduce data movement, enhance memory locality, and improve energy efficiency by enabling the CPU and GPU to share memory directly. This effort focused on the interplay of key design components—cache line size, the number of CUs, and main memory technology—and the trade-offs of each configuration were analyzed. This paper highlights the various configurations’ impact on memory accesses, data reuse, and power utilization. The results provide valuable insights that can be leveraged to optimize APU architectures for high-performance and energy-efficient computing and thus create a balanced architecture. This optimization can be achieved by adopting dynamic cache management, runtime CU scaling, and advanced memory integration, highlighting the potential of APUs to address critical challenges in compute, data movement, and memory power consumption.

Asifuzzaman, Kazi [ORNL] (ORCID:0000000240044791)↗

Electricity Bill Calculator (elecprice) v0.1.0

The Electricity Bill Calculator Library is a generic tool for manipulating the tariffs of electricity, with an emphasis on commercial Time-Of-Use (TOU) rates in the U.S. and residential Net Energy Metering tariffs in CA. Typical uses of the package are price signal generation and bill computation. To generate price signals from a specific tariff and given a time window, the tool creates a pandas dataframes containing the various components of the electricity charges, at each time step. This is particularly useful for Demand Response (DR) applications, such as price-based optimization of energy in buildings. The tool also computes bills given a building's power consumption and a specific tariff and returning the corresponding cost of electricity, as well as a breakdown per type of rate.

Prakash, Anand Krishnan↗

Data-driven analysis to understand GPU hardware resource usage of optimizations

With heterogeneous systems, the number of GPUs per chip increases to provide computational capabilities for solving science at a nanoscopic scale. However, low utilization for single GPUs defies the need to invest more money in expensive accelerators. Although related work develops optimizations to improve application performance, none studies how these optimizations impact hardware resource usage or average GPU utilization. Here, this paper takes a data-driven analysis approach in addressing this gap by (1) characterizing how hardware resource usage affects device utilization, execution time, or both, (2) presenting a multiobjective metric to identify important application-device interactions that can be optimized to improve device utilization and application performance jointly, (3) studying hardware resource usage behaviors of several optimizations for a benchmark application, and finally (4) identifying optimization opportunities for several scientific proxy applications based on their hardware resource usage behaviors. Furthermore, we demonstrate the applicability of our methodology by applying the identified optimizations to a proxy application, which improves the execution time, device utilization, and power consumption by up to 29.6%, 5.3% and 26.5% respectively.

Computer science↗

Polyhedral Relaxations for Optimal Pump Scheduling of Potable Water Distribution Networks

The classic pump scheduling or optimal water flow (OWF) problem for water distribution networks (WDNs) minimizes the cost of power consumption for a given WDN over a fixed time horizon. In its exact form, the OWF is a computationally challenging mixed-integer nonlinear program (MINLP). It is complicated by nonlinear equality constraints that model network physics, discrete variables that model operational controls, and intertemporal constraints that model changes to storage devices. To address the computational challenges of the OWF, this paper develops tight polyhedral relaxations of the original MINLP, derives novel valid inequalities (or cuts) using duality theory, and implements novel optimization-based bound tightening and cut generation procedures. The efficacy of each new method is rigorously evaluated by measuring empirical improvements in OWF primal and dual bounds over 45 literature instances. The evaluation suggests that our relaxation improvements, model strengthening techniques, and a thoughtfully selected polyhedral relaxation partitioning scheme can substantially improve OWF primal and dual bounds, especially when compared with similar relaxation-based techniques that do not leverage these new methods.

bound tightening↗

Implement-Only Implementation of a Multi Pressure Rail System to an Agricultural Planter

Tightening emissions regulations and rising fuel costs have driven a desire across many industries for more efficient actuation systems. This is particularly true of the agricultural sector. An extremely common arrangement in this sector is the tractor and implement pairing, in which actuators on an implement are powered by a hydraulic supply system on the towing tractor. This arrangement complicates the development of energy efficient hydraulic systems, as many new system designs require modification of both machines to reap efficiency benefits. Past work by the authors’ team has demonstrated great potentials for Multi-Pressure-Rail (MPR) technology involving both the tractor and implement subsystems. However, applicability of this MPR technology in a more realistic scenario where only one vehicle is equipped with such technology was not addressed. This work proposes an implementation of the MPR technology to an agricultural planter that allows significant savings, while only modifying the implement machine. This is done by manipulating the load sense network of a stock tractor to set system pressures to those required by the MPR system. This greatly reduces the barrier to implementation of MPR technology in agriculture. The work begins by outlining the reference machine for the system, then reviews the MPR system working principle. After this, the proposed expansion to the MPR concept is laid out, and applied to the reference system. Finally, experimental validation is carried out, demonstrating on average 37% reduction in system power consumption.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

Performance trade-offs in reconfigurable networks for HPC

Designing efficient interconnects to support high-bandwidth and low-latency communication is critical toward realizing high performance computing (HPC) and data center (DC) systems in the exascale era. At extreme computing scales, providing the requisite bandwidth through overprovisioning becomes impractical. These challenges have motivated studies exploring reconfigurable network architectures that can adapt to traffic patterns at runtime using optical circuit switching. Despite the plethora of proposed architectures, surprisingly little is known about the relative performances and trade-offs among different reconfigurable network designs. We aim to bridge this gap by tackling two key issues in reconfigurable network design. First, we study how cost, power consumption, network performance, and scalability vary based on optical circuit switch (OCS) placement in the physical topology. Specifically, we consider two classes of reconfigurable architectures: one that places OCSs between top-of-rack (ToR) switches—ToR-reconfigurable networks (TRNs)—and one that places OCSs between pods of racks—pod-reconfigurable networks (PRNs). Second, we tackle the effects of reconfiguration frequency on network performance. Our results, based on network simulations driven by real HPC and DC workloads, show that while TRNs are optimized for low fan-out communication patterns, they are less suited for carrying high fan-out workloads. PRNs exhibit better overall trade-off, capable of performing comparably to a fully non-blocking fat tree for low fan-out workloads, and significantly outperform TRNs for high fan-out communication patterns.

Teh, Min Yee↗

Compact mid-infrared dual-comb spectrometer for outdoor spectroscopy

This manuscript describes the design of a robust, mid-infrared dual-comb spectrometer operating in the 3.1-µm to 4-µm spectral window for future field applications. The design represents an improvement in system size, power consumption, and robustness relative to previous work while also providing a high spectral signal-to-noise ratio. We demonstrate a system quality factor of 2×10 6 and 30 hours of continuous operation over a 120-meter outdoor air path.

Ycas, Gabriel↗

Thermo-optic properties of silicon-rich silicon nitride for on-chip applications

We demonstrate the thermo-optic properties of silicon-rich silicon nitride (SRN) films deposited using plasma-enhanced chemical vapor deposition (PECVD). Shifts in the spectral response of Mach-Zehnder interferometers (MZIs) as a function of temperature were used to characterize the thermo-optic coefficients of silicon nitride films with varying silicon contents. A clear relation is demonstrated between the silicon content and the exhibited thermo-optic coefficient in silicon nitride films, with the highest achievable coefficient being as high as (1.65±0.08) ×10 −4 K -1 . Furthermore, we realize an SRN multi-mode interferometer (MMI) based thermo-optic switch with over 20 dB extinction ratio and total power consumption for two-port switching of 50 mW.

Nejadriahi, Hani↗

Ultra-low loss visible light waveguides for integrated atomic, molecular, and quantum photonics

Atomic, molecular and optical (AMO) visible light systems are the heart of precision applications including quantum, atomic clocks and precision metrology. As these systems scale in terms of number of lasers, wavelengths, and optical components, their reliability, space occupied, and power consumption will push the limits of using traditional laboratory-scale lasers and optics. Visible light photonic integration is critical to advancing AMO based sciences and applications, yet key performance aspects remain to be addressed, most notably waveguide losses and laser phase noise and stability. Additionally, a visible light integrated solution needs to be wafer-scale CMOS compatible and capable of supporting a wide array of photonic components. While the regime of ultra-low loss has been achieved at telecommunication wavelengths, progress at visible wavelengths has been limited. Here, we report the lowest waveguide losses and highest resonator Qs to date in the visible range, to the best of our knowledge. We report waveguide losses at wavelengths associated with strontium transitions in the 461 nm to 802 nm wavelength range, of 0.01 dB/cm to 0.09 dB/cm and associated intrinsic resonator Q of 60 Million to 9.5 Million, a decrease in loss by factors of 6x to 2x and increase in Q by factors of 10x to 1.5x over this visible wavelength range. Additionally, we measure an absorption limited loss and Q of 0.17 dB/m and 340 million at 674 nm. This level of performance is achieved in a wafer-scale foundry compatible Si 3 N 4 platform with a 20 nm thick core and TEOS-PECVD deposited upper cladding oxide, and enables waveguides for different wavelengths to be fabricated on the same wafer with mask-only changes per wavelength. These results represent a significant step forward in waveguide platforms that operate in the visible, opening up a wide range of integrated applications that utilize atoms, ions and molecules including sensing, navigation, metrology and clocks.

Chauhan, Nitesh↗

Integrated SOAs enable energy-efficient intra-data center coherent links

Coherent optical links are becoming increasingly attractive for intra-data center applications as data rates scale. Realizing the era of high-volume short-reach coherent links will require substantial improvements in transceiver cost and power efficiency, necessitating a reassessment of conventional architectures best-suited for longer-reach links and a review of assumptions for shorter-reach implementations. In this work, we analyze the impact of integrated semiconductor optical amplifiers (SOAs) on link performance and power consumption, and describe the optimal design spaces for low-cost and energy-efficient coherent links. Placing SOAs after the modulator provide the most energy-efficient link budget improvement, up to 6 pJ/bit for large link budgets, despite any penalties from nonlinear impairments. Increased robustness to SOA nonlinearities makes QPSK-based coherent links especially attractive, and larger supported link budgets enable the inclusion of optical switches, which could revolutionize data center networks and improve overall energy efficiency.

Maharry, Aaron (ORCID:0000000273732697)↗

Prediction of laser beam spatial profiles in a high-energy laser facility by use of deep learning

We adapt the significant advances achieved recently in the field of generative artificial intelligence/machine-learning to laser performance modeling in multipass, high-energy laser systems with application to high-shot-rate facilities relevant to inertial fusion energy. Advantages of neural-network architectures include rapid prediction capability, data-driven processing, and the possibility to implement such architectures within future low-latency, low-power consumption photonic networks. Four models were investigated that differed in their generator loss functions and utilized the U-Net encoder/decoder architecture with either a reconstruction loss alone or combined with an adversarial network loss. We achieved inference times of 1.3 ms for a 256 × 256 pixel near-field beam with errors in predicted energy of the order of 1% over most of the energy range. It is shown that prediction errors are significantly reduced by ensemble averaging the models with different weight initializations. These results suggest that including the temporal dimension in such models may provide accurate, real-time spatiotemporal predictions of laser performance in high-shot-rate laser systems.

47 OTHER INSTRUMENTATION↗

Ultra-power-efficient heterogeneous III–V/Si MOSCAP (de-)interleavers for DWDM optical links

We discuss the design and demonstration of various III–V/Si asymmetric Mach–Zehnder interferometer (AMZI) and ring-assisted AMZI (de-)interleavers operating at O-band wavelengths with 65 GHz channel spacing. The wafer-bonded III–V/Si metal-oxide-semiconductor capacitor (MOSCAP) structure facilitates ultra-low-power phase tuning on a heterogeneous platform that allows for complete monolithic transceiver photonic integration. The second- and third-order MOSCAP AMZI (de-)interleavers exhibit cross-talk (XT) levels down to − 22 dB and − 32 dB with tuning powers of 83.0 nW and 53.0 nW, respectively. The one-, two-, and three-ring-assisted MOSCAP AMZI (de-)interleavers have XT levels down to − 27 dB, − 22 dB, and − 20 dB for tuning powers of 10.0 nW, 7220.0 nW, and 33.6 nW, respectively. The leakage current density is measured to be in the range of 1.6 – 27 μA / cm 2 . To the best of our knowledge, we have demonstrated for the first time, athermal III–V/Si MOSCAP (de-)interleavers with the lowest XT and reconfiguration power consumption on a silicon platform.

Cheung, Stanley (ORCID:0000000248860013)↗

Nanolaser arrays: toward application-driven dense integration

Abstract The past two decades have seen widespread efforts being directed toward the development of nanoscale lasers. A plethora of studies on single such emitters have helped demonstrate their advantageous characteristics such as ultrasmall footprints, low power consumption, and room-temperature operation. Leveraging knowledge about single nanolasers, the next phase of nanolaser technology will be geared toward scaling up design to form arrays for important applications. In this review, we discuss recent progress on the development of such array architectures of nanolasers. We focus on valuable attributes and phenomena realized due to unique array designs that may help enable real-world, practical applications. Arrays consisting of exactly two nanolasers are first introduced since they can serve as a building block toward comprehending the behavior of larger lattices. These larger-sized lattices can be distinguished depending on whether or not their constituent elements are coupled to one another in some form. While uncoupled arrays are suitable for applications such as imaging, biosensing, and even cryptography, coupling in arrays allows control over many aspects of the emission behavior such as beam directionality, mode switching, and orbital angular momentum. We conclude by discussing some important future directions involving nanolaser arrays.

Deka, Suruj S.↗