Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “low memory”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 289 records · Page 16

Facile fabrication of highly ordered poly(vinylidene fluoride-trifluoroethylene) nanodot arrays for organic ferroelectric memory

Nano-patterned ferroelectric materials have attracted significant attention as the presence of two or more thermodynamically equivalent switchable polarization states can be employed in many applications such as non-volatile memory. In this work, a simple and effective approach for fabrication of highly ordered poly(vinylidene fluoride–trifluoroethylene) P(VDF-TrFE) nanodot arrays is demonstrated. By using a soft polydimethylsiloxane mold, we successfully transferred the 2D array pattern from the initial monolayer of colloidal polystyrene nanospheres to the imprinted P(VDF-TrFE) films via nanoimprinting. The existence of a preferred orientation of the copolymer chain after nanoimprinting was confirmed by Fourier transform infrared spectra. Local polarization switching behavior was measured by piezoresponse force microscopy, and each nanodot showed well-formed hysteresis curve and butterfly loop with a coercive field of ∼62.5 MV/m. To illustrate the potential application of these ordered P(VDF-TrFE) nanodot arrays, the writing and reading process as non-volatile memory was demonstrated at a relatively low voltage. As such, our results offer a facile and promising route to produce arrays of ferroelectric polymer nanodots with improved piezoelectric functionality.

36 MATERIALS SCIENCE↗

Epitaxial Co 50 Fe 50 (110)/Pt(111) films on MgAl 2 O 4 (001) and its enhancement of perpendicular magnetic anisotropy

Perpendicular magnetic anisotropy (PMA) in magnetic thin films with low coercivity is desirable for magnetic memory devices. It has been discovered that a (111)-oriented or textured Pt seed layer can enhance PMA and is, therefore, commonly utilized in spintronic structures. We grow (111)-oriented Pt epitaxial films via off-axis sputtering on various substrates and investigate the optimal substrate and orientation for high quality, epitaxial growth. Our results show that Pt(111) epitaxial films grow remarkably well on MgAl 2 O 4 (001) with an exceptionally narrow X-ray diffraction rocking curve. This high-quality seed layer is determined to promote epitaxial growth of Pt/Co 50 Fe 50 /Pt trilayers with strong PMA comparable to many repeats of the magnetic multilayers reported previously. In addition, the Pt seed layer enhances the maximum thicknesses of Co 50 Fe 50 that can still maintain PMA up to 1.07 nm.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Thickness scaling and ferroelectric switching in wurtzite structure zinc magnesium oxide thin films

This study reports the thickness scaling of sputtered ferroelectric Zn 0.61 Mg 0.39 O (ZMO) thin films down to 43 nm. Encapsulated IrO 2 /ZMO/Ir capacitors exhibited switchable polarizations exceeding 50 μC cm −2 and coercive fields that increased from 3.9 to 4.4 MV cm −1 as the thickness decreased. Switching kinetics are best described by the simultaneous non-linear nucleation and the growth model. Bimodal switching is prevalent at low thicknesses, with the fastest switching times measured to be approximately 400 ns. Device encapsulation made ZMO switching kinetics more abrupt, potentially due to changes in the concentration of atmosphere-induced defects such as hydroxides. These results demonstrate stable ferroelectricity and sub-microsecond switching in sub-50 nm wurtzite ZMO, highlighting its potential as a low-voltage ferroelectric for integrated nonvolatile memory applications.

36 MATERIALS SCIENCE↗

Toward an optimal online checkpoint solution under a two-level HPC checkpoint model

The traditional single-level checkpointing method suffers from significant overhead on large-scale platforms. Hence, multilevel checkpointing protocols have been studied extensively in recent years. The multilevel checkpoint approach allows different levels of checkpoints to be set (each with different checkpoint overheads and recovery abilities), in order to further improve the fault tolerance performance of extreme-scale HPC applications. How to optimize the checkpoint intervals for each level, however, is an extremely difficult problem. In this paper, we construct an easy-to-use two-level checkpoint model. Checkpoint level 1 deals with errors with low checkpoint/recovery overheads such as transient memory errors, while checkpoint level 2 deals with hardware crashes such as node failures. Compared with previous optimization work, our new optimal checkpoint solution offers two improvements: (1) it is an online solution without requiring knowledge of the job length in advance, and (2) it shows that periodic patterns are optimal and determines the best pattern. We evaluate the proposed solution and compare it with the most up-to-date related approaches on an extreme-scale simulation testbed constructed based on a real HPC application execution. Simulation results show that our proposed solution outperforms other optimized solutions and can improve the performance significantly in some cases. Specifically, with the new solution the wall-clock time can be reduced by up to 25.3% over that of other state-of-the-art approaches. Lastly, a brute-force comparison with all possible patterns shows that our solution is always within 1% of the best pattern in the experiments.

97 MATHEMATICS AND COMPUTING↗

Low dose irradiation profoundly affects transcriptome and microRNAme in rat mammary gland tissues

Ionizing radiation has been successfully used in medical tests and treatment therapies for a variety of medical conditions. However, patients and health-care workers are greatly concerned about overexposure to medical ionizing radiation and possible cancer induction due to frequent mammographies and/or CT scans. Diagnostic imaging involves the use of low doses of ionizing radiation, and its potential carcinogenic role creates a cancer risk concern for exposed individuals. In this study, the effects of X-ray exposure of different doses on the gene expression patterns and the micro-RNA expression patterns in normal breast tissue were investigated in rats. Our results revealed the activation of immune response pathways upon low dose of radiation exposure. These included natural killer mediated cytotoxicity pathways, antigen processing and presentation pathways, chemokine signaling pathways, and T- and B-cell receptor signaling pathways. Both high and low doses of radiation led to miRNA expression alterations. Increased expression of miR-34a may be linked to cell cycle arrest and apoptosis. Up-regulation of miR-34a was correlated with down-regulation of its target E2F3 and up-regulation of p53. This data suggests that ionizing radiation at specific high and low doses leads to cell cycle arrest and a possible initiation of apoptosis.

59 BASIC BIOLOGICAL SCIENCES↗

RAM-Based frame synchronizer

Frame synchronizer for serial telemetry is rapidly reconfigured for changing formats. Synchronizer generates signals marking data-word boundaries, beginning of each frame, and beginning of each paragraph. Also derived are search, check, and lock status signals. Existing unit is assembled from standard random-access memory elements and MOS and low-power-Schottky logic.

Niswander, J. K.↗

Bipolar and Monopolar Lithium-Ion Battery Technology at Yardney

Lithium-ion battery systems offer several advantages: intrinsically safe; long cycle life; environmentally friendly; high energy density; wide operating temperature range; good discharge rate capability; low self-discharge; and no memory effect.

Russell, P.↗

Probabilistic resource allocation system with self-adaptive capability

A probabilistic resource allocation system is disclosed containing a low capacity computational module (Short Term Memory or STM) and a self-organizing associative network (Long Term Memory or LTM) where nodes represent elementary resources, terminal end nodes represent goals, and weighted links represent the order of resource association in different allocation episodes. Goals and their priorities are indicated by the user, and allocation decisions are made in the STM, while candidate associations of resources are supplied by the LTM based on the association strength (reliability). Weights are automatically assigned to the network links based on the frequency and relative success of exercising those links in the previous allocation decisions. Accumulation of allocation history in the form of an associative network in the LTM reduces computational demands on subsequent allocations. For this purpose, the network automatically partitions itself into strongly associated high reliability packets, allowing fast approximate computation and display of allocation solutions satisfying the overall reliability and other user-imposed constraints. System performance improves in time due to modification of network parameters and partitioning criteria based on the performance feedback.

Yufik, Yan M.↗

Probabilistic resource allocation system with self-adaptive capability

A probabilistic resource allocation system is disclosed containing a low capacity computational module (Short Term Memory or STM) and a self-organizing associative network (Long Term Memory or LTM) where nodes represent elementary resources, terminal end nodes represent goals, and directed links represent the order of resource association in different allocation episodes. Goals and their priorities are indicated by the user, and allocation decisions are made in the STM, while candidate associations of resources are supplied by the LTM based on the association strength (reliability). Reliability values are automatically assigned to the network links based on the frequency and relative success of exercising those links in the previous allocation decisions. Accumulation of allocation history in the form of an associative network in the LTM reduces computational demands on subsequent allocations. For this purpose, the network automatically partitions itself into strongly associated high reliability packets, allowing fast approximate computation and display of allocation solutions satisfying the overall reliability and other user-imposed constraints. System performance improves in time due to modification of network parameters and partitioning criteria based on the performance feedback.

Yufik, Yan M.↗

Low-temperature etching of silicon oxide and silicon nitride with hydrogen fluoride

Etching of high aspect ratio features into alternating SiO 2 and SiN layers is an enabling technology for the manufacturing of 3D NAND flash memories. In this paper, we study a low-temperature or cryo plasma etch process, which utilizes HF gas together with other gas additives. Compared with a low-temperature process that uses separate fluorine and hydrogen gases, the etching rate of the SiO 2 /SiN stack doubles. Both materials etch faster with this so-called second generation cryo etch process. Pure HF plasma enhances the SiN etching rate, while SiO 2 requires an additional fluorine source such as PF 3 to etch meaningfully. Further, the insertion of H 2 O plasma steps into the second generation cryo etch process boosts the SiN etching rate by a factor of 2.4, while SiO 2 etches only 1.3 times faster. We observe a rate enhancing effect of H 2 O coadsorption in thermal etching experiments of SiN with HF. Ammonium fluorosilicate (AFS) plays a salient role in etching of SiN with HF with and without plasma. AFS appears weakened in the presence of H 2 O. Density functional theory calculations confirm the reduction of the bonding energy when NH 4 F in AFS is replaced by H 2 O.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Spaceborne Processor Array

A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

Chow, Edward T.↗

The Use of Field Programmable Gate Arrays (FPGA) in Small Satellite Communication Systems

This paper will describe the use of digital Field Programmable Gate Arrays (FPGA) to contribute to advancing the state-of-the-art in software defined radio (SDR) transponder design for the emerging SmallSat and CubeSat industry and to provide advances for NASA as described in the TAO5 Communication and Navigation Roadmap (Ref 4). The use of software defined radios (SDR) has been around for a long time. A typical implementation of the SDR is to use a processor and write software to implement all the functions of filtering, carrier recovery, error correction, framing etc. Even with modern high speed and low power digital signal processors, high speed memories, and efficient coding, the compute intensive nature of digital filters, error correcting and other algorithms is too much for modern processors to get efficient use of the available bandwidth to the ground. By using FPGAs, these compute intensive tasks can be done in parallel, pipelined fashion and more efficiently use every clock cycle to significantly increase throughput while maintaining low power. These methods will implement digital radios with significant data rates in the X and Ka bands. Using these state-of-the-art technologies, unprecedented uplink and downlink capabilities can be achieved in a 1/2 U sized telemetry system. Additionally, modern FPGAs have embedded processing systems, such as ARM cores, integrated inside the FPGA allowing mundane tasks such as parameter commanding to occur easily and flexibly. Potential partners include other NASA centers, industry and the DOD. These assets are associated with small satellite demonstration flights, LEO and deep space applications. MSFC currently has an SDR transponder test-bed using Hardware-in-the-Loop techniques to evaluate and improve SDR technologies.

Varnavas, Kosta↗

Surface Control of Cold Hibernated Elastic Memory Self-Deployable Structure

A new class of simple, reliable, lightweight, low packaging volume and cost, self-deployable structures has been developed for use in space and commercial applications. This technology called 'cold hibernated elastic memory' (CHEM) utilizes shape memory polymers (SMP)in open cellular (foam) structure or sandwich structures made of shape memory polymer foam cores and polymeric composite skins. Some of many potential CHEM space applications require a high precision deployment and surface accuracy during operation. However, a CHEM structure could be slightly distorted by the thermo-mechanical processing as well as by thermal space environment Therefore, the sensor system is desirable to monitor and correct the potential surface imperfection. During these studies, the surface control of CHEM smart structures was demonstrated using a Macro-Fiber Composite (MFC) actuator developed by the NASA LaRC and US Army ARL. The test results indicate that the MFC actuator performed well before and after processing cycles. It reduced some residue compressive strain that in turn corrected very small shape distortion after each processing cycle. The integrated precision strain gages were detecting only a small flat shape imperfection indicating a good recoverability of original shape of the CHEM test structure.

glass transition temperature Tg↗

Charging/discharging behavior and mechanism of silicon quantum dots embedded in amorphous silicon carbide films

The charging/discharging behavior of Si quantum dots (QDs) embedded in amorphous silicon carbide (a-SiC{sub x}) was investigated based on the Al/insulating layer/Si QDs embedded in a-SiC{sub x}/SiO{sub 2}/p-Si (metal-insulator-quantum dots-oxide-silicon) multilayer structure by capacitance-voltage (C-V) and conductance-voltage (G-V) measurements. Transmission electron microscopy and Raman scattering spectroscopy measurements reveal the microstructure and distribution of Si QDs. The occurrence and shift of conductance peaks indicate the carrier transfer and the charging/discharging behavior of Si QDs. The multilayer structure shows a large memory window of 5.2 eV at ±8 V sweeping voltage. Analysis of the C-V and G-V results allows a quantification of the Coulomb charging energy and the trapped charge density associated with the charging/discharging behavior. It is found that the memory window is related to the size effect, and Si QDs with large size or low Coulomb charging energy can trap two or more electrons by changing the charging voltage. Meanwhile, the estimated lower potential barrier height between Si QD and a-SiC{sub x}, and the lower Coulomb charging energy of Si QDs could enhance the charging and discharging effect of Si QDs and lead to an enlarged memory window. Further studies of the charging/discharging mechanism of Si QDs embedded in a-SiC{sub x} can promote the application of Si QDs in low-power consumption semiconductor memory devices.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

Analog In-Memory Computing for the Synthetic Aperture Radar Polar Format Algorithm

As the utility of synthetic aperture radar (SAR) systems increases in autonomous vehicles, satellites, and other power- and space-constrained edge applications, there is a growing need for processors that can form SAR images at low power. In recent years, analog in-memory compute (AIMC) has shown immense promise for accelerating neural networks and other matrix-vector multiplication (MVM) heavy workloads at the edge. Here, in this work, we examine how the polar format algorithm (PFA), a popular SAR image formation algorithm, can be mapped to these AIMC systems. The PFA maps readily onto analog MVMs because it primarily consists of two linear operations: interpolation of frequency-domain data to a Cartesian grid, followed by a 2-D Fourier transform. This work presents two approaches to map the interpolation operation onto MVMs in analog hardware: a chirp transform and a modified form of sinc interpolation. These mappings introduce algorithmic errors, and their effect on the quality of SAR image formation is examined, both quantitatively and qualitatively. In addition, the impact of errors introduced by the analog hardware is explored to determine which approach is optimal under varying assumptions about the underlying analog memory devices and circuits.

Analog computing↗

pnnl/memgaze

MemGaze is a memory analysis toolset that combines high-resolution trace analysis and low overhead measurement, both with respect to time and space. It provides high-resolution by collecting world-level memory access traces, where the highest resolution supported is back-to-back sequences. It achieves low-overhead in space and time by leveraging sampling and various methods of hardware support for collecting traces. Its post-mortem trace processing provides multiresolution analysis for locations vs. operations; accesses vs. spatio-temporal reuse, and reuse (distance, rate, volume) vs. access patterns.

Central, PNNL Developer↗

Processor architecture and data buffering

A set of architectures from three major architecture families: stack, register, and memory-to-memory is discussed. It is shown that scalable architectures are not applicable for low-density technologies because they require at least 32 words of local memory. Software support is shown to be capable of bridging the performance gap between scalable and nonscalable architectures. A register architecture with 32 words of local memory allocated interprocedurally outperforms scalable architectures with equal sizes local memories and even some with larger size local memories. The performance advantage of unscalable architectures becomes significant when in addition to quality compile-time support, a small cache is added to an unscalable architecture. A 32-register architecture with 512 byte cache executes 20 percent less cycles when compared with an 8-set multiple overlapping set organization.

Mulder, Hans↗