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At least 289 records · Page 16

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NASA NTRS1980

Acceptable testing of VLSI components which contain error correctors

If a VLSI chip is partitioned into functional units (FU's) and redundant FU's are added, error correcting codes may be employed to increase the yield and/or reliability of the chip. Acceptable testing is defined to be testing the chip with the error corrector functioning, thus obtaining the maximum increase in yield afforded by the error correction. The acceptable testing theorem shows that the use of coding and error correction in conjunction with acceptable testing can significantly increase the yield of VLSI chips without seriously compromising their reliability.

Cliff, R. A.↗

DOE OSTI2026

Composite-dimensional topological codes with boundaries and defects

We introduce new algorithms and provide example constructions of stabilizer models for the gapped boundaries, domain walls, and 0D defects of Abelian composite-dimensional twisted quantum doubles. Using the physically intuitive concept of condensation, our algorithm explicitly describes how to construct the boundary and domain-wall stabilizers starting from the bulk model. This extends the utility of Pauli stabilizer models in describing nontranslationally invariant topological orders with gapped boundaries. To highlight this utility, we provide a series of examples, including a new family of quantum error-correcting codes where the double of ℤ4 is coupled to instances of the double semion (DS) phase. We discuss the codes' utility in the burgeoning area of quantum error correction with an emphasis on the interplay between deconfined anyons, logical operators, error rates, and decoding. We also augment our construction, built using algorithmic tools to describe the properties of explicit stabilizer layouts at the microscopic lattice level, with dimensional counting arguments and macroscopic-level constructions building on pants decompositions. The latter outlines how such codes' representation and design can be automated. Our results are validated by a series of error-correcting threshold calculations comparing our codes' performance with that of standard surface codes. To do so, we introduce a composite-dimensional belief-propagation decoder with ordered statistics that utilizes combination sweeps. Going beyond our worked-out examples, we expect our explicit step-by-step algorithms to pave the path for higher-dimensional codes to be discovered and implemented in near-future architectures that take advantage of various hardware platforms.

Mousa, Mohamad [Purdue University]↗

NASA NTRS1988

Cyclic unequal error protection codes constructed from cyclic codes of composite length

The unequal error correction capabilities of binary cyclic codes of composite length are investigated. Under certain conditions, direct sums of concatenated codes have unequal error correction capabilities. By a modified Hartmann and Tzeng algorithm, it is shown that a binary cyclic code of composite length is equivalent to the direct sum of concatenated codes. With this, some binary cyclic unequal error protection (UEP) codes are constructed. Finally, two-level UEP cyclic direct-sum codes are presented which provide error correction capabilities higher than those guaranteed by the Blokh-Zyablov constructions.

Lin, Mao-Chao↗

NASA NTRS2005

Spaceborne Doppler Radar Measurements of Rainfall: Correction of Errors Induced by Pointing Uncertainties

In this paper a sea surface radar echo spectral analysis technique to correct for the rainfall velocity error caused by radar-pointing uncertainty is presented. The correction procedure is quite straightforward when the radar is observing a homogeneous rainfall field. When nonuniform beam filling (NUBF) occurs and attenuating frequencies are used, however, additional steps are necessary in order to correctly estimate the antenna-pointing direction. This new technique relies on the application of the combined frequency-time (CFT) algorithm to correct for uneven attenuation effects on the observed sea surface Doppler spectrum. The performance of this correction technique was evaluated by a Monte Carlo simulation of the Doppler precipitation radar backscatter from high-resolution 3D rain fields (either generated by a cloud resolving numerical model or retrieved from airborne radar measurements). The results show that the antenna-pointing-induced error can, indeed, be reduced by the proposed technique in order to achieve 1 m s(exp -1) accuracy on rainfall vertical velocity estimates.

remote sensing↗

DOE OSTI2016

The two-qubit amplitude damping channel: Characterization using quantum stabilizer codes

A protocol based on quantum error correction based characterization of quantum dynamics (QECCD) is developed for quantum process tomography on a two-qubit system interacting dissipatively with a vacuum bath. The method uses a 5-qubit quantum error correcting code that corrects arbitrary errors on the first two qubits, and also saturates the quantum Hamming bound. The dissipative interaction with a vacuum bath allows for both correlated and independent noise on the two-qubit system. We study the dependence of the degree of the correlation of the noise on evolution time and inter-qubit separation.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2016

Method, apparatus and system to compensate for drift by physically unclonable function circuitry

Techniques and mechanisms to detect and compensate for drift by a physically uncloneable function (PUF) circuit. In an embodiment, first state information is registered as reference information to be made available for subsequent evaluation of whether drift by PUF circuitry has occurred. The first state information is associated with a first error correction strength. The first state information is generated based on a first PUF value output by the PUF circuitry. In another embodiment, second state information is determined based on a second PUF value that is output by the PUF circuitry. An evaluation of whether drift has occurred is performed based on the first state information and the second state information, the evaluation including determining whether a threshold error correction strength is exceeded concurrent with a magnitude of error being less than the first error correction strength.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2013

An Investigation of Coupling of the Internal Kink Mode to Error Field Correction Coils in Tokamaks

The coupling of the internal kink to an external m/=1/1 pertubation if studied for profiles that are known to result in a saturated internal kink in the limit of a cylindrical tokamak. It is found from 3D equilibrium calculations that, for A 30 circular plasmas and A=3 elliptical shapes, this coupling of the boundary perturbation to the internal kink is strong; the amplitude of the m/n=1/1 structure at q=1 is large compared to the amplitude applied at the plasma boundary. It is proposed that this excitation, which could readily be applied with error field correction coils, be explored as a mechanism for controlling sawtooth amplitudes in high performance tokamak discharges. This saturated internal kink, resulting from small field errors in proposed as an explanation for the TEXTOR measurements of q0 and the distinction between sawtooth effects on the q-profile observed in TEXTOR and DIII-D.

q0↗

NASA NTRS1991

Asymmetric soft-error resistant memory

A memory system is provided, of the type that includes an error-correcting circuit that detects and corrects, that more efficiently utilizes the capacity of a memory formed of groups of binary cells whose states can be inadvertently switched by ionizing radiation. Each memory cell has an asymmetric geometry, so that ionizing radiation causes a significantly greater probability of errors in one state than in the opposite state (e.g., an erroneous switch from '1' to '0' is far more likely than a switch from '0' to'1'. An asymmetric error correcting coding circuit can be used with the asymmetric memory cells, which requires fewer bits than an efficient symmetric error correcting code.

Buehler, Martin G.↗

NASA NTRS1987

Performance analysis of a hybrid ARQ error control scheme for near earth satellite communications

A robust error control coding scheme is presented. The scheme is a cascaded forward error correction (FEC) scheme supported by parity retransmissions for further error correction in the erroneous data words. The error performance and throughput efficiency of the scheme are analyzed. Two specific schemes are proposed for NASA near earth satellite communications. It is shown that both schemes provide high reliability and throughput efficiency even for high channel bit error rates in the range of .002. The schemes are suitable for high data rate file transfer.

Lin, Shu↗

DOE OSTI2017

Identifying and Correcting Timing Errors at Seismic Stations in and around Iran

A fundamental component of seismic research is the use of phase arrival times, which are central to event location, Earth model development, and phase identification, as well as derived products. Hence, the accuracy of arrival times is crucial. However, errors in the timing of seismic waveforms and the arrival times based on them may go unidentified by the end user, particularly when seismic data are shared between different organizations. Here, we present a method used to analyze travel-time residuals for stations in and around Iran to identify time periods that are likely to contain station timing problems. For the 14 stations with the strongest evidence of timing errors lasting one month or longer, timing corrections are proposed to address the problematic time periods. Finally, two additional stations are identified with incorrect locations in the International Registry of Seismograph Stations, and one is found to have erroneously reported arrival times in 2011.

58 GEOSCIENCES↗

NASA NTRS1975

Performance of some block codes on a Gaussian channel

A technique proposed by Chase (1972) is used to evaluate the performance of several fairly long binary block codes on a wideband additive Gaussian channel. Considerations leading to the use of Chase's technique are discussed. Chase's concepts are first applied to the most powerful practical class of binary codes, the BCH codes with Berlekamp's (1972) decoding algorithm. Chase's algorithm is then described along with proposed selection of candidate codes. Results are presented of applying Chase's algorithm to four binary codes: (23, 12) Golay code, (32, 16) second-order Reed-Muller code, (63, 36) 5-error correcting BCH code, and (95, 39) 9-error correcting shortened BCH code. It is concluded that there are many block codes of length not exceeding 100 with extremely attractive maximum likelihood decoding performance on a Gaussian channel. BCH codes decoded via Berlekamp's binary decoding algorithm and Chase's idea are close to being practical competitors to short-constraint length convolutional codes with Viterbi decoding.

Baumert, L. D.↗

NASA NTRS1994

A terabyte linear tape recorder

A plan has been formulated and selected for a NASA Phase 2 SBIR award for using the VLBA tape recorder for recording general data. The VLBA tape recorder is a high-speed, high-density linear tape recorder developed for Very Long Baseline Interferometry (VLBI) which is presently capable of recording at rates up to 2 Gbit/sec and holding up to 1 Terabyte of data on one tape, using a special interface and not employing error correction. A general-purpose interface and error correction will be added so that the recorder can be used in other high-speed, high-capacity applications.

Webber, John C.↗

DOE OSTI2018

Method and apparatus for selective and power-aware memory error protection and memory management

A method for providing selective memory error protection responsive to a predictable failure notification associated with at least one portion of a memory in a computing system includes: obtaining an active error correcting code (ECC) configuration corresponding to the portion of the memory; determining whether the active ECC configuration is sufficient to correct at least one error in the portion of the memory affected by the predictable failure notification; when the active ECC configuration is insufficient to correct the error, determining whether data corruption can be tolerated by an application running on the computing system; when data corruption cannot be tolerated by the application, determining whether a stronger ECC level is available and, if a stronger ECC level is available, increasing a strength of the active ECC configuration; and when data corruption can be tolerated, performing page reassignment and aggregation of non-critical data.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2015

Detecting and correcting hard errors in a memory array

Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array.

96 KNOWLEDGE MANAGEMENT AND PRESERVATION↗

NASA NTRS2006

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 microns

Design options for decreasing the susceptibility of integrated circuits to Single Event Upset (SEU) fall into two categories: (1) increasing the critical charge to cause an upset at a particular node, and (2) employing redundancy to mask or correct errors. With decreasing device sizes on an Integrated Circuit (IC), the amount of charge required to represent a logic state has steadily reduced. Critical charge methods such as increasing drive strength or increasing the time required to change state as in capacitive or resistive hardening or delay based approaches extract a steadily increasing penalty as a percentage of device resources and performance. Dual redundancy is commonly assumed only to provide error detection with Triple Modular Redundancy (TMR) required for correction, but less well known methods employ dual redundancy to achieve full error correction by voting two inputs with a prior state to resolve ambiguity. This requires special circuits such as the Whitaker latch [1], or the guard-gate [2] which some of us have called a Transition AND Gate (TAG) [3]. A 2-input guard gate is shown in Figure 1. It is similar to a Muller Completion Element [4] and relies on capacitance at node "out" to retain the prior state when inputs disagree, while eliminating any output buffer which would be susceptible to radiation strikes. This paper experimentally compares delay based and dual rail flip-flop designs wherein both types of circuits employ guard-gates to optimize layout and performance, and draws conclusions about design criteria and suitability of each option. In both cases a design goal is protection against Single Event Transients (SET) in combinational logic as well as SEU in the storage elements. For the delay based design, it is also a goal to allow asynchronous clear or preset inputs on the storage elements, which are often not available in radiation tolerant designs.

Shuler, Robert L.↗

NASA NTRS1991

Techniques for containing error propagation in compression/decompression schemes

Data compression has the potential for increasing the risk of data loss. It can also cause bit error propagation, resulting in catastrophic failures. There are a number of approaches possible for containing error propagation due to data compression: (1) data retransmission; (2) data interpolation; (3) error containment; and (4) error correction. The most fruitful techniques will be ones where error containment and error correction are integrated with data compression to provide optimal performance for both. The error containment characteristics of existing compression schemes should be analyzed for their behavior under different data and error conditions. The error tolerance requirements of different data sets need to be understood, so guidelines can then be developed for matching error requirements to suitable compression algorithms.

Kobler, Ben↗

NASA NTRS1989

Method for detection and correction of errors in speech pitch period estimates

A method of detecting and correcting received values of a pitch period estimate of a speech signal for use in a speech coder or the like. An average is calculated of the nonzero values of received pitch period estimate since the previous reset. If a current pitch period estimate is within a range of 0.75 to 1.25 times the average, it is assumed correct, while if not, a correction process is carried out. If correction is required successively for more than a preset number of times, which will most likely occur when the speaker changes, the average is discarded and a new average calculated.

Bhaskar, Udaya↗

DOE OSTI2025

Mitigating cosmic-ray-like correlated events with a modular quantum processor

Quantum processors based on superconducting qubits are being scaled to larger qubit numbers, enabling the implementation of small-scale quantum error-correction codes. However, catastrophic chip-scale correlated errors have been observed in these processors, attributed to, e.g., cosmic ray impacts, which challenge conventional error-correction codes such as the surface code. These events are characterized by a temporary but pronounced suppression of the qubit-energy relaxation times. Here, in this study, we explore the potential for modular quantum computing architectures to mitigate such correlated energy decay events. We measure cosmic-ray-like events in a quantum processor comprising a motherboard and two flip-chip bonded daughterboard modules, each module containing two superconducting qubits. We monitor the appearance of correlated qubit decay events within a single module and across the physically separated modules. We find that while decay events within one module are strongly correlated (over 85%), events in separate modules only display approximately 2% correlations. We also report coincident decay events in the motherboard and in either of the two daughterboard modules, providing further insight into the nature of these decay events. These results suggest that modular architectures, combined with bespoke errorcorrection codes, offer a promising approach for protecting future quantum processors from chip-scale correlated errors.

Wu, Xuntao [Univ. of Chicago, IL (United States)] ↗