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NASA NTRS1995

Efficient finite element simulation of slot spirals, slot radomes and microwave structures

This progress report contains the following two documents: (1) 'Efficient Finite Element Simulation of Slot Antennas using Prismatic Elements' - A hybrid finite element-boundary integral (FE-BI) simulation technique is discussed to treat narrow slot antennas etched on a planar platform. Specifically, the prismatic elements are used to reduce the redundant sampling rates and ease the mesh generation process. Numerical results for an antenna slot and frequency selective surfaces are presented to demonstrate the validity and capability of the technique; and (2) 'Application and Design Guidelines of the PML Absorber for Finite Element Simulations of Microwave Packages' - The recently introduced perfectly matched layer (PML) uniaxial absorber for frequency domain finite element simulations has several advantages. In this paper we present the application of PML for microwave circuit simulations along with design guidelines to obtain a desired level of absorption. Different feeding techniques are also investigated for improved accuracy.

Gong, J.↗

NASA NTRS2003

High-Performance Solid-State W-Band Power Amplifiers

The figure shows one of four solid-state power amplifiers, each capable of generating an output power greater than or equal to 240 mW over one of four overlapping frequency bands from 71 to 106 GHz. (The bands are 71 to 84, 80 to 92, 88 to 99, and 89 to 106 GHz.) The amplifiers are designed for optimum performance at a temperature of 130 K. These amplifiers were developed specifically for incorporation into frequency-multiplier chains in local oscillators in a low-noise, far-infrared receiving instrument to be launched into outer space to make astrophysical observations. The designs of these amplifiers may also be of interest to designers and manufacturers of terrestrial W-band communication and radar systems. Each amplifier includes a set of six high-electron-mobility transistor (HEMT) GaAs monolithic microwave integrated-circuit (MMIC) chips, microstrip cavities, and other components packaged in a housing made from A-40 silicon-aluminum alloy. This alloy was chosen because, for the original intended spacecraft application, it offers an acceptable compromise among the partially competing requirements for high thermal conductivity, low mass, and low thermal expansion. Problems that were solved in designing the amplifiers included designing connectors and packages to fit the available space; designing microstrip signal-power splitters and combiners; matching of impedances across the frequency bands; matching of the electrical characteristics of those chips installed in parallel power-combining arms; control and levelling of output power across the bands; and designing the MMICs, microstrips, and microstrip cavities to suppress tendencies toward oscillation in several modes, both inside and outside the desired frequency bands.

Gaier, Todd↗

NASA NTRS2013

Fast, Large-Area, Wide-Bandgap UV Photodetector for Cherenkov Light Detection

Due to limited resources available for power and space for payloads, miniaturizing and integrating instrumentation is a high priority for addressing the challenges of manned and unmanned deep space missions to high Earth orbit (HEO), near Earth objects (NEOs), Lunar and Martian orbits and surfaces, and outer planetary systems, as well as improvements to high-altitude aircraft safety. New, robust, and compact detectors allow future instrumentation packages more options in satisfying specific mission goals. A solid-state ultraviolet (UV) detector was developed with a theoretical fast response time and large detection area intended for application to Cherenkov detectors. The detector is based on the wide-bandgap semiconductor zinc oxide (ZnO), which in a bridge circuit can detect small, fast pulses of UV light like those required for Cherenkov detectors. The goal is to replace the role of photomultiplier tubes in Cherenkov detectors with these solid-state devices, saving on size, weight, and required power. For improving detection geometry, a spherical detector to measure high atomic number and energy (HZE) ions from any direction has been patented as part of a larger space radiation detector system. The detector will require the development of solid-state UV photodetectors fast enough (2 ns response time or better) to detect the shockwave of Cherenkov light emitted as the ions pass through a quartz, sapphire, or acrylic ball. The detector must be small enough to fit in the detector system structure, but have an active area large enough to capture enough Cherenkov light from the sphere. The detector is fabricated on bulk single-crystal undoped ZnO. Inter - digitated finger electrodes and contact pads are patterned via photolithography, and formed by sputtered metal of silver, platinum, or other high-conductivity metal.

Wrbanek, John D.↗

DOE OSTI2021

Room-temperature single-photon emitters in silicon nitride

Single-photon emitters are essential in enabling several emerging applications in quantum information technology, quantum sensing, and quantum communication. Scalable photonic platforms capable of hosting intrinsic or embedded sources of single-photon emission are of particular interest for the realization of integrated quantum photonic circuits. Here, we report on the observation of room-temperature single-photon emitters in silicon nitride (SiN) films grown on silicon dioxide substrates. Photophysical analysis reveals bright (>10 5 counts/s), stable, linearly polarized, and pure quantum emitters in SiN films with a second-order autocorrelation function value at zero time delay g (2) (0) below 0.2 at room temperature. We suggest that the emission originates from a specific defect center in SiN because of the narrow wavelength distribution of the observed luminescence peak. Single-photon emitters in SiN have the potential to enable direct, scalable, and low-loss integration of quantum light sources with a well-established photonic on-chip platform.

42 ENGINEERING↗

DOE OSTI2022

Radiation-Hardened GaN-Based Wireless Communications Architectures for Terrestrial Nuclear Reactor Sensing and Instrumentation

Wireless technologies have become increasingly common in applications, ranging from close proximity inductive communication links in medical devices to short-range Bluetooth and WiFi communications and longer-range cellular communications. Nonetheless, these technologies are unsuitable for use in or around nuclear reactors due to the extreme radiation and temperatures inherent in these environments and their associated significant degradative effects on electronics hardware. However, recent work in wide bandgap– based electronics has shown promise for gallium nitride (GaN) as an emerging technology for the realization of practical wireless communications systems for use in harsh environments. This report presents initial progress on the development of wireless communications architectures designed specifically for nuclear reactor application, based on inherently radiation-hardened (rad-hard) GaN technology. Prior work on rad-hard analog communications topologies is reviewed, and several digital modulation and encoding schemes that utilize GaN-based electronics devices are newly proposed for application in reactor environments. Continuous-time and discrete-time system simulations were performed, and results are presented for the preliminary transmitter and receiver designs, respectively. In addition, an overview of a software-defined radio testbed, designed for communications protocol development, is provided. Future work will focus on implementing candidate radiation-resistant wireless architectures using a research AlGaN/GaN high electron mobility transistor (HEMT) integrated circuit process, which is available at the Ohio State University, and irradiation studies will be carried out to assess the true potential of this technology for reactor application.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

NASA NTRS2010

Electrically Variable Resistive Memory Devices

Nonvolatile electronic memory devices that store data in the form of electrical- resistance values, and memory circuits based on such devices, have been invented. These devices and circuits exploit an electrically-variable-resistance phenomenon that occurs in thin films of certain oxides that exhibit the colossal magnetoresistive (CMR) effect. It is worth emphasizing that, as stated in the immediately preceding article, these devices function at room temperature and do not depend on externally applied magnetic fields. A device of this type is basically a thin film resistor: it consists of a thin film of a CMR material located between, and in contact with, two electrical conductors. The application of a short-duration, low-voltage current pulse via the terminals changes the electrical resistance of the film. The amount of the change in resistance depends on the size of the pulse. The direction of change (increase or decrease of resistance) depends on the polarity of the pulse. Hence, a datum can be written (or a prior datum overwritten) in the memory device by applying a pulse of size and polarity tailored to set the resistance at a value that represents a specific numerical value. To read the datum, one applies a smaller pulse - one that is large enough to enable accurate measurement of resistance, but small enough so as not to change the resistance. In writing, the resistance can be set to any value within the dynamic range of the CMR film. Typically, the value would be one of several discrete resistance values that represent logic levels or digits. Because the number of levels can exceed 2, a memory device of this type is not limited to binary data. Like other memory devices, devices of this type can be incorporated into a memory integrated circuit by laying them out on a substrate in rows and columns, along with row and column conductors for electrically addressing them individually or collectively.

Liu, Shangqing↗

NASA NTRSDate not supplied

Impact of Emerging Computing Architectures and Opportunities for Process Systems Engineering Applications

Moore’s “law” was the observation that the number of transistors in an integrated circuit doubled approximately every two years. This trend has distinctly failed to hold in recent years. The death of Moore’s law has left researchers and practitioners in the computational sciences searching for technologies to provide the speedups formerly supported by Moore’s law. Previously overlooked chip architectures and other computing technologies are now receiving more development resources. Critically, these technologies are gaining more mature software support, opening their adoption by researchers in algorithms and applications. In this article, we review some of these computing technologies, their relationship with various algorithms and applications, and their potential benefits (or pitfalls). We close with recommendations for future work by the process systems engineering community specifically.

Emerging hardware↗

NASA NTRS2005

In Situ Electrochemical Deposition of Microscopic Wires

A method of fabrication of wires having micron and submicron dimensions is built around electrochemical deposition of the wires in their final positions between electrodes in integrated circuits or other devices in which the wires are to be used. Heretofore, nanowires have been fabricated by a variety of techniques characterized by low degrees of controllability and low throughput rates, and it has been necessary to align and electrically connect the wires in their final positions by use of sophisticated equipment in expensive and tedious post-growth assembly processes. The present method is more economical, offers higher yields, enables control of wire widths, and eliminates the need for post-growth assembly. The wires fabricated by this method could be used as simple electrical conductors or as transducers in sensors. Depending upon electrodeposition conditions and the compositions of the electroplating solutions in specific applications, the wires could be made of metals, alloys, metal oxides, semiconductors, or electrically conductive polymers. In this method, one uses fabrication processes that are standard in the semiconductor industry. These include cleaning, dry etching, low-pressure chemical vapor deposition, lithography, dielectric deposition, electron-beam lithography, and metallization processes as well as the electrochemical deposition process used to form the wires. In a typical case of fabrication of a circuit that includes electrodes between which microscopic wires are to be formed on a silicon substrate, the fabrication processes follow a standard sequence until just before the fabrication of the microscopic wires. Then, by use of a thermal SiO-deposition technique, the electrodes and the substrate surface areas in the gaps between them are covered with SiO. Next, the SiO is electron-beam patterned, then reactive-ion etched to form channels having specified widths (typically about 1 m or less) that define the widths of the wires to be formed. Drops of an electroplating solution are placed on the substrate in the regions containing the channels thus formed, then the wires are electrodeposited from the solution onto the exposed portions of the electrodes and into the channels. The electrodeposition is a room-temperature, atmospheric-pressure process. The figure shows an example of palladium wires that were electrodeposited into 1-mm-wide channels between gold electrodes.

Yun, Minhee↗

NASA NTRS2011

Qualification of emerging point-of-load regulators for next generation power systems

As demand for high-speed, on-board, digital-processing integrated circuits (ICs) on spacecraft increases (FPGAs and DSPs in particular), the need for the next generation point-of-load (POL) regulator becomes a prominent design issue. Shrinking process nodes have resulted in core rails dropping to values close to 1.0 V, drastically reducing margin to standard switching converters or regulators that power digital ICs. The objectives of this study are to first identify reliability issues or additional space reliability requirements that might not be addressed for commercial application of POL converters; second, to study the performances of existing or emerging POL converters (including linear regulators) within a practical two-stage power distribution architecture; and, finally, to identify points of failure at extreme temperatures (low and high) beyond specifications.

Leon, Rosa↗

NASA NTRS2009

System for Automated Calibration of Vector Modulators

Vector modulators are used to impose baseband modulation on RF signals, but non-ideal behavior limits the overall performance. The non-ideal behavior of the vector modulator is compensated using data collected with the use of an automated test system driven by a LabVIEW program that systematically applies thousands of control-signal values to the device under test and collects RF measurement data. The technology innovation automates several steps in the process. First, an automated test system, using computer controlled digital-to-analog converters (DACs) and a computer-controlled vector network analyzer (VNA) systematically can apply different I and Q signals (which represent the complex number by which the RF signal is multiplied) to the vector modulator under test (VMUT), while measuring the RF performance specifically, gain and phase. The automated test system uses the LabVIEW software to control the test equipment, collect the data, and write it to a file. The input to the Lab - VIEW program is either user-input for systematic variation, or is provided in a file containing specific test values that should be fed to the VMUT. The output file contains both the control signals and the measured data. The second step is to post-process the file to determine the correction functions as needed. The result of the entire process is a tabular representation, which allows translation of a desired I/Q value to the required analog control signals to produce a particular RF behavior. In some applications, corrected performance is needed only for a limited range. If the vector modulator is being used as a phase shifter, there is only a need to correct I and Q values that represent points on a circle, not the entire plane. This innovation has been used to calibrate 2-GHz MMIC (monolithic microwave integrated circuit) vector modulators in the High EIRP Cluster Array project (EIRP is high effective isotropic radiated power). These calibrations were then used to create correction tables to allow the commanding of the phase shift in each of four channels used as a phased array for beam steering of a Ka-band (32-GHz) signal. The system also was the basis of a breadboard electronic beam steering system. In this breadboard, the goal was not to make systematic measurements of the properties of a vector modulator, but to drive the breadboard with a series of test patterns varying in phase and amplitude. This is essentially the same calibration process, but with the difference that the data collection process is oriented toward collecting breadboard performance, rather than the measurement of output from a network analyzer.

Lux, James↗

NASA NTRS2003

Prototype Parts of a Digital Beam-Forming Wide-Band Receiver

Some prototype parts of a digital beamforming (DBF) receiver that would operate at multigigahertz carrier frequencies have been developed. The beam-forming algorithm in a DBF receiver processes signals from multiple antenna elements with appropriate time delays and weighting factors chosen to enhance the reception of signals from a specific direction while suppressing signals from other directions. Such a receiver would be used in the directional reception of weak wideband signals -- for example, spread-spectrum signals from a low-power transmitter on an Earth-orbiting spacecraft or other distant source. The prototype parts include superconducting components on integrated-circuit chips, and a multichip module (MCM), within which the chips are to be packaged and connected via special inter-chip-communication circuits. The design and the underlying principle of operation are based on the use of the rapid single-flux quantum (RSFQ) family of logic circuits to obtain the required processing speed and signal-to-noise ratio. RSFQ circuits are superconducting circuits that exploit the Josephson effect. They are well suited for this application, having been proven to perform well in some circuits at frequencies above 100 GHz. In order to maintain the superconductivity needed for proper functioning of the RSFQ circuits, the MCM must be kept in a cryogenic environment during operation.

Kaplan, Steven B.↗

NASA NTRS1997

PMMW Camera TRP

Passive millimeter wave (PMMW) sensors have the ability to see through fog, clouds, dust and sandstorms and thus have the potential to support all-weather operations, both military and commercial. Many of the applications, such as military transport or commercial aircraft landing, are technologically stressing in that they require imaging of a scene with a large field of view in real time and with high spatial resolution. The development of a low cost PMMW focal plane array camera is essential to obtain real-time video images to fulfill the above needs. The overall objective of this multi-year project (Phase 1) was to develop and demonstrate the capabilities of a W-band PMMW camera with a microwave/millimeter wave monolithic integrated circuit (MMIC) focal plane array (FPA) that can be manufactured at low cost for both military and commercial applications. This overall objective was met in July 1997 when the first video images from the camera were generated of an outdoor scene. In addition, our consortium partner McDonnell Douglas was to develop a real-time passive millimeter wave flight simulator to permit pilot evaluation of a PMMW-equipped aircraft in a landing scenario. A working version of this simulator was completed. This work was carried out under the DARPA-funded PMMW Camera Technology Reinvestment Project (TRP), also known as the PMMW Camera DARPA Joint Dual-Use Project. In this final report for the Phase 1 activities, a year by year description of what the specific objectives were, the approaches taken, and the progress made is presented, followed by a description of the validation and imaging test results obtained in 1997.

Source record↗

NASA NTRS2012

Cryogenic Applications of Commercial Electronic Components

We have developed a range of techniques useful for constructing analog and digital circuits for operation in a liquid Helium environment (4.2K), using commercially available low power components. The challenges encountered in designing cryogenic electronics include finding components that can function usefully in the cold and possess low enough power dissipation so as not to heat the systems they are designed to measure. From design, test, and integration perspectives it is useful for components to operate similarly at room and cryogenic temperatures; however this is not a necessity. Some of the circuits presented here have been used successfully in the MUSTANG and in the GISMO camera to build a complete digital to analog multiplexer (which will be referred to as the Cryogenic Address Driver board). Many of the circuit elements described are of a more general nature rather than specific to the Cryogenic Address Driver board, and were studied as a part of a more comprehensive approach to addressing a larger set of cryogenic electronic needs.

Buchanan, Ernest D.↗

NASA NTRS1999

The Biolink Implantable Telemetry System

Most biotelemetry applications deal with the moderated data rates of biological signals. Few people have studied the problem of transcutaneous data transmission at the rates required by NASA's Life Sciences-Advanced BioTelemetry System (LS-ABTS). Implanted telemetry eliminate the problems associated with wire breaking the skin, and permits experiments with awake and unrestrained subjects. Our goal is to build a low-power 174-216MHz Radio Frequency (RF) transmitter suitable for short range biosensor and implantable use. The BioLink Implantable Telemetry System (BITS) is composed of three major units: an Analog Data Module (ADM), a Telemetry Transmitter Module (TTM), and a Command Receiver Module (CRM). BioLink incorporates novel low-power techniques to implement a monolithic digital RF transmitter operating at 100kbps, using quadrature phase shift keying (QPSK) modulation in the 174-216MHz ISM band. As the ADM will be specific for each application, we focused on solving the problems associated with a monolithic implementation of the TTM and CRM, and this is the emphasis of this report. A system architecture based on a Frequency-Locked Loop (FLL) Frequency Synthesizer is presented, and a novel differential frequency that eliminates the need for a frequency divider is also shown. A self sizing phase modulation scheme suitable for low power implementation was also developed. A full system-level simulation of the FLL was performed and loop filter parameters were determined. The implantable antenna has been designed, simulated and constructed. An implant package compatible with the ABTS requirements is also being proposed. Extensive work performed at 200MHz in 0.5um complementary metal oxide semiconductors (CMOS) showed the feasibility of integrating the RF transmitter circuits in a single chip. The Hajimiri phase noise model was used to optimize the Voltage Controlled Oscillator (VCO) for minimum power consumption. Two test chips were fabricated in a 0.5pm, 3V CMOS process. Measured phase noise for a 1.5mW, 200MHz ring oscillator VCO is -80dBc/Hz at 100KHZ offset, showing good agreement with the theory. We also propose a novel superregenerative receiver architecture for implementing the command receiver. The superregenerative receiver's simplicity, low cost, and low power consumption has made it the receiver of choice for short-distance data communications, remote control and home automation. We present the design of a superregenerative AM receiver implemented in a 0.5um CMOS technology that operates at 433.92MHz and dissipates only 300uW. Further work entails detailed transistor-level design of the FLL and superregenerative receiver and a monolithic implementation of an implantable transceiver in 0.5um CMOS technology.

Betancourt-Zamora, Rafael J.↗

NASA NTRS2023

The Impact of Soft Magnetic Materials in Electrified Aircraft Applications

Electrical systems with high power and high power density are integral to many aerospace and energy applications. These systems, enabled by power electronics with wide bandgap semiconductor devices, require management of both efficiency/thermal aspects and electromagnetic interference that are problems specific to high power and high frequency applications, respectively. In addition to advanced active components, these applications also require passive components (inductors, capacitors, conductors) capable of operation under challenging conditions. This work surveys the state of the art of magnetic components and soft magnetic materials used as inductive cores. The wide variety of motor and converter topologies translates to a variety of requirements in the magnetics including mechanical properties, permeabilities, and frequency response. The scaling impact of material properties will be surveyed with respect to component performance and sizing, using both data from experiment and the published literature. Variations on simulations, both in lumped circuits and finite element models, will also be discussed as these are important aspects of the design phase of modern power electronics.

Alex Leary↗

NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗

NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

High temperature↗

NASA NTRS2000

A Boundary Scan Test Vehicle for Direct Chip Attach Testing

To facilitate the new faster, better and cheaper spacecraft designs, smaller more mass efficient avionics and instruments are using higher density electronic packaging technologies such as direct chip attach (DCA). For space flight applications, these technologies need to have demonstrated reliability and reasonably well defined fabrication and assembly processes before they will be accepted as baseline designs in new missions. As electronics shrink in size, not only can repair be more difficult, but 49 probing" circuitry can be very risky and it becomes increasingly more difficult to identify the specific source of a problem. To test and monitor these new technologies, the Direct Chip Attach Task, under NASA's Electronic Parts and Packaging Program (NEPP), chose the test methodology of boundary scan testing. The boundary scan methodology was developed for interconnect integrity and functional testing at hard to access electrical nodes. With boundary scan testing, active devices are used and failures can be identified to the specific device and lead. This technology permits the incorporation of "built in test" into almost any circuit and thus gives detailed test access to the highly integrated electronic assemblies. This presentation will describe boundary scan, discuss the development of the boundary scan test vehicle for DCA and current plans for testing of direct chip attach configurations.

Parsons, Heather A.↗