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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 289 records · Page 16
All sourcesNASA NTRSDOE OSTI
NASA NTRS1979

A model for testing centerfinding algorithms for automated optical navigation

An efficient software simulation of the imaging process for optical navigation is presented, illustrating results using simple examples. The problems of image definition and optical system modeling, including ideal image containing features and realistic models of optical filtering performed by the entire camera system, are examined. A digital signal processing technique is applied to the problem of developing methods of automated optical navigation and the subsequent mathematical formulation is presented. Specific objectives such as an analysis of the effects of camera defocusing on centerfinding of planar targets, addition of noise filtering to the algorithm, and implementation of multiple frame capability were investigated.

Griffin, M. D.↗
NASA NTRS1982

Chip level simulation of fault tolerant computers

Chip-level modeling techniques in the evaluation of fault tolerant systems were researched. A fault tolerant computer was modeled. An efficient approach to functional fault simulation was developed. Simulation software was also developed.

Armstrong, J. R.↗
NASA NTRS1982

Advanced reliability modeling of fault-tolerant computer-based systems

Two methodologies for the reliability assessment of fault tolerant digital computer based systems are discussed. The computer-aided reliability estimation 3 (CARE 3) and gate logic software simulation (GLOSS) are assessment technologies that were developed to mitigate a serious weakness in the design and evaluation process of ultrareliable digital systems. The weak link is based on the unavailability of a sufficiently powerful modeling technique for comparing the stochastic attributes of one system against others. Some of the more interesting attributes are reliability, system survival, safety, and mission success.

Bavuso, S. J.↗
NASA NTRS1983

Potential of minicomputer/array-processor system for nonlinear finite-element analysis

The potential of using a minicomputer/array-processor system for the efficient solution of large-scale, nonlinear, finite-element problems is studied. A Prime 750 is used as the host computer, and a software simulator residing on the Prime is employed to assess the performance of the Floating Point Systems AP-120B array processor. Major hardware characteristics of the system such as virtual memory and parallel and pipeline processing are reviewed, and the interplay between various hardware components is examined. Effective use of the minicomputer/array-processor system for nonlinear analysis requires the following: (1) proper selection of the computational procedure and the capability to vectorize the numerical algorithms; (2) reduction of input-output operations; and (3) overlapping host and array-processor operations. A detailed discussion is given of techniques to accomplish each of these tasks. Two benchmark problems with 1715 and 3230 degrees of freedom, respectively, are selected to measure the anticipated gain in speed obtained by using the proposed algorithms on the array processor.

Strohkorb, G. A.↗
NASA NTRS1984

Test experience on an ultrareliable computer communication network

The dispersed sensor processing mesh (DSPM) is an experimental, ultra-reliable, fault-tolerant computer communications network that exhibits an organic-like ability to regenerate itself after suffering damage. The regeneration is accomplished by two routines - grow and repair. This paper discusses the DSPM concept for achieving fault tolerance and provides a brief description of the mechanization of both the experiment and the six-node experimental network. The main topic of this paper is the system performance of the growth algorithm contained in the grow routine. The characteristics imbued to DSPM by the growth algorithm are also discussed. Data from an experimental DSPM network and software simulation of larger DSPM-type networks are used to examine the inherent limitation on growth time by the growth algorithm and the relationship of growth time to network size and topology.

Abbott, L. W.↗
NASA NTRS1984

Flight Experiment Demonstration System (FEDS) functional description and interface document

This document presents a functional description of the Flight Experiment Demonstration System (FEDS) and of interfaces between FEDS and external hardware and software. FEDS is a modification of the Automated Orbit Determination System (AODS). FEDS has been developed to support a ground demonstration of microprocessor-based onboard orbit determination. This document provides an overview of the structure and logic of FEDS and details the various operational procedures to build and execute FEDS. It also documents a microprocessor interface between FEDS and a TDRSS user transponder and describes a software simulator of the interface used in the development and system testing of FEDS.

Belcher, R. C.↗
NASA NTRS1983

New results in fault latency modelling

The test design and results from assessment of the performance of the self-test program and the extent of fault latency in a redundant flight control system (FCS) are reported. Assembly language programming generated gate-level faults directed to every avionics component. Details of the fault-simulation software are described, noting the input needed to match the five control-surface parameters managed by the FCS. Most faults were immediately detected, and component-level faults, occurring at pins, were more easily noted than gate-level faults. The results indicated that a 200-word self-test program is sufficient to obtain a fault coverage of 85 percent. Minor hardware changes are required to reach levels over 90 percent.

Mcgough, J. G.↗
NASA NTRS1984

Test experience on an ultrareliable computer communication network

The dispersed sensor processing mesh (DSPM) is an experimental, ultrareliable, fault-tolerant computer communications network that exhibits an organic-like ability to regenerate itself after suffering damage. The regeneration is accomplished by two routines - grow and repair. This paper discusses the DSPM concept for achieving fault tolerance and provides a brief description of the mechanization of both the experiment and the six-node experimental network. The main topic of this paper is the system performance of the growth algorithm contained in the grow routine. The characteristics imbued to DSPM by the growth algorithm are also discussed. Data from an experimental DSPM network and software simulation of larger DSPM-type networks are used to examine the inherent limitation on growth time by the growth algorithm and the relationship of growth time to network size and topology.

Abbott, L. W.↗
NASA NTRS1986

Distributed synthetic aperture radar simulation

Synthetic aperture radar (SAR) depends primarily on attainable frequency resolution rather than on large physical size of the antenna array. The distributed architecture concept (DSAR) incorporates active elements (amplifiers) at or near the elemental radiators of the array. Since SAR's are expensive to build and expensive to test, a computer modeling approach is a feasible method of predicting the quality or nature of the SAR image from the proposed system parameters. The goal of this project is to produce a DSAR simulation software package. This report describes the progress made thus far and the work which remains to be done. Extensive work on this project had been done previously by two NASA contractors. The principal task remaining involved the creation of a suitable interface between these programs and the hardware and software available at the Johnson Space Center.

Bourgeois, B. A.↗
NASA NTRS1988

A Generalized Method for Automatic Downhand and Wirefeed Control of a Welding Robot and Positioner

A generalized method for controlling a six degree-of-freedom (DOF) robot and a two DOF positioner used for arc welding operations is described. The welding path is defined in the part reference frame, and robot/positioner joint angles of the equivalent eight DOF serial linkage are determined via an iterative solution. Three algorithms are presented: the first solution controls motion of the eight DOF mechanism such that proper torch motion is achieved while minimizing the sum-of-squares of joint displacements; the second algorithm adds two constraint equations to achieve torch control while maintaining part orientation so that welding occurs in the downhand position; and the third algorithm adds the ability to control the proper orientation of a wire feed mechanism used in gas tungsten arc (GTA) welding operations. A verification of these algorithms is given using ROBOSIM, a NASA developed computer graphic simulation software package design for robot systems development.

Fernandez, Ken↗
NASA NTRS1986

Laser Docking System Radar flight experiment

Flight experiments to verify the Laser Docking System Radar are discussed. The docking requirements are summarized, and the breadboarded hardware is described, emphasizing the two major scanning concepts being utilized: a mechanical scanning technique employing galvanometer beamsteerers and an electronic scanning technique using an image dissector. The software simulations used to apply hardware solutions to the docking requirements are briefly discussed, the tracking test bed is described, and the objectives of the flight experiment are reviewed.

Erwin, Harry O.↗
NASA NTRS1989

On testing VLSI chips for the big Viterbi decoder

A general technique that can be used in testing very large scale integrated (VLSI) chips for the Big Viterbi Decoder (BVD) system is described. The test technique is divided into functional testing and fault-coverage testing. The purpose of functional testing is to verify that the design works functionally. Functional test vectors are converted from outputs of software simulations which simulate the BVD functionally. Fault-coverage testing is used to detect and, in some cases, to locate faulty components caused by bad fabrication. This type of testing is useful in screening out bad chips. Finally, design for testability, which is included in the BVD VLSI chip design, is described in considerable detail. Both the observability and controllability of a VLSI chip are greatly enhanced by including the design for the testability feature.

Hsu, I. S.↗
NASA NTRS1988

Development of an automated checkout, service and maintenance system for a Space Station EVAS

The development of a new operational system for the Space Station will minimize the time normally spent on performing on-orbit checkout, servicing, and maintenance of an extravehicular activity system of the Space Station. This system, the Checkout, Servicing, and Maintenance System (COSM), is composed of interactive control software interfacing with software simulations of hardware components. The major elements covered in detail include the controller, the EMU simulator and the regenerative life support system. The operational requirements and interactions of the individual elements as well as the protocols are also discussed.

Abeles, Fred J.↗
NASA NTRS1989

GPS-based system for satellite tracking and geodesy

High-performance receivers and data processing systems developed for GPS are reviewed. The GPS Inferred Positioning System (GIPSY) and the Orbiter Analysis and Simulation Software (OASIS) are described. The OASIS software is used to assess GPS system performance using GIPSY for data processing. Consideration is given to parameter estimation for multiday arcs, orbit repeatability, orbit prediction, daily baseline repeatability, agreement with VLBI, and ambiguity resolution. Also, the dual-frequency Rogue receiver, which can track up to eight GPS satellites simultaneously, is discussed.

Bertiger, Willy I.↗
NASA NTRS1989

Determination of Earth orientation using the Global Positioning System

Modern spacecraft tracking and navigation require highly accurate Earth-orientation parameters. For near-real-time applications, errors in these quantities and their extrapolated values are a significant error source. A globally distributed network of high-precision receivers observing the full Global Positioning System (GPS) configuration of 18 or more satellites may be an efficient and economical method for the rapid determination of short-term variations in Earth orientation. A covariance analysis using the JPL Orbit Analysis and Simulation Software (OASIS) was performed to evaluate the errors associated with GPS measurements of Earth orientation. These GPS measurements appear to be highly competitive with those from other techniques and can potentially yield frequent and reliable centimeter-level Earth-orientation information while simultaneously allowing the oversubscribed Deep Space Network (DSN) antennas to be used more for direct project support.

Freedman, A. P.↗
NASA NTRS1991

SSSFD manipulator engineering using statistical experiment design techniques

The Satellite Servicer System Flight Demonstration (SSSFD) program is a series of Shuttle flights designed to verify major on-orbit satellite servicing capabilities, such as rendezvous and docking of free flyers, Orbital Replacement Unit (ORU) exchange, and fluid transfer. A major part of this system is the manipulator system that will perform the ORU exchange. The manipulator must possess adequate toolplate dexterity to maneuver a variety of EVA-type tools into position to interface with ORU fasteners, connectors, latches, and handles on the satellite, and to move workpieces and ORUs through 6 degree of freedom (dof) space from the Target Vehicle (TV) to the Support Module (SM) and back. Two cost efficient tools were combined to perform a study of robot manipulator design parameters. These tools are graphical computer simulations and Taguchi Design of Experiment methods. Using a graphics platform, an off-the-shelf robot simulation software package, and an experiment designed with Taguchi's approach, the sensitivities of various manipulator kinematic design parameters to performance characteristics are determined with minimal cost.

Barnes, John↗
NASA NTRS1991

Coding gains and error rates from the Big Viterbi Decoder

A prototype hardware Big Viterbi Decoder (BVD) was completed for an experiment with the Galileo Spacecraft. Searches for new convolutional codes, studies of Viterbi decoder hardware designs and architectures, mathematical formulations, and decompositions of the deBruijn graph into identical and hierarchical subgraphs, and very large scale integration (VLSI) chip design are just a few examples of tasks completed for this project. The BVD bit error rates (BER), measured from hardware and software simulations, are plotted as a function of bit signal to noise ratio E sub b/N sub 0 on the additive white Gaussian noise channel. Using the constraint length 15, rate 1/4, experimental convolutional code for the Galileo mission, the BVD gains 1.5 dB over the NASA standard (7,1/2) Maximum Likelihood Convolution Decoder (MCD) at a BER of 0.005. At this BER, the same gain results when the (255,233) NASA standard Reed-Solomon decoder is used, which yields a word error rate of 2.1 x 10(exp -8) and a BER of 1.4 x 10(exp -9). The (15, 1/6) code to be used by the Cometary Rendezvous Asteroid Flyby (CRAF)/Cassini Missions yields 1.7 dB of coding gain. These gains are measured with respect to symbols input to the BVD and increase with decreasing BER. Also, 8-bit input symbol quantization makes the BVD resistant to demodulated signal-level variations which may cause higher bandwidth than the NASA (7,1/2) code, these gains are offset by about 0.1 dB of expected additional receiver losses. Coding gains of several decibels are possible by compressing all spacecraft data.

Onyszchuk, I. M.↗
NASA NTRS1991

Testing interconnected VLSI circuits in the Big Viterbi Decoder

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Onyszchuk, I. M.↗