SEARCH · Engineering Papers

Results for “Read Only Memory”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 289 records · Page 16

All sources NASA NTRS DOE OSTI

NASA NTRS1986

Spaceborne optical disk controller development

The current status and potential applications of an optical-disk buffer (ODB) memory system being developed by an interagency consortium including NASA and the USAF are reviewed. The design goals for the ODB include usable capacity 1 Tb, maximum data rate 1.6 Gb/s, read error rate less than 10 to the -12th, time to initial access less than 100 ms, and unlimited read/write cycles. Present efforts focus on a brassboard ODB which employs 12 14-inch magnetooptic disks and 24 nine-diode read/write heads. A typical space application of an optical disk mass memory system (ODMMS) is discussed: as communications buffer, temporary storage, and/or multiuser I/O buffer for data management on the Space Station Earth Observing System. Environmental, operational, system-architecture, and functional-separation factors; critical design issues; and standardization questions for spaceborne ODMMSs are examined in detail.

Shull, Thomas A.↗

NASA NTRS2006

Radiation Tests on 2Gb NAND Flash Memories

We report on SEE and TID tests of highly scaled Samsung 2Gbits flash memories. Both in-situ and biased interval irradiations were used to characterize the response of the total accumulated dose failures. The radiation-induced failures can be categorized as followings: single event upset (SEU) read errors in biased and unbiased modes, write errors, and single-event-functional-interrupt (SEFI) failures.

NAND circuits↗

NASA NTRS2006

Simulating Responses of Gravitational-Wave Instrumentation

Synthetic LISA is a computer program for simulating the responses of the instrumentation of the NASA/ESA Laser Interferometer Space Antenna (LISA) mission, the purpose of which is to detect and study gravitational waves. Synthetic LISA generates synthetic time series of the LISA fundamental noises, as filtered through all the time-delay-interferometry (TDI) observables. (TDI is a method of canceling phase noise in temporally varying unequal-arm interferometers.) Synthetic LISA provides a streamlined module to compute the TDI responses to gravitational waves, according to a full model of TDI (including the motion of the LISA array and the temporal and directional dependence of the arm lengths). Synthetic LISA is written in the C++ programming language as a modular package that accommodates the addition of code for specific gravitational wave sources or for new noise models. In addition, time series for waves and noises can be easily loaded from disk storage or electronic memory. The package includes a Python-language interface for easy, interactive steering and scripting. Through Python, Synthetic LISA can read and write data files in Flexible Image Transport System (FITS), which is a commonly used astronomical data format.

Armstrong, John↗

NASA NTRS1996

The Global File System

The global file system (GFS) is a prototype design for a distributed file system in which cluster nodes physically share storage devices connected via a network-like fiber channel. Networks and network-attached storage devices have advanced to a level of performance and extensibility so that the previous disadvantages of shared disk architectures are no longer valid. This shared storage architecture attempts to exploit the sophistication of storage device technologies whereas a server architecture diminishes a device's role to that of a simple component. GFS distributes the file system responsibilities across processing nodes, storage across the devices, and file system resources across the entire storage pool. GFS caches data on the storage devices instead of the main memories of the machines. Consistency is established by using a locking mechanism maintained by the storage devices to facilitate atomic read-modify-write operations. The locking mechanism is being prototyped in the Silicon Graphics IRIX operating system and is accessed using standard Unix commands and modules.

Soltis, Steven R.↗

NASA NTRS2002

Focal plane infrared readout circuit with automatic background suppression

A circuit for reading out a signal from an infrared detector includes a current-mode background-signal subtracting circuit having a current memory which can be enabled to sample and store a dark level signal from the infrared detector during a calibration phase. The signal stored by the current memory is subtracted from a signal received from the infrared detector during an imaging phase. The circuit also includes a buffered direct injection input circuit and a differential voltage readout section. By performing most of the background signal estimation and subtraction in a current mode, a low gain can be provided by the buffered direct injection input circuit to keep the gain of the background signal relatively small, while a higher gain is provided by the differential voltage readout circuit. An array of such readout circuits can be used in an imager having an array of infrared detectors. The readout circuits can provide a high effective handling capacity.

Pain, Bedabrata↗

DOE OSTI2024

Electrically Controlled All-Antiferromagnetic Tunnel Junctions on Silicon with Large Room-Temperature Magnetoresistance

Antiferromagnetic (AFM) materials are a pathway to spintronic memory and computing devices with unprecedented speed, energy efficiency, and bit density. Realizing this potential requires AFM devices with simultaneous electrical writing and reading of information, which are also compatible with established silicon-based manufacturing. Recent experiments have shown tunneling magnetoresistance (TMR) readout in epitaxial AFM tunnel junctions. However, these TMR structures are not grown using a silicon-compatible deposition process, and controlling their AFM order required external magnetic fields. Here are shown three-terminal AFM tunnel junctions based on the noncollinear antiferromagnet PtMn 3 , sputter-deposited on silicon. The devices simultaneously exhibit electrical switching using electric currents, and electrical readout by a large room-temperature TMR effect. First-principles calculations explain the TMR in terms of the momentum-resolved spin-dependent tunneling conduction in tunnel junctions with noncollinear AFM electrodes.

36 MATERIALS SCIENCE↗

NASA NTRS2006

Holographic memory using beam steering

A method, apparatus, and system provide the ability for storing holograms at high speed. A single laser diode emits a collimated laser beam to both write to and read from a photorefractice crystal. One or more liquid crystal beam steering spatial light modulators (BSSLMs) or Micro-Electro-Mechanical Systems (MEMS) mirrors steer a reference beam, split from the collimated laser beam, at high speed to the photorefractive crystal.

Chao, Tien-Hsin↗

NASA NTRS2007

Holographic memory using beam steering

A method, apparatus, and system provide the ability for storing holograms at high speed. A single laser diode emits a collimated laser beam to both write to and read from a photorefractice crystal. One or more liquid crystal beam steering spatial light modulators (BSSLMs) steer a reference beam, split from the collimated laser beam, at high speed to the photorefractive crystal.

Chao, Tien-Hsin↗

DOE OSTI2021

Observation of current-induced switching in non-collinear antiferromagnetic IrMn 3 by differential voltage measurements

There is accelerating interest in developing memory devices using antiferromagnetic (AFM) materials, motivated by the possibility for electrically controlling AFM order via spin-orbit torques, and its read-out via magnetoresistive effects. Recent studies have shown, however, that high current densities create non-magnetic contributions to resistive switching signals in AFM/heavy metal (AFM/HM) bilayers, complicating their interpretation. Here we introduce an experimental protocol to unambiguously distinguish current-induced magnetic and nonmagnetic switching signals in AFM/HM structures, and demonstrate it in IrMn 3 /Pt devices. A six-terminal double-cross device is constructed, with an IrMn 3 pillar placed on one cross. The differential voltage is measured between the two crosses with and without IrMn 3 after each switching attempt. For a wide range of current densities, reversible switching is observed only when write currents pass through the cross with the IrMn 3 pillar, eliminating any possibility of non-magnetic switching artifacts. Micromagnetic simulations support our findings, indicating a complex domain-mediated switching process.

36 MATERIALS SCIENCE↗

NASA NTRS1979

Development of non-volatile semiconductor memory

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

Heikkila, W. W.↗

NASA NTRS2002

SEE and TID extension testing of the Xilinx XQR18V04 4Mbit radiation hardened configuration PROM

The XQR18V04 was evaluated for single event upset rates using proton and heavy ions. The PROM was demonstrated to be immune to latch-up, as well as to static upset in the flash memory cells, to an LET > 125 MeV/mg/cmz (effective). The PROM was also tested in a dynamic mode, which revealed three distinct error modes: Read Bit Errors, Address Errors, and a Single Event Functional Interrupt (SEW which affected the data output drivers. Saturation cross-sections, and onset thresholds, for these errorinodes were measured at the heavy ion facility at Texas A&M University, and the proton facility at UC Davis. Additional testing was performed at UC Davis and the Cobalt 60 source at McClellan Air Force Base to examine the effect to TID life as a function of power biasing. The PROM demonstrated a 100% improvement in total TID life with an 84% percent decrease in device usage.

FPGA Virtex II SEU↗

NASA NTRS2001

Integrated semiconductor-magnetic random access memory system

The present disclosure describes a non-volatile magnetic random access memory (RAM) system having a semiconductor control circuit and a magnetic array element. The integrated magnetic RAM system uses CMOS control circuit to read and write data magnetoresistively. The system provides a fast access, non-volatile, radiation hard, high density RAM for high speed computing.

Katti, Romney R.↗

NASA NTRS2001

MEMS Memory Elements

This paper presents a design example that illustrates the potential of microelectromechanical systems (MEMS) to perform the mechanical positioning required for addressing stored data and to enable an entirely new mechanism for reading and writing magnetic data. Specifically, MEMS sensors and actuators can be used to achieve active servo control of the separation between magnetic probe tips and a media surface with sub-nanometer accuracy. This allows mechanical position to be used to selectively write magnetic marks in a continuous thin-film magnetic media. In addition, MEMS sensors can be used to measure the separation between a magnetic probe tip and the media with a noise floor of roughly 22 picometers, allowing them to be used as position sensors in a magnetic force microscope (MFM) style data detection system.

Carley, L. Richard↗

DOE OSTI2021

Reliability processing of remote direct memory access

Methods and systems for monitoring remote transmissions of messages among a plurality of nodes are described. A processing element in a first node may allocate a sequence number to a request to read and/or update data in a second node. The processing element may be different from main processors of the first node. The processing element may send the message and the sequence number to the second node. The processing element may modify a status of the sequence number to an active state, indicating a transmission of the message is pending. The processing element may, in response to a response from the second node, modify the status of the sequence number to an inactive state, indicating a completed transmission of the message. The processing element may, in response to no response from the second node within a time period, resend the message and the sequence number to the second node.

Kumar, Sameer↗

DOE OSTI2025

Amorphous Indium Oxide Channel FEFETs With Write Voltage of 0.9 V and Endurance >10 12 for Refresh-Free Embedded Memory

This work presents, for the first time, a back-end-of-the-line (BEOL)-compatible W-doped indium oxide (IWO) ferroelectric field-effect transistor (FEFET) with a record-low operating voltage below 0.9 V and a write speed of 20 ns while achieving a transient read current window (CW) ratio ( I LVT /I HVT ) greater than 10 4 . The device also exhibits exceptional reliability characteristics such as: 1) measured bipolar write endurance up to 10 12 cycles; 2) a fast read speed of 50 ns; 3) read endurance surpassing 10 12 cycles; and 4) retention exceeding 10 4 s at 85 ∘ C. Furthermore, a physics-based numerical model has been developed to investigate the nanoscale characteristics of BEOL FEFET devices, leveraging nucleation-limited switching in HfO 2 ferroelectrics and dc characterization to extract material and channel parameters for accurate device simulation. The simulation uncovers the stochastic switching behavior of BEOL amorphous oxide semiconductor (AOS) FEFETs and demonstrates an intrinsic switching time as low as 1 ps, highlighting the potential of BEOL AOS FEFETs for ultrafast memory applications. These results establish AOS FEFETs as a compelling candidate for high-density embedded memory applications for last-level cache (LLC) (L4) in advanced CMOS technology nodes.

1-V ferroelectric field-effect transistor (FEFET)↗

NASA NTRS1972

Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model

The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.

Source record↗

NASA NTRS1997

Application-Controlled Demand Paging for Out-of-Core Visualization

In the area of scientific visualization, input data sets are often very large. In visualization of Computational Fluid Dynamics (CFD) in particular, input data sets today can surpass 100 Gbytes, and are expected to scale with the ability of supercomputers to generate them. Some visualization tools already partition large data sets into segments, and load appropriate segments as they are needed. However, this does not remove the problem for two reasons: 1) there are data sets for which even the individual segments are too large for the largest graphics workstations, 2) many practitioners do not have access to workstations with the memory capacity required to load even a segment, especially since the state-of-the-art visualization tools tend to be developed by researchers with much more powerful machines. When the size of the data that must be accessed is larger than the size of memory, some form of virtual memory is simply required. This may be by segmentation, paging, or by paged segments. In this paper we demonstrate that complete reliance on operating system virtual memory for out-of-core visualization leads to poor performance. We then describe a paged segment system that we have implemented, and explore the principles of memory management that can be employed by the application for out-of-core visualization. We show that application control over some of these can significantly improve performance. We show that sparse traversal can be exploited by loading only those data actually required. We show also that application control over data loading can be exploited by 1) loading data from alternative storage format (in particular 3-dimensional data stored in sub-cubes), 2) controlling the page size. Both of these techniques effectively reduce the total memory required by visualization at run-time. We also describe experiments we have done on remote out-of-core visualization (when pages are read by demand from remote disk) whose results are promising.

Cox, Michael↗

DOE OSTI2026

Memory-Aware External Facelist Calculation: A Data-Parallel Atomic Hash Counting Approach

Unstructured volumetric meshes serve as fundamental data representations in various scientific simulations and analyses. They play a crucial role in representing complex computational domains and are essential for important numerical techniques, such as finite element analysis. Whenever such a mesh is read from a file, streamed in-situ, or generated by algorithms, scientific visualization libraries rely on calculating the external surface of a geometry, named “external facelist”, to produce a polygonal mesh for rendering. Consequently, external facelist calculation has become one of the most widely used algorithms in the scientific visualization domain, necessitating optimal performance. In this paper, we explore relevant work on external facelist calculation algorithms in two common visualization libraries, VTK and Viskores, assess their performance and memory constraints, and introduce a novel memory-aware external facelist calculation algorithm employing an atomic hash counting approach. This algorithm fully leverages Viskores' data-parallel primitive operations, facilitating its execution across diverse many-core architectures. Our algorithm features the lowest memory footprint on the GPU and the second-lowest on the CPU among all evaluated methods, and it also delivers the fastest performance on both CPU and GPU. It has been made available under an open-source license in the VTK and Viskores visualization systems.

Tsalikis, Spiros [Kitware] (ORCID:0000000151137195↗