SMuRF Processor
This repository contains the SMuRF data processor. This processor receive each data frame from coming from the SMuRF FPGA, and average the data by a configurable number of samples.
Vasquez, Jesus↗
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Results for “PROCESSORS”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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An evaluation of MPI message rate on hybrid-core processors
Power and energy concerns are motivating chip manufacturers to consider future hybrid-core processor designs that may combine a small number of traditional cores optimized for single-thread performance with a large number of simpler cores optimized for throughput performance. This trend is likely to impact the way in which compute resources for network protocol processing functions are allocated and managed. In particular, the performance of MPI match processing is critical to achieving high message throughput. In this paper, we analyze the ability of simple and more complex cores to perform MPI matching operations for various scenarios in order to gain insight into how MPI implementations for future hybrid-core processors should be designed.
97 MATHEMATICS AND COMPUTING↗
Computational Particle Dynamic Simulations on Multicore Processors (CPDMu) Final Report Phase I
Statement of Problem - Department of Energy has many legacy codes for simulation of computational particle dynamics and computational fluid dynamics applications that are designed to run on sequential processors and are not easily parallelized. Emerging high-performance computing architectures employ massively parallel multicore architectures (e.g., graphics processing units) to increase throughput. Parallelization of legacy simulation codes is a high priority, to achieve compatibility, efficiency, accuracy, and extensibility. General Statement of Solution - A legacy simulation application designed for implementation on mainly-sequential processors has been represented as a graph G. Mathematical transformations, applied to G, produce a graph representation {und G} for a high-performance architecture. Key computational and data movement kernels of the application were analyzed/optimized for parallel execution using the mapping G {yields} {und G}, which can be performed semi-automatically. This approach is widely applicable to many types of high-performance computing systems, such as graphics processing units or clusters comprised of nodes that contain one or more such units. Phase I Accomplishments - Phase I research decomposed/profiled computational particle dynamics simulation code for rocket fuel combustion into low and high computational cost regions (respectively, mainly sequential and mainly parallel kernels), with analysis of space and time complexity. Using the research team's expertise in algorithm-to-architecture mappings, the high-cost kernels were transformed, parallelized, and implemented on Nvidia Fermi GPUs. Measured speedups (GPU with respect to single-core CPU) were approximately 20-32X for realistic model parameters, without final optimization. Error analysis showed no loss of computational accuracy. Commercial Applications and Other Benefits - The proposed research will constitute a breakthrough in solution of problems related to efficient parallel computation of particle and fluid dynamics simulations. These problems occur throughout DOE, military and commercial sectors: the potential payoff is high. We plan to license or sell the solution to contractors for military and domestic applications such as disaster simulation (aerodynamic and hydrodynamic), Government agencies (hydrological and environmental simulations), and medical applications (e.g., in tomographic image reconstruction). Keywords - High-performance Computing, Graphic Processing Unit, Fluid/Particle Simulation. Summary for Members of Congress - Department of Energy has many simulation codes that must compute faster, to be effective. The Phase I research parallelized particle/fluid simulations for rocket combustion, for high-performance computing systems.
97 MATHEMATICS AND COMPUTING↗
Evaluation of the Leon3 Soft-Core Processor Within a Xilinx Radiation-Hardened Field-Programmable Gate Array
The purpose of this document is to summarize the work done to evaluate the performance of the Leon3 soft-core processor in a radiation environment while instantiated in a radiation-hardened static random-access memory based field-programmable gate array. This evaluation will look at the differences between two soft-core processors: the open-source Leon3 core and the fault-tolerant Leon3 core. Radiation testing of these two cores was conducted at the Texas A&M University Cyclotron facility and Lawrence Berkeley National Laboratory. The results of these tests are included within the report along with designs intended to improve the mitigation of the open-source Leon3. The test setup used for evaluating both versions of the Leon3 is also included within this document.
97 MATHEMATICS AND COMPUTING↗
Image Matrix Processor for Volumetric Computations Final Report CRADA No. TSB-1148-95
The development of an Image Matrix Processor (IMP) was proposed that would provide an economical means to perform rapid ray-tracing processes on volume "Giga Voxel" data sets. This was a multi-phased project. The objective of the first phase of the IMP project was to evaluate the practicality of implementing a workstation-based Image Matrix Processor for use in volumetric reconstruction and rendering using hardware simulation techniques. Additionally, ARACOR and LLNL worked together to identify and pursue further funding sources to complete a second phase of this project.
97 MATHEMATICS AND COMPUTING↗
Efficient Scalable Tomography of Many-Qubit Quantum Processors
Quantum computing has the potential to realize powerful and revolutionary applications. A quantum computer can, in theory, solve certain problems exponentially faster than its classical counterparts. The current state of the art devices, however, are too small and noisy to practically realize this goal. An important tool for the advancement of quantum hardware, called model-based characterization, seeks to learn what types of noise are exhibited in a quantum processor. This technique, however, is notoriously difficult to scale up to even modest numbers of qubit, and has been limited to just 2 qubits until now. In this report, we present a novel method for performing model-based characterization, or tomography, on a many-qubit quantum processor. We consider up to 10 qubits, but the technique is expected to scale to even larger systems.
97 MATHEMATICS AND COMPUTING↗
Efficient, Predictive Tomography of Multi-Qubit Quantum Processors
After decades of R&D, quantum computers comprising more than 2 qubits are appearing. If this progress is to continue, the research community requires a capability for precise characterization (“tomography”) of these enlarged devices, which will enable benchmarking, improvement, and finally certification as mission-ready. As world leaders in characterization -- our gate set tomography (GST) method is the current state of the art – the project team is keenly aware that every existing protocol is either (1) catastrophically inefficient for more than 2 qubits, or (2) not rich enough to predict device behavior. GST scales poorly, while the popular randomized benchmarking technique only measures a single aggregated error probability. This project explored a new insight: that the combinatorial explosion plaguing standard GST could be avoided by using an ansatz of few-qubit interactions to build a complete, efficient model for multi-qubit errors. We developed this approach, prototyped it, and tested it on a cutting-edge quantum processor developed by Rigetti Quantum Computing (RQC), a US-based startup. We implemented our new models within Sandia’s PyGSTi open-source code, and tested them experimentally on the RQC device by probing crosstalk. We found two major results: first, our schema worked and is viable for further development; second, while the Rigetti device is indeed a “real” 8-qubit quantum processor, its behavior fluctuated significantly over time while we were experimenting with it and this drift made it difficult to fit our models of crosstalk to the data.
97 MATHEMATICS AND COMPUTING↗
A conceptual, parallel operating data compression processor
Data compressor processor concept envisions a simplified system for telemetry communications. It is simultaneously a zero-order processor and a floating aperture, a variable aperture, and a binary integer aperture with a decoded buffet fullness counter.
Anderson, T. O.↗
Vehicle Structural Analysis: Pre and Post Processor Data Handling
Pre-processor, post-processor, and multiple level substructuring routines for data management in support of NASTRAN finite element structural analysis of spacecraft
Furuike, T.↗
Radio astronomy Explorer B antenna aspect processor
The antenna aspect system used on the Radio Astronomy Explorer B spacecraft is described. This system consists of two facsimile cameras, a data encoder, and a data processor. Emphasis is placed on the discussion of the data processor, which contains a data compressor and a source encoder. With this compression scheme a compression ratio of 8 is achieved on a typical line of camera data. These compressed data are then convolutionally encoded.
Miller, W. H.↗
Improved general-purpose namelist processor
Processor is written in FORTRAN with minimal machine-dependent coding, allowing easy conversion to various digital computers. It eliminates 19 continuation-card limit of current namelist processors and permits unlimited number of variables to be read in a single namelist declaration.
Wojtaszek, E. W.↗
Analysis of DuPont and Kodak duplicating films and chemistries in a Fultron spray processor
A test program was conducted with duPont duplicating film type SR 112 and SCOLOR developer and Kodak duplicating film types 2430, 2422, and FE 2628 (SO-467) and MX-641 developer to determine sensitometric and image quality characteristics of these materials when used with a fultron spray processor. The test results show that the SCOLOR developer foams excessively in the fultron processor when used with or without the addition of an antifoaming agent. The Kodak type FE 2628 film with MX-641 chemistry had the longest linear Log E range at a 1.0 gamma. Sensitometric curves and granularity traces for all film process combinations tested are included.
Weinstein, M. S.↗
Future applications of associative processor systems to operational KSC systems for optimizing cost and enhancing performance characteristics
The application of associative memory processor equipment to conventional host processors type systems is discussed. Efforts were made to demonstrate how such application relieves the task burden of conventional systems, and enhance system speed and efficiency. Data cover comparative theoretical performance analysis, demonstration of expanded growth capabilities, and demonstrations of actual hardware in simulated environment.
Perkinson, J. A.↗
An investigation of potential applications of OP-SAPS: Operational sampled analog processors
The impact of charge-coupled device (CCD) processors on future instrumentation was investigated. The CCD devices studied process sampled analog data and are referred to as OP-SAPS - operational sampled analog processors. Preliminary studies into various architectural configurations for systems composed of OP-SAPS show that they have potential in such diverse applications as pattern recognition and automatic control. It appears probable that OP-SAPS may be used to construct computing structures which can serve as special peripherals to large-scale computer complexes used in real time flight simulation. The research was limited to the following benchmark programs: (1) face recognition, (2) voice command and control, (3) terrain classification, and (4) terrain identification. A small amount of effort was spent on examining a method by which OP-SAPS may be used to decrease the limiting ground sampling distance encountered in remote sensing from satellites.
Parrish, E. A.↗
The MIDAS processor
The MIDAS (Multivariate Interactive Digital Analysis System) processor is a high-speed processor designed to process multispectral scanner data (from Landsat, EOS, aircraft, etc.) quickly and cost-effectively to meet the requirements of users of remote sensor data, especially from very large areas. MIDAS consists of a fast multipipeline preprocessor and classifier, an interactive color display and color printer, and a medium scale computer system for analysis and control. The system is designed to process data having as many as 16 spectral bands per picture element at rates of 200,000 picture elements per second into as many as 17 classes using a maximum likelihood decision rule.
Kriegler, F. J.↗
Measurement accuracy of flow velocity via a digital-frequency-counter laser velocimeter processor
The laser velocimeter (LV) technique has so far been successfully applied to many flow situations to obtain mean velocity and turbulence level measurements. The paper deals with a unique LV system employing a digital frequency counter for measurements of turbulence spectra within the objectives of achieving higher accuracies and a wider range of velocities than were possible by previous analog systems. Systematic analysis of the effects of LV system errors in the accuracy of the turbulence power spectral measurements is performed and shown to agree reasonably with the experimental LV spectra results. Sufficient understanding of the accuracy and limitations of the digital frequency counter LV spectral measurement system is obtained. Among the major system errors encountered in a typical digital frequency counter LV processor, the truncation error is regarded as the most serious source of error. The quantizing step size defined as the ratio of Doppler frequency to processor clock frequency is an important parameter in determining the dynamic range of a turbulence power spectrum.
Wang, J. C. F.↗
Formulation of detailed consumables management models for the development (preoperational) period of advanced space transportation system. Volume 5: Flight operations processor requirements
The functional requirements for the Flight Operations Processor are defined. The Flight Operations Processor is that element of the Consumables Management System providing support during the flight operations.
Zamora, M. A.↗
Formulation of consumables management models: Mission planning processor payload interface definition
Consumables models required for the mission planning and scheduling function are formulated. The relation of the models to prelaunch, onboard, ground support, and postmission functions for the space transportation systems is established. Analytical models consisting of an orbiter planning processor with consumables data base is developed. A method of recognizing potential constraint violations in both the planning and flight operations functions, and a flight data file storage/retrieval of information over an extended period which interfaces with a flight operations processor for monitoring of the actual flights is presented.
Torian, J. G.↗