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At least 289 records · Page 16

Formulation of consumables management models: Test plan for the mission planning processor working model

The test plan and test procedures to be used in the verification and validation of the software being implemented in the mission planning processor working model program are documented. The mission planning processor is a user oriented tool for consumables management and is part of the total consumables subsystem management concept. An overview of the working model is presented. Execution of the test plan will comprehensively exercise the working model software. An overview of the test plan, including a testing schedule, is presented along with the test plan for the unit, module, and system levels. The criteria used to validate the working model results for each consumables subsystem is discussed.

Connelly, L. C.↗

The application of charge-coupled device processors in automatic-control systems

The application of charge-coupled device (CCD) processors to automatic-control systems is suggested. CCD processors are a new form of semiconductor component with the unique ability to process sampled signals on an analog basis. Specific implementations of controllers are suggested for linear time-invariant, time-varying, and nonlinear systems. Typical processing time should be only a few microseconds. This form of technology may become competitive with microprocessors and minicomputers in addition to supplementing them.

Mcvey, E. S.↗

Use of a multi-look unfocussed SAR processor on spacecraft

Two methods of processing signals from a multi-look unfocussed synthetic-aperture radar are considered. A saving in the processor complexity is achieved in comparison to a fully focussed SAR system at the expense of slightly greater clutter levels and poorer along-track resolution. In addition, lower power consumption enables the unfocussed processor to increase the number of looks to compensate in part for the reduced resolution.

Fong, R. K. T.↗

MBASIC batch processor architectural overview

The MBASIC (TM) batch processor, a language translator designed to operate in the MBASIC (TM) environment is described. Features include: (1) a CONVERT TO BATCH command, usable from the ready mode; and (2) translation of the users program in stages through several levels of intermediate language and optimization. The processor is to be designed and implemented in both machine-independent and machine-dependent sections. The architecture is planned so that optimization processes are transparent to the rest of the system and need not be included in the first design implementation cycle.

Reynolds, S. M.↗

Multibeam single frequency synthetic aperture radar processor for imaging separate range swaths

A method and apparatus are described for single frequency multibeam imaging of multiple strips of range swath at high range intervals for those applications where it is desirable to cover a range swath much greater than is possible for a given interpulse interval. Data from a single frequency synthetic aperture radar (in which beam parameters are adjusted so that the return from each successive swath is received during successive interpulse periods) are separated in Dopple frequency for the return from each beam at the frequency plane of the processor. Alternatively, the image formed by each beam may be spatially separated in the azimuth direction and successively selected by positioning an appropriate slit in the recording plane of the processor.

Jain, A.↗

OPS MCC level B/C formulation requirements: Area targets and space volumes processor

The level B/C mathematical specifications for the area targets and space volumes processor (ATSVP) are described. The processor is designed to compute the acquisition-of-signal (AOS) and loss-of-signal (LOS) times for area targets and space volumes. The characteristics of the area targets and space volumes are given. The mathematical equations necessary to determine whether the spacecraft lies within the area target or space volume are given. These equations provide a detailed model of the target geometry. A semianalytical technique for predicting the AOS and LOS time periods is disucssed. This technique was designed to bound the actual visibility period using a simplified target geometry model and unperturbed orbital motion. Functional overview of the ATSVP is presented and it's detailed logic flow is described.

Bishop, M. J., Jr.↗

Reduced power processor requirements for the 30-cm diameter Hg ion thruster

An evaluation of simplifications for the thruster power processor interface for a 30 cm Hg ion thruster is presented. Tests on the engine, thruster control, and the power supplies are performed. Reduced power processors requirements are defined and the impact on thruster design, performance, and lifetime are assessed.

Rawlin, V. K.↗

A programmable power processor for a 25 kW power module

The paper presents the concept and major design problems of a programmable power processor for the 25 kW electrical power system for the Shuttle Orbiter. The load will be handled by three parallel power stages operated in phase sequence with each power transistor having its own commutating diode and filter inductor. The power stages will be run at a fixed frequency of 10 kHz with the 'on'-time variable up to 100%. The input filter bank in the breadboard programmable power processor is planned to be a series-parallel combination of tantalum cased tantalum wet-slug capacitors.

Kapustka, R. E.↗

User's guide: SPAR processor MN analysis of inelastic three-dimensional solids, part 2

A user's guide to the processor MN is presented. The processor MN is used to analyze systems in which some or all of the three dimensional elements have nonlinear stress-strain relations. Representations of nonlinear material behavior implemented into the system are provided including Von Mises yield criterion, the Prandtl-Reuss flow rule, and the mechanical sublayer method. The primary data sets used to represent the state of the system are presented.

Whetstone, W. D.↗

Detailed description of the HP-9825A HFRMP trajectory processor (TRAJ)

The computer code for the trajectory processor of the HP-9825A High Fidelity Relative Motion Program is described in detail. The processor is a 12-degrees-of-freedom trajectory integrator which can be used to generate digital and graphical data describing the relative motion of the Space Shuttle Orbiter and a free-flying cylindrical payload. Coding standards and flow charts are given and the computational logic is discussed.

Kindall, S. M.↗

HP-9825A HFRMP trajectory processor (#TRAJ), detailed description

The computer code for the trajectory processor (#TRAJ) of the high fidelity relative motion program is described. The #TRAJ processor is a 12-degrees-of-freedom trajectory integrator (6 degrees of freedom for each of two vehicles) which can be used to generate digital and graphical data describing the relative motion of the Space Shuttle Orbiter and a free-flying cylindrical payload. A listing of the code, coding standards and conventions, detailed flow charts, and discussions of the computational logic are included.

Kindall, S. M.↗

Advanced development of a programmable power processor

The need for the development of a multipurpose flexible programmable power processor (PPP) has increased significantly in recent years to reduce ever rising development costs. One of the program requirements the PPP specification will cover is the 25 kW power module power conversion needs. The 25 kW power module could support the Space Shuttle program during the 1980s and 1990s and could be the stepping stone to future large space programs. Trades that led to selection of a microprocessor controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Component selection and design considerations are also discussed.

Lukens, F. E.↗

An Imaging Infrared (IIR) seeker using a microprogrammed processor

A recently developed Imaging Infrared Seeker uses a microprogrammed processor to perform gimbal servo control and system interface while performing the seeker functions of automatic target detection, acquisition, and tracking. The automatic detection mode requires up to 80% of the available capability of a high performance microprogrammed processor. Although system complexity was increased significantly, this approach can be cost effective when the basic computation capacity is already available.

Richmond, K. V.↗

A high performance multiplier processor for use with aerospace microcomputers

An MC68000 based microcomputer including a hardware multiplier processor has been designed and prototyped for a reentry vehicle navigation and control application. In this paper, the microcomputer is discussed with emphasis on the multiplier processor architecture, software control and theory of operation.

Pierce, P. E.↗

Extended operating range of the 30-cm ion thruster with simplified power processor requirements

A two grid 30 cm diameter mercury ion thruster was operated with only six power supplies over the baseline J series thruster power throttle range with negligible impact on thruster performance. An analysis of the functional model power processor showed that the component mass and parts count could be reduced considerably and the electrical efficiency increased slightly by only replacing power supplies with relays. The input power, output thrust, and specific impulse of the thruster were then extended, still using six supplies, from 2660 watts, 0.13 newtons, and 2980 seconds to 9130 watts, 0.37 newtons, and 3820 seconds, respectively. Increases in thrust and power density enable reductions in the number of thrusters and power processors required for most missions. Preliminary assessments of the impact of thruster operation at increased thrust and power density on the discharge characteristics, performance, and lifetime of the thruster were also made.

Rawlin, V. K.↗

The massively parallel processor

Future sensor systems will utilize massively parallel computing systems for rapid analysis of two-dimensional data. The Goddard Space Flight Center has an ongoing program to develop these systems. A single-instruction multiple data computer known as the Massively Parallel Processor (MPP) is being fabricated for NASA by the Goodyear Aerospace Corporation. This processor contains 16,384 processing elements arranged in a 128 x 128 array. The MPP will be capable of adding more than 6 billion 8-bit numbers per second. Multiplication of eight-bit numbers can occur at a rate of 2 billion per second. Delivery of the MPP to Goddard Space Flight Center is scheduled for 1983.

Schaefer, D. H.↗

A floating-point/multiple-precision processor for airborne applications

A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86.

Yee, R.↗

Computer simulation of a space SAR using a range-sequential processor for soil moisture mapping

The ability of a spaceborne synthetic aperture radar (SAR) to detect soil moisture was evaluated by means of a computer simulation technique. The computer simulation package includes coherent processing of the SAR data using a range-sequential processor, which can be set up through hardware implementations, thereby reducing the amount of telemetry involved. With such a processing approach, it is possible to monitor the earth's surface on a continuous basis, since data storage requirements can be easily met through the use of currently available technology. The Development of the simulation package is described, followed by an examination of the application of the technique to actual environments. The results indicate that in estimating soil moisture content with a four-look processor, the difference between the assumed and estimated values of soil moisture is within + or - 20% of field capacity for 62% of the pixels for agricultural terrain and for 53% of the pixels for hilly terrain. The estimation accuracy for soil moisture may be improved by reducing the effect of fading through non-coherent averaging.

Fujita, M.↗