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At least 289 records · Page 16

Defect distribution near the surface of electron-irradiated silicon

The surface-defect distributions of electron-irradiated n-type silicon have been investigated using a transient capacitance technique. Schottky, p-n junction, and MOS structures were used in profiling the defect distributions. Surface depletions of defects observed were attributed to the vacancy distribution, but not that of oxygen, and other capture centers' distributions. The vacancy diffusion length at 300 K was estimated to be about 3-6 microns.

Wang, K. L.↗

Design, fabrication, and evaluation of charge-coupled devices with aluminum-anodized-aluminum gates

A 4-phase, 49 1/2 bit CCD shift register was designed and fabricated using two levels of aluminum metallization with anodic Al2O3 insulation separating the layers. Test circuitry was also designed and constructed. A numerical analysis of an MOS-RC transmission line was made and results are given to characterize performance for various conductivities. The electrical design of the CCD included a low-noise dual-gate input and a balanced floating diffusion output circuit. Metallization was accomplished both by low voltage DC sputtering and thermal evaporation. The audization was according to published procedures using a buffered tartaric acid bath. Approximately 20 wafers were processed with 50 complete chips per wafer. All devices failed by shorting between the metal levels at some point. Experimental procedures eliminated temperature effects from sintering and drying, anodic oxide thickness, edge effects, photoresist stripping procedures, and metallization techniques as the primary causes of failure. It was believed from a study of SEM images that protuberances (hillocks) grow up from the first level metal through the oxide either causing a direct short or producing a weak, highly stressed insulation point which fails at low voltage. The cause of these hillocks is unknown; however, they have been observed to grow during temperature excursions to 470 C.

Gassaway, J. D.↗

Device model for FETSIM circuit simulation program

A description of the MOS transistor used in the FETSIM analysis program is presented. CMOS/SOS device parameters are included. Typical device mobilities are given as well as the empirically determined constants necessary to model second-order effect conductance variations due to gate voltage and saturated drain voltage.

Ramondetta, P.↗

New processes and materials for ultraviolet detection with solid state devices

The three major effects that degrade external responsivity of silicon from the 1/lambda theoretical curve for a quantum detector are: surface reflectance, surface recombination, and junction depth. Since the p-n junction must be very shallow, problems relating to surface are further enhanced. MOS type of processing is necessary. HCl oxides and numerous acid clean-ups are utilized in order to obtain a contamination free surface with low Qss levels. Stringent process controls such as CV shifts, spreading resistance measurements, thickness monitoring etc., are used to analyze the surface contaminations, surface mobile charges, surface concentrations, junction depth, oxide thickness etc. Low surface concentrations of 10 to the 18th atoms/cu cm are achieved by low temperature boron nitride depositions. Shallow junction depths of the order of a few tenths of a micron are achieved by low temperature controlled diffusions. In order to improve breakdown characteristics of these shallow junction devices, field plate and deep diffused p(+) ring geometries are used.

Chopra, D.↗

Radiation hardened PMOS process with ion implanted threshold adjust

By including specific process modifications the effect of ion implantation on radiation hardness can be minimized and radiation hard ion implanted MOS circuits can be fabricated. The experimental procedure followed was to examine key processing steps (with respect to radiation hardness) on ion-implanted individual PMOS transistors. The individual transistors were evaluated by continuously monitoring the threshold voltage as the transistors were being irradiated. By comparing runs it was possible to deduce what is considered a radiation hard ion implanted process. Tests with a complex LSI PMOS IC processor chip containing over 2000 transistors and resistors were also conducted

Jhabvala, M.↗

Digital Image Display Control System, DIDCS

DIDCS is an interactive image display and manipulation system that is used for a variety of astronomical image reduction and analysis operations. The hardware system consists of a PDP 11/40 main frame with 32K of 16-bit core memory; 96K of 16-bit MOS memory; two 9 track 800 BPI tape drives; eight 2.5 million byte RKO5 type disk packs, three user terminals, and a COMTAL 8000-S display system which has sufficient memory to store and display three 512 x 512 x 8 bit images along with an overlay plane and function table for each image, a pseudo color table and the capability for displaying true color. The software system is based around the language FORTH, which will permit an open ended dictionary of user level words for image analyses and display. A description of the hardware and software systems will be presented along with examples of the types of astronomical research that are being performed. Also a short discussion of the commonality and exchange of this type of image analysis system will be given.

Fischel, D.↗

RAM-Based frame synchronizer

Frame synchronizer for serial telemetry is rapidly reconfigured for changing formats. Synchronizer generates signals marking data-word boundaries, beginning of each frame, and beginning of each paragraph. Also derived are search, check, and lock status signals. Existing unit is assembled from standard random-access memory elements and MOS and low-power-Schottky logic.

Niswander, J. K.↗

More-reliable SOS ion implantations

Conducting layer prevents static charges from accumulating during implantation of silicon-on-sapphire MOS structures. Either thick conducting film or thinner film transparent to ions is deposited prior to implantation, and gaps are etched in regions to be doped. Grounding path eliminates charge flow that damages film or cracks sapphire wafer. Prevention of charge buildup by simultaneously exposing structure to opposite charges requires equipment modifications less practical and more expensive than deposition of conducting layer.

Woo, D. S.↗

Four-quadrant CCD analog multiplier

Sequential processing technique improves accuracy when CCD-array signals are multiplied by weighting function to remove offsets. System uses two schemes to cancel undesired output contributions arising from prerequisite biases. First is spontaneous cancellation by multiple "nominally identical" devices; second is sequential cancellation where same devices are used repeatedly to form multiple products. Single device then successively subtracts products, eliminating effects of MOS-array threshold nonuniformities.

Brooks, C. W.↗

CADAT place-and-routine in two dimensions

CADAT place-and-route-in-two dimensions program (PR2D) is standard-cell automatic-layout program for generating large-scale-integrated/metal-oxidesemiconductor (LSI/MOS) arrays. PR2D translates logic designer's cell interconnection requirements into physically-defined MOS chip. PR2D reads input data, searches pin data file for data on each pattern type, generates placement of patterns, and interconnects patterns. As output, it generates artwork for layouts.

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Passivation layer for steel substrate of solar cell

Solar cell is fabricated on commerical sheet-steel substrate passivated with tungsten layer. Layer prevents constituents of steel from interacting with semiconductor materials in MOS thin-film solar cell. Thin plating of nickel on steel improves bonding of tungsten. Use of steel as substrate reduces materials cost of solar cell construction.

Stirn, R. J.↗

An introduction to the BANNING design automation system for shuttle microelectronic hardware development

The BANNING MOS design system is presented. It complements rather than supplant the normal design activities associated with the design and fabrication of low-power digital electronic equipment. BANNING is user-oriented and requires no programming experience to use effectively. It provides the user a simulation capability to aid in his circuit design and it eliminates most of the manual operations involved in the layout and artwork generation of integrated circuits. An example of its operation is given and some additional background reading is provided.

Mcgrady, W. J.↗

Studies of silicon p-n junction solar cells

To provide theoretical support for investigating different ways to obtain high open-circuit voltages in p-n junction silicon solar cells, an analytical treatment of heavily doped transparent-emitter devices is presented that includes the effects of bandgap narrowing, Fermi-Dirac statistics, a doping concentration gradient, and a finite surface recombination velocity at the emitter surface. Topics covered include: (1) experimental determination of bandgap narrowing in the emitter of silicon p-n junction devices; (2) heavily doped transparent regions in junction solar cells, diodes, and transistors; (3) high-low-emitter solar cell; (4) determination of lifetimes and recombination currents in p-n junction solar cells; (5) MOS and oxide-charged-induced BSF solar cells; and (6) design of high efficiency solar cells for space and terrestrial applications.

Neugroschel, A.↗

Crystal growth of device quality GaAs in space

The apparatus and techniques used in effort to determine the relationships between crystal growth and electronic properties are described with emphasis on electroepitaxy and melt-grown gallium aresenide crystal. Applications of deep level transient spectroscopy, derivative photocapitance spectroscopy, and SEM-cathodoluminescene in characterizing wide bandgap semiconductors; determining photoionization in MOS, Schottky barriers, and p-n junctions; and for identifying inhomogeneities are examined, as well as the compensation of indium phosphide.

Gatos, H. C.↗

A study of trends and techniques for space base electronics

A sputtering system was developed to deposit aluminum and aluminum alloys by the dc sputtering technique. This system is designed for a high level of cleanliness and for monitoring the deposition parameters during film preparation. This system is now ready for studying the deposition and annealing parameters upon double-level metal preparation. A technique recently applied for semiconductor analysis, the finite element method, was studied for use in the computer modeling of two dimensional MOS transistor structures. It was concluded that the method has not been sufficiently well developed for confident use at this time. An algorithm was developed for confident use at this time. An algorithm was developed for implementing a computer study which is based upon the finite difference method. The program which was developed was modified and used to calculate redistribution data for boron and phosphorous which had been predeposited by ion implantation with range and straggle conditions. Data were generated for 111 oriented SOS films with redistribution in N2, dry O2 and steam ambients.

Trotter, J. D.↗

Annual Conference on Nuclear and Space Radiation Effects, 16th, Santa Cruz, Calif., July 17-20, 1979, Proceedings

Papers are presented on the following topics: radiation effects in bipolar microcircuits; basic radiation mechanisms in materials and devices; energy deposition and dosimetry; and system responses from SGEMP, IEMP, and EMP. Also considered are basic processes in SGEMP and IEMP, radiation effects in MOS microcircuits, and space radiation effects and spacecraft charging.

Bombardt, J.↗

Trends and techniques for space base electronics

A system was developed for depositing aluminum and aluminum alloys by the D.C. sputtering technique. This system which was designed for a high level of cleanliness and ion monitoring the deposition parameters during film preparation is ready for studying the deposition and annealing parameters upon double level metal preparation. The finite element method was studied for use in the computer modeling of two dimensional MOS transistor structures. An algorithm was developed for implementing a computer study which is based upon the finite difference method. The program was modified and used to calculate redistribution data for boron and phosphorous which had been predeposited by ion implantation with range and straggle conditions typical of those used at MSFC. Data were generated for 111 oriented SOS films with redistribution in N2, dry O2 and steam ambients. Data are given showing both two dimensional effects and the evolution of the junction depth, sheet resistance and integrated dose with redistribution time.

Gassaway, J. D.↗

RAD hard PROM design study

The results of a preliminary study on the design of a radiation hardened fusible link programmable read-only memory (PROM) are presented. Various fuse technologies and the effects of radiation on MOS integrated circuits are surveyed. A set of design rules allowing the fabrication of a radiation hardened PROM using a Si-gate CMOS process is defined. A preliminary cell layout was completed and the programming concept defined. A block diagram is used to describe the circuit components required for a 4 K design. A design goal data sheet giving target values for the AC, DC, and radiation parameters of the circuit is presented.

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