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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 289 records · Page 16
All sourcesNASA NTRSDOE OSTI
DOE OSTI2013

Exploring Hardware Support For Scaling Irregular Applications on Multi-node Multi-core Architectures

With the recent emergence of large-scale knowledge dis- covery, data mining and social network analysis, irregular applications have gained renewed interest. Classic cache-based high-performance architectures do not provide optimal performances with such kind of workloads, mainly due to the very low spatial and temporal locality of the irregular control and memory access patterns. In this paper, we present a multi-node, multi-core, fine-grained multi-threaded shared-memory system architecture specifically designed for the execution of large-scale irregular applications, and built on top of three pillars, that we believe are fundamental to support these workloads. First, we offer transparent hardware support for Partitioned Global Address Space (PGAS) to provide a large globally-shared address space with no software library overhead. Second, we employ multi-threaded multi-core processing nodes to achieve the necessary latency tolerance required by accessing global memory, which potentially resides in a remote node. Finally, we devise hardware support for inter-thread synchronization on the whole global address space. We first model the performances by using an analytical model that takes into account the main architecture and application characteristics. We describe the hardware design of the proposed cus- tom architectural building blocks that provide support for the above- mentioned three pillars. Finally, we present a limited-scale evaluation of the system on a multi-board FPGA prototype with typical irregular kernels and benchmarks. The experimental evaluation demonstrates the architecture performance scalability for different configurations of the whole system.

FPGA↗
DOE OSTI2023

Hardware-based Advanced Electromagnetic Transient Simulation for A Large-Scale PV Plant in Real Time Digital Simulator

Power electronics-based resources, such as high-voltage direct current (HVdc) substations, photovoltaic (PV) plants, wind plants, electric vehicle charging stations, and energy storage systems, are increasingly being integrated within the power grid. Recently, multiple reports have emphasized the necessity for high-fidelity electromagnetic transient (EMT) simulations of these large-scale power electronics-based resources to accurately understand their behavior in power grids. However, performing hardware-based EMT simulations with high-fidelity models for such large power electronics systems is challenging due to the small time-step requirements and the involvement of a large number of states. This paper presents the implementation of hardware-based high-fidelity EMT dynamic model of a large-scale PV plant, accomplished through custom model development using the specific-C language in real-time digital simulator hardware (RTDS) and software (RSCAD).

Choi, Jongchan↗
DOE OSTI2020

Understanding the Interplay between Hardware Errors and User Job Characteristics on the Titan Supercomputer

Designing dependable supercomputers begins with an understanding of errors in real-world, large-scale systems. The Titan supercomputer at Oak Ridge National Laboratory provides a unique opportunity to investigate errors when an actual system is actively used by multiple concurrent users and workloads from diverse domains at varying scales. This study presents a thorough analysis of 6, 908, 497 hardware errors from 18, 688 compute nodes of Titan for 312, 215 user jobs over a 3-year time period. Through careful joining of two system logs – the Machine Check Architecture (MCA) log and the job scheduler log – we show the correlated pattern of hardware errors for each job and user, in addition to individual descriptive statistics of errors, jobs, and users. Since the majority of hardware errors are memory errors, this study also shows the importance of error correcting in memory systems.

Lim, Seung-Hwan↗
DOE OSTI2024

Hardware-in-the-Loop Testing of Wide-Area Damping Controller for Field Implementation in Large-scale Power Grid

In our previous work, an adaptive measurement-driven wide-area damping controller (WADC) for suppressing inter-area oscillations has been proposed and a hardware prototype was developed and validated through hardware-in-the-loop tests. As a continuation of the work, this paper introduces a WADC software prototype to handle the realistic challenges for field implementation in the control room of the power grid. The WADC software is developed and operated as an openPDC adapter with a graphical user interface (GUI) to monitor the WADC inputs and output, the communication delays and other variables. The software prototype has been fully tested through an enhanced hardware-in-the-loop (HIL) test setup. Its performance is verified under various realistic communication uncertainties, such as random time delays and data losses, with different communication protocols. The experiment results have proven the WADC software can deliver sufficient damping to suppress the targeted oscillation mode in handling various communication uncertainties for future field deployment.

Jia, Xinlan↗
DOE OSTI2020

Module-OT: A Hardware Security Module for Operational Technology

Increased penetration levels of renewable energy and other types of distributed energy resources (DERs) on the modern electric grid-combined with technological advancements for electric system monitoring and control-introduce new cyberattack vectors and increase the cyberattack surface of energy systems. According to the IEEE Std. 1547-2018, DERs must use Modbus, Distributed Network Protocol 3 (DNP3), or Smart Energy Profile 2.0 (SEP2) as their communication protocol. Previous research identified several vulnerabilities and security breaches in each one of these communication protocols; despite this, existing standards for DERs do not recommend cybersecurity measures. In order to reduce vulnerabilities in power distribution systems, this paper presents a novel open-source hardware security module that improves both information and operational security to better protect data and communications on the distribution grid. The security hardware is called “module for operational technology,” or simply Module-OT, and it has been validated and tested in an emulated distribution system application. Module-OT is integrated within a communication system in the transport layer of the Open Systems Interconnection (OSI) model. It improves system security through encryption, authentication, authorization, certificate management, and user access control. The main advancement of Module-OT is the addition of hardware cryptographic acceleration that improves the overall communication performance in terms of end-to-end latency.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2015

SU-E-T-404: Evaluation of the Effect of Spine Hardware for CyberKnife Spinal Stereotactic Radiosurgery

Purpose: Spine hardware made of high-Z materials such as titanium has the potential to affect the dose distribution around the metal rods in CyberKnife spinal stereotactic radiosurgery (SRS) treatments. The purpose of this work was to evaluate the magnitude of such effect retrospectively for clinical CyberKnife plans. Methods: The dose calculation was performed within the MultiPlan treatment planning system using the ray tracing (RT) and Monte Carlo (MC) method. A custom density model was created by extending the CT-to-Density table to titanium density of 4.5 g/cm3 with the CT number of 4095. To understand the dose perturbation caused by the titanium rod, a simple beam setup (7.5 mm IRIS collimator) was used to irradiate a mimic rod (5 mm) with overridden high density. Five patient spinal SRS cases were found chronologically from 2010 to 2015 in our institution. For each case, the hardware was contoured manually. The original plan was re-calculated using both RT and MC methods with and without rod density override without changing clinical beam parameters. Results: The simple beam irradiation shows that there is 10% dose increase at the interface because of electron backscattering and 7% decrease behind the rod because of photon attenuation. For actual clinical plans, the iso-dose lines and DVHs are almost identical (<2%) for calculations with and without density override for both RT and MC methods. However, there is a difference of more than 10% for D90 between RT and MC method. Conclusion: Although the dose perturbation around the metal rods can be as large as 10% for a single beam irradiation, for clinical treatments with complex beam composition the effect of spinal hardware to the PTV and spinal dose is minimal. As such, the MC dose algorithm without rod density override for CyberKnife spinal SRS is acceptable.

60 APPLIED LIFE SCIENCES↗
DOE OSTI2017

Hardware-Software Complex for Measurement of Energy and Angular Distributions of Charged Particles Formed in Nuclear Reactions

A hardware-software complex for measurement of energy and angular distributions of charged particles formed in nuclear reactions is presented. Hardware and software structures of the complex, the basic set of the modular nuclear-physical apparatus of a multichannel detecting system on the basis of ΔE–E telescopes of silicon detectors, and the hardware of experimental data collection, storage, and processing are presented and described.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2015

Efficient Execution of Recursive Programs on Commodity Vector Hardware

The pursuit of computational efficiency has led to the proliferation of throughput-oriented hardware, from GPUs to increasingly-wide vector units on commodity processors and accelerators. This hardware is designed to efficiently execute data-parallel computations in a vectorized manner. However, many algorithms are more naturally expressed as divide-and-conquer, recursive, task-parallel computations; in the absence of data parallelism, it seems that such algorithms are not well-suited to throughput-oriented architectures. This paper presents a set of novel code transformations that expose the data-parallelism latent in recursive, task-parallel programs. These transformations facilitate straightforward vectorization of task-parallel programs on commodity hardware. We also present scheduling policies that maintain high utilization of vector resources while limiting space usage. Across several task-parallel benchmarks, we demonstrate both efficient vector resource utilization and substantial speedup on chips using Intel's SSE4.2 vector units as well as accelerators using Intel's AVX512 units.

resursion↗
DOE OSTI2023

Hardware-Conscious Optimization of the Quantum Toffoli Gate

While quantum computing holds great potential in combinatorial optimization, electronic structure calculation, and number theory, the current era of quantum computing is limited by noisy hardware. Many quantum compilation approaches can mitigate the effects of imperfect hardware by optimizing quantum circuits for objectives such as critical path length. Few approaches consider quantum circuits in terms of the set of vendor-calibrated operations (i.e., native gates) available on target hardware. This manuscript expands the analytical and numerical approaches for optimizing quantum circuits at this abstraction level. We present a procedure for combining the strengths of analytical native gate-level optimization with numerical optimization. Although we focus on optimizing Toffoli gates on the IBMQ native gate set, the methods presented are generalizable to any gate and superconducting qubit architecture. Our optimized Toffoli gate implementation demonstrates an 18% reduction in infidelity compared with the canonical implementation as benchmarked on IBM Jakarta with quantum process tomography. Assuming the inclusion of multi-qubit cross-resonance (MCR) gates in the IBMQ native gate set, we produce Toffoli implementations with only six multi-qubit gates, a 25% reduction from the canonical eight multi-qubit implementations for linearly connected qubits.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Experiences Detecting Defective Hardware in Exascale Supercomputers

In May 2022, the newest supercomputer to top the TOP 500 list was Frontier at Oak Ridge National Laboratory, demonstrating the capability of computing more than 1.1 quintillion (1018) floating-point calculations every second. Driving this ground-breaking rate of computing is Frontier’s more than 37,000 graphics processing units (GPUs) and 9,408 central processing units (CPUs). In total, Frontier contains more than 60 million parts. At this scale, the smallest margin of error may generate hundreds of hardware errors across the system. These errors are capable of directly hindering world-class science performed on Frontier if not found. In this work, we describe and evaluate two strategies for finding hardware-level faults in Frontier’s 9,408 compute nodes. There are two strategies developed: the first uses the Slurm scheduler to scavenge available compute time to run the node screen, the second builds upon the lessons learned in the first strategy and enforces a weekly screen of each node. Using June 2023 as a case study, we find that the first scheduling strategy consumed more than ten times the resources as the second scheduling strategy, but successfully detected five hardware defects in Frontier. We summarize the lessons learned while developing and running a node screen on the world’s first exascale supercomputer.

Hagerty, Nick↗
DOE OSTI2015

HPC Programming on Intel Many-Integrated-Core Hardware with MAGMA Port to Xeon Phi

This paper presents the design and implementation of several fundamental dense linear algebra (DLA) algorithms for multicore with Intel Xeon Phi coprocessors. In particular, we consider algorithms for solving linear systems. Further, we give an overview of the MAGMA MIC library, an open source, high performance library, that incorporates the developments presented here and, more broadly, provides the DLA functionality equivalent to that of the popular LAPACK library while targeting heterogeneous architectures that feature a mix of multicore CPUs and coprocessors. The LAPACK-compliance simplifies the use of the MAGMA MIC library in applications, while providing them with portably performant DLA. High performance is obtained through the use of the high-performance BLAS, hardware-specific tuning, and a hybridization methodology whereby we split the algorithm into computational tasks of various granularities. Execution of those tasks is properly scheduled over the heterogeneous hardware by minimizing data movements and mapping algorithmic requirements to the architectural strengths of the various heterogeneous hardware components. Our methodology and programming techniques are incorporated into the MAGMA MIC API, which abstracts the application developer from the specifics of the Xeon Phi architecture and is therefore applicable to algorithms beyond the scope of DLA.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2020

Re-Envisioning RCx: Achieving Max Potential HVAC Controls Retrofits through Modernized BAS Hardware and Software

Most existing buildings have sub-optimal heating, ventilation, and air conditioning (HVAC) controls, resulting in wasted energy and occupant discomfort. Retro-commissioning (RCx) addresses many of these issues, but it is a lengthy and highly customized process. Limited capabilities of existing building automation system hardware restricts the scope of most RCx projects. Incentive programs consider building automation system (BAS) hardware retrofits to be high-capital investments and do not allow them in typical RCx programs. This paper describes work that the authors are leading to facilitate technical and market innovation in the BAS industry to unlock large savings in existing commercial buildings through deep retrofits of BAS hardware and software. California and New York research projects are demonstrating BAS retrofits leveraging the American Society of Heating, Refrigeration, and Air Conditioning Engineers’ (ASHRAE) new Guideline 36 high performance sequences of operation to achieve greater than 20 percent whole building energy savings, while saving costs and reducing risk through streamlined processes and standardization across BAS manufacturer product lines and across implementation practices. This paper describes market barriers that impede achieving deep savings from BAS retrofits in custom incentive and traditional RCx programs and presents a new maximum potential BAS retrofit model that addresses these barriers. The new model leverages the authors’ efforts in market enablement through open standards, BAS industry partnerships, and tools for cost-effective scaling that includes tools for project screening, savings calculations, and measurement and verification (M&V). This approach is widely applicable and will be ready for at-scale implementation within two years.

Paliaga, Gwelen↗
DOE OSTI2017

Hardware Acceleration of Adaptive Neural Algorithms.

As tradit ional numerical computing has faced challenges, researchers have turned towards alternative computing approaches to reduce power - per - computation metrics and improve algorithm performance. Here, we describe an approach towards non - conventional computing that strengthens the connection between machine learning and neuroscience concepts. The Hardware Acceleration of Adaptive Neural Algorithms (HAANA) project ha s develop ed neural machine learning algorithms and hardware for applications in image processing and cybersecurity. While machine learning methods are effective at extracting relevant features from many types of data, the effectiveness of these algorithms degrades when subjected to real - world conditions. Our team has generated novel neural - inspired approa ches to improve the resiliency and adaptability of machine learning algorithms. In addition, we have also designed and fabricated hardware architectures and microelectronic devices specifically tuned towards the training and inference operations of neural - inspired algorithms. Finally, our multi - scale simulation framework allows us to assess the impact of microelectronic device properties on algorithm performance.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2019

Hardware Evaluation Outreach: Application development Challenges Now and for the Exascale Era

The intent of this document is to assist the programmer in understanding details of contemporary and Exascale hardware system design and how these designs provide opportunities and place constraints on next-generation simulation software design. We attempt to clarify hardware organization and component details for our most current and Exascale systems to help program developers understand how software needs to change in order to take best advantage of the performance available. Exascale success is specifically defined for ECP as a 50x improvement over baseline in the aggregate "capability volume" on several KPP axes, of which raw floating point performance is only one, but also includes characteristics such as problem size, system memory size, node memory size, power, and efficiency. This multi-axis approach is particularly important to understand in the context of delivered improvements in real applications, since, for instance, the floating point computation may comprise less than 10% of the actual computational work required. Given the Exascale requirements and the constraints these requirements put on the performance expectations of fundamental system components, the programmer will be forced to re-think several application implementation details in order to achieve exaflop performance on these systems. The remainder of this document aims to present more detail on Exascale era system hardware and the specific areas that the programmer should address to extract performance from these systems. We attempt to give the programmer guidance at both a high- and low-level, providing some abstract suggestions on how to refactor codes given the expected system architectures and some low-level recommendations on how to implement these modifications. We also include a section on training resources that are helpful for both programmers that are just beginning to understand code modifications for contemporary and Exascale systems and for those that have done some refactoring and are now trying to extract maximal application performance from these systems.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Empirical Performance Analysis of HPC Applications with Portable Hardware Counter Metrics [Thesis]

In this dissertation, we demonstrate that it is possible to develop methods of empirical hardware-counter-based performance analysis for scientific applications running on diverse types of CPUs. Although hardware counters have been used in performance analysis for at least 30 years, the methods used are still limited to particular CPU vendors or even particular generations of CPUs from the same vendor. Our motivating hypothesis is that hardware counter-based measurements could be developed to provide consistent performance information on diverse CPU types. This dissertation proves the hypothesis was correct by demonstrating one such set of metrics.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Application of Quantum Machine Learning to High Energy Physics Analysis at LHC using IBM Quantum Computer Simulators and IBM Quantum Computer Hardware

Our group pioneers the use of Quantum Machine Learning (QML) on High Energy Physics analysis at LHC. We have successfully employed several QML classification algorithms in the ttH (Higgs production in association with a top quark pair) and Higgs to two muons (Higgs coupling to second generation fermions), two recent LHC flagship physics analysis, on gate-model quantum computer simulators and hardware. The simulation studies have been performed with the IBM Quantum Framework, Google Tensorflow Quantum Framework, and Amazon Braket Framework, and we have achieved good classification performance that is similar to the performances of the classical machine learning methods currently used in LHC physics analyses, classical SVM, classical BDT, and classical deep neural network for example. We have also performed our studies using IBM superconducting quantum computer hardware and the performance is promising and is approaching the performance from IBM quantum simulators. Moreover, we extend our studies to other QML areas such as quantum anomaly detection and quantum generative adversarial, and some preliminary results have been obtained. Also, we have overcome the challenges of intensive computing resources in the cases of large qubits (25 qubits or more) and large numbers of events using NVIDIA cuQuantum with NERSC Perlmutter HPC. Our studies give an example that Quantum Machine Learning performs as well as its classical counterpart for realistic High Energy Physics analysis datasets. Furthermore, our result on noisy quantum hardware provides important validation for the result on noiseless quantum simulators.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

A Data-driven approach to Determining the Fidelity in the Hardware-in-the-loop Systems using Subspace Identification Method

One of the major questions in any Hardware-in-the-loop (HiL) simulation is to understand the fidelity of the HiL simulation itself which is most often indicated qualitatively as either high or low instead of quantifying it. Being cognizant of the level of fidelity forms the crux to assess the validity and credibility of the HiL simulation. In this work, we address this issue by developing a systematic, data-driven approach to assess the fidelity of any HiL simulation, and more specifically, the fidelity of the interface between the simulator and hardware in an HiL simulation. Applying a subspace identification method, a linear system representing the interface is obtained from the time-series data captured between the hardware and simulator in the HiL simulation. Finally, the fidelity is defined based on this linear system properties. The proposed data-driven fidelity quantification framework is illustrated on the IEEE 123 node feeder system running on HYPERSIM and interacting with virtual protection relays.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Determining quantum phase diagrams of topological Kitaev-inspired models on NISQ quantum hardware

Topological protection is employed in fault-tolerant error correction and in developing quantum algorithms with topological qubits. But, topological protection intrinsic to models being simulated , also robustly protects calculations, even on NISQ hardware. We leverage it by simulating Kitaev-inspired models on IBM quantum computers and accurately determining their phase diagrams. This requires constructing conventional quantum circuits for Majorana braiding to prepare the ground states of Kitaev-inspired models. The entanglement entropy is then measured to calculate the quantum phase boundaries. We show how maintaining particle-hole symmetry when sampling through the Brillouin zone is critical to obtaining high accuracy. This work illustrates how topological protection intrinsic to a quantum model can be employed to perform robust calculations on NISQ hardware, when one measures the appropriate protected quantum properties. It opens the door for further simulation of topological quantum models on quantum hardware available today.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗