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Viewgraphs on the development of the Radiation-Hardened Re-programmable Field-Programmable Gate Array (RHrFPGA) are presented. The topics include: 1) Radiation Test Suite; 2) Testing Interface; 3) Test Configuration; 4) Facilities; 5) Test Programs; 6) Test Procedure; and 7) Test Results. A summary of heavy ion and proton testing is also included.
The small mechanosensitive channel, MscS, is a part of the turgor-driven solute efflux system that protects bacteria from lysis in the event of osmotic downshift. It has been identified in Escherichia coli as a product of the orphan yggB gene, now called mscS (Levina et al., 1999, EMBO J. 18:1730). Here I show that that the isolated 31-kDa MscS protein is sufficient to form a functional mechanosensitive channel gated directly by tension in the lipid bilayer. MscS-6His complexes purified in the presence of octylglucoside and lipids migrate in a high-resolution gel-filtration column as particles of approximately 200 kDa. Consistent with that, the protein cross-linking patterns predict a hexamer. The channel reconstituted in soybean asolectin liposomes was activated by pressures of 20-60 mm Hg and displayed the same asymmetric I-V curve and slight anionic preference as in situ. At the same time, the single-channel conductance is proportional to the buffer conductivity in a wide range of salt concentrations. The rate of channel activation in response to increasing pressure gradient across the patch was slower than the rate of closure in response to decreasing steps of pressure gradient. Therefore, the open probability curves were recorded with descending series of pressures. Determination of the curvature of patches by video imaging permitted measurements of the channel activity as a function of membrane tension (gamma). Po(gamma) curves had the midpoint at 5.5 +/- 0.1 dyne/cm and gave estimates for the energy of opening DeltaG = 11.4 +/- 0.5 kT, and the transition-related area change DeltaA = 8.4 +/- 0.4 nm(2) when fitted with a two-state Boltzmann model. The correspondence between channel properties in the native and reconstituted systems is discussed.
The mechanisms of Ca2+ entry and their effects on cell function were investigated in cultured chicken osteoclasts and putative osteoclasts produced by fusion of mononuclear cell precursors. Voltage-gated Ca2+ channels (VGCC) were detected by the effects of membrane depolarization with K+, BAY K 8644, and dihydropyridine antagonists. K+ produced dose-dependent increases of cytosolic calcium ([Ca2+]i) in osteoclasts on glass coverslips. Half-maximal effects were achieved at 70 mM K+. The effects of K+ were completely inhibited by dihydropyridine derivative Ca2+ channel blocking agents. BAY K 8644 (5 X 10(-6) M), a VGCC agonist, stimulated Ca2+ entry which was inhibited by nicardipine. VGCCs were inactivated by the attachment of osteoclasts to bone, indicating a rapid phenotypic change in Ca2+ entry mechanisms associated with adhesion of osteoclasts to their resorption substrate. Increasing extracellular Ca2+ ([Ca2+]e) induced Ca2+ release from intracellular stores and Ca2+ influx. The Ca2+ release was blocked by dantrolene (10(-5) M), and the influx by La3+. The effects of [Ca2+]e on [Ca2+]i suggests the presence of a Ca2+ receptor on the osteoclast cell membrane that could be coupled to mechanisms regulating cell function. Expression of the [Ca2+]e effect on [Ca2+]i was similar in the presence or absence of bone matrix substrate. Each of the mechanisms producing increases in [Ca2+]i, (membrane depolarization, BAY K 8644, and [Ca2+]e) reduced expression of the osteoclast-specific adhesion structure, the podosome. The decrease in podosome expression was mirrored by a 50% decrease in bone resorptive activity. Thus, stimulated increases of osteoclast [Ca2+]i lead to cytoskeletal changes affecting cell adhesion and decreasing bone resorptive activity.
The High Temperature Integrated Electronics and Sensors (HTIES) Program at the NASA Lewis Research Center is currently developing silicon carbide (SiC) for use in harsh conditions where silicon, the semiconductor used in nearly all of today's electronics, cannot function. The HTIES team recently fabricated and demonstrated the first semiconductor digital logic gates ever to function at 600 C.
Quantum logic gates (QLGs) or other logic systems are based on quantum-dots (QD) with a stringent requirement of size uniformity. The QD are widely known building units for QLGs. The size control of QD is a critical issue in quantum-dot fabrication. The work presented here offers a new method to develop quantum-dots using a bio-template, called ferritin, that ensures QD production in uniform size of nano-scale proportion. The bio-template for uniform yield of QD is based on a ferritin protein that allows reconstitution of core material through the reduction and chelation processes. One of the biggest challenges for developing QLG is the requirement of ordered and uniform size of QD for arrays on a substrate with nanometer precision. The QD development by bio-template includes the electrochemical/chemical reconsitution of ferritins with different core materials, such as iron, cobalt, manganese, platinum, and nickel. The other bio-template method used in our laboratory is dendrimers, precisely defined chemical structures. With ferritin-templated QD, we fabricated the heptagonshaped patterned array via direct nano manipulation of the ferritin molecules with a tip of atomic force microscope (AFM). We also designed various nanofabrication methods of QD arrays using a wide range manipulation techniques. The precise control of the ferritin-templated QD for a patterned arrangement are offered by various methods, such as a site-specific immobilization of thiolated ferritins through local oxidation using the AFM tip, ferritin arrays induced by gold nanoparticle manipulation, thiolated ferritin positioning by shaving method, etc. In the signal measurements, the current-voltage curve is obtained by measuring the current through the ferritin, between the tip and the substrate for potential sweeping or at constant potential. The measured resistance near zero bias was 1.8 teraohm for single holoferritin and 5.7 teraohm for single apoferritin, respectively.
The use of SRAM-based Field Programmable Gate Arrays (FPGAs) is becoming more and more prevalent in space applications. Commercial-grade FPGAs are potentially susceptible to permanently debilitating Single-Event Latchups (SELs). Repair methods based on Evolutionary Algorithms may be applied to FPGA circuits to enable successful fault recovery. This paper presents the experimental results of applying such methods to repair four commonly used circuits (quadrature decoder, 3-by-3-bit multiplier, 3-by-3-bit adder, 440-7 decoder) into which a number of simulated faults have been introduced. The results suggest that evolutionary repair techniques can improve the process of fault recovery when used instead of or as a supplement to Triple Modular Redundancy (TMR), which is currently the predominant method for mitigating FPGA faults.
The main promise of Quantum Dot Cellular Automata (QCA) as a new computing paradigm is the possbility of implementing a set of universal logic gates and thus feasibility of general-purpose computing.
A new body-driven current mirror that utilizes an adaptive gate bias to provide accurate operation over a wide range of bias currents is presented.
Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA.
The electrical characteristics of proton-irradiated bipolar transistors are affected by ionization damage to the insulating oxide and displacement damage to the semiconductor bulk. While both types of damage degrade the transistor, it is important to understand the mechanisms individually and to be able to analyze them separately. In this paper, a method for analyzing the effects of ionization and displacement damage using gate-controlled lateral PNP bipolar junction transistors is described. This technique allows the effects of oxide charge, surface recombination velocity, and bulk traps to be measured independently.
The efficient detection of single photons at 1.06 micron is of considerable interest for lidar/ladar systems designed for remote sensing an d ranging as well as for free-space optical transmission in photon-st arved applications. However, silicon-based single photon avalanche diodes (SPADs) used at shorter wavelengths have very low single photon d etection efficiency (approximately 1 - 2%) at 1.06 micron, and InP/In GaAs SPADs designed for telecommunications wavelengths near 1.5 micro n exhibit high dark count rates that generally inhibit non-gated (free-running) operation. To bridge this "single photon detection gap" for wavelengths just beyond 1 micron, we have developed high performance , large area (80 - 200 micron diameter) InP-based InGaAsP quaternary absorber SPADs optimized for operation at 1.06 micron and based on a highly reliable planar geometry avalanche photodiode structure. We wil l show that dark count rates are sufficiently low to allow for non-ga ted operation while achieving detection efficiencies far surpassing t hose found for Si SPADs. At a detection efficiency of 10%, 80 micron diameter devices exhibit dark count rates below 1000 Hz and count rate s of at least 3 MHz when operated at -40 C. Significantly higher dete ction efficiencies (30 - 50%) are achievable with acceptable tradeoff s in dark count rate. In this paper, we will also discuss performance modeling for these devices and compare their behavior with longer wav elength InP-based InGaAs ternary absorber SPADs fabricated on a relat ed device design platform.
We present initial results for the thin epitaxial Xilinx Virtex-4 Fie ld Programmable Gate Array (FPGA), and compare to previous results ob tained for the Virtex-II and Virtex-II Pro. The data presented was a cquired through a consortium based effort with the common goal of pr oviding the space community with data and mitigation methods for the use of Xilinx FPGAs in space.
An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.
The current implementation of the Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays (TRIGA) is equipped with CFDP protocol and CCSDS Telemetry and Telecommand framing schemes to replace the CPU intensive software counterpart implementation for reliable deep space communication. We present the hardware/software co-design methodology used to accomplish high data rate throughput. The hardware CFDP protocol stack implementation is then compared against the two recent flight implementations. The results from our experiments show that TRIGA offers more than 3 orders of magnitude throughput improvement with less than one-tenth of the power consumption.
In this paper, we present two single stage MMIC amplifiers with the first demonstrating a measured S21 gain of 3-dB at 280-GHz and the second demonstrating 2.5-dB gain at 300- GHz, which is the threshold of the sub-millimeter wave regime. The high-frequency operation is enabled by a high-speed InP HEMT with a 35-nm gate. This is the first demonstrated S21 gain at sub-millimeter wave frequencies in a MMIC.
A regio-regular poly(3-hexylthiophene) (RRP3HT) thin-film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. RRP3HT is a semiconducting polymer that has a carrier mobility and on/off ratio when used in a field effect transistor (FET) configuration. This commercially available polymer is very soluble in common organic solvents and is easily processed to form uniform thin films. The most important polymer-based device fabricated and studied is the FET, since it forms the building block in logic circuits and switches for active matrix (light-emitting-diode) (LED) displays, smart cards, and radio frequency identification (RFID) cards.
A continuing effort to develop carbon-nanotube-based field emitters (cold cathodes) as high-current-density electron sources has yielded an optimized device design and a fabrication scheme to implement the design. One major element of the device design is to use a planar array of bundles of carbon nanotubes as the field-emission tips and to optimize the critical dimensions of the array (principally, heights of bundles and distances between them) to obtain high area-averaged current density and high reliability over a long operational lifetime a concept that was discussed in more detail in Arrays of Bundles of Carbon Nanotubes as Field Emitters (NPO-40817), NASA Tech Briefs, Vol. 31, No. 2 (February 2007), page 58. Another major element of the design is to configure the gate electrodes (anodes used to extract, accelerate, and/or focus electrons) as a ring that overhangs a recess wherein the bundles of nanotubes are located, such that by virtue of the proximity between the ring and the bundles, a relatively low applied potential suffices to generate the large electric field needed for emission of electrons.
An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.