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At least 289 records · Page 16
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Temperature-tuned ultrafast X-ray shutter using optics-on-a-chip

Typically modulation systems are incapable of performing synchronous modulation for high-energy radiation systems. A method and system for performing high-energy synchronous radiation modulating is described. The method includes providing an oscillatory diffractive element, with the oscillatory diffractive element capable of being oscillated over a range of angles. A radiation source provides radiation to the oscillatory diffractive element. An electrical signal is provided to electrodes that oscillate the oscillatory diffractive element to modulate the radiation. A temperature controller controls the temperature of the oscillatory diffractive element to tune the oscillatory motion of the oscillatory diffractive element.

Wang, Jin↗
DOE OSTI2026

On-chip probabilistic inference for charged-particle tracking at the sensor edge

Modern scientific instruments operate under increasingly extreme constraints on bandwidth, latency, and power. Inference at the sensor edge determines experimental data collection efficiency by deciding which information to save for further analysis. Particle tracking detectors at the Large Hadron Collider exemplify this challenge: pixelated silicon sensors generate rich spatiotemporal ionization patterns, yet most of this information is discarded due to data-rate limitations. Concurrently, advancements in co-design tools provide rapid turn-around for incorporating machine learning into application-specific integrated circuits, motivating designs for particle detectors with new integrated technologies. We demonstrate that neural networks embedded in the front-end electronics can infer charged-particle kinematic parameters from a single silicon layer. We regress hit positions and incident angles with calibrated uncertainties, while satisfying stringent constraints on numerical precision, latency, and silicon area. Our results establish a path toward probabilistic inference directly at the edge, opening new opportunities for intelligent sensing in high-rate scientific instruments.

Das, Arghya Ranjan [Purdue U.] (ORCID:000000018451↗
DOE OSTI2026

Measuring quasiparticle dynamics for particle impact reconstruction in a superconducting qubit chip

Quasiparticle poisoning following particle impacts poses a significant challenge to the development of fault-tolerant superconducting quantum computers, as a sudden excess of quasiparticles can simultaneously degrade the coherence of multiple qubits across large device arrays. In this work, we present a statistical analysis that models the time evolution of radiation-induced qubit energy relaxation through quasiparticle density dynamics. This study provides insight into quasiparticle loss processes by distinguishing between recombination and trapping decay channels and assessing their respective impact on qubit performance. We precisely measure quasiparticle recombination in multiple transmon qubits and uncover an unexpected dependence of qubit relaxation dynamics on deposited energy. By linking correlated relaxation events across qubits to ballistic phonon propagation, we introduce a statistical localization approach to extract the energy deposited in the substrate, which is in good agreement with Monte Carlo simulation. This work establishes the quantitative framework for using an arbitrary subset of superconducting transmon qubits in a QPU as energy-resolving witness particle detectors.

Celi, E. [Northwestern U.]↗
DOE OSTI2020

On the Cutting of Metals: A Mechanics Viewpoint

The mechanics of large-strain deformation in cutting of metals is discussed, primarily from viewpoint of recent developments in in situ analysis of plastic flow and microstructure characterization. It is shown that a broad range of deformation parameters can be accessed in chip formation—strains of 1–10, strain rates of 10–10 5 /s, and temperatures up to 0.7T m —and controlled. This range is far wider than achievable by any other single-stage, severe plastic deformation (SPD) process. The resulting extreme deformation conditions produce a rich variety of microstructures in the chip. Four principal types of chip formation—continuous, shear-localized, segmented, and mushroom-type—as elucidated first by Nakayama (1974, “The Formation of ‘Saw-Toothed Chip’ in Metal Cutting,” Proceedings of International Conference on Production Engineering, Tokyo, pp. 572–577) are utilized to emphasize the diverse plastic flow phenomena, especially unsteady deformation modes that prevail in cutting. These chip types are intimately connected with the underlying flow, each arising from a distinct mode and triggered by an instability phenomenon. The role of plastic flow instabilities such as shear banding, buckling, and fracture in mediating unsteady flow modes is expounded, along with consequences of the flow modes and chip types for the cutting. Sinuous flow is shown to be the reason why gummy (highly strain-hardening) metals, although relatively soft, are so difficult to cut. Synthesizing the various observations, a hypothesis is put forth that it is the stability of flow modes that determines the mechanics of cutting. Furthermore, this leads to a flow-stability phase diagram that could provide a framework for predicting chip types and process attributes.

42 ENGINEERING↗
DOE OSTI2022

Dual-scale folding in cutting of commercially pure aluminum alloys

We examine a, hitherto, little-studied and curious machining chip morphology, with tell-tale signs of folding at two different length scales, that is common in cutting of certain ductile and highly strain-hardening metals like soft aluminum alloys, tantalum and niobium. This chip morphology does not appear in the usual catalogues of common chip types. The mechanics of formation of the “dual-scale folded chip” is studied in model material systems of commercially pure aluminum alloys (AA 1100 and AA 8040), that prominently exhibit this chip morphology. The flow, folding and associated plastic instabilities are investigated using micro/macro structure observations of the chip in a plane-strain cutting framework, with high-speed in situ imaging and image analysis of material flow; and force measurements. The smaller-scale folding is shown to develop in the primary deformation zone while the larger-scale folding occurs as the chip traverses the rake face of the tool. The resulting chip is composed of irregularly-spaced large folds, superimposed onto which are the quasi periodic small folds. The representative wavelengths of the two folds differ on average by an order of magnitude, 0.1 mm vs. 2 mm. The observations reveal a direct coupling between the material flow and chip morphology, and how specific attributes of the dual-scale folded chip arise from the flow mechanism. Plastic buckling is found to play a key role in the folding at both length scales. The small-scale folds are characteristic of a sinuous plastic flow mode, while the large-scale folding is characterized by buckling and stick-slip along the tool rake face, triggered by adhesive pinning of the chip to the tool. Important consequences of the dualscale folding are very large cutting forces, and force oscillations of large amplitude, despite the alloys being very soft, only ~ 25 HV. Here, the dual-scale folding is why many of these alloys are classified as “gummy” to machine. Since the dual-scale folded chip is associated with large cutting forces and poor surface quality, there is much to be gained by disrupting this flow type in practical machining applications. Methods for controlling the folding to improve machining performance with the gummy alloys are briefly discussed.

36 MATERIALS SCIENCE↗
DOE OSTI2025

RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades

The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.

Alimonti, G↗
DOE OSTI2023

Better Than Worst-Case Decoding for Quantum Error Correction

The overheads of classical decoding for quantum error correction in cryogenic quantum systems grow rapidly with the number of logical qubits and their correction code distance. Decoding at room temperature is bottlenecked by refrigerator I/O bandwidth while cryogenic on-chip decoding is limited by area/power/thermal budget. To overcome these overheads, we are motivated by the observation that in the common case (over 90% of the time), error correction 'syndromes' are fairly trivial with high redundancy / sparsity, since the error correction codes are over-provisioned to be able to correct for uncommon worst-case complex scenarios (to ensure substantially low logical error rates). If suitably exploited, these trivial scenarios can be handled with insignificant overhead, thereby alleviating any bottlenecks towards handling the worst-case scenarios by state-of-the-art means. Here, we propose Better Than Worst-Case Decoding for Quantum Error Correction, targeting cryogenic quantum systems and Surface Code, consisting of: On-chip Clique Decoder: An extremely lightweight decoder for correcting trivial common-case errors, designed for the cryogenic domain. The decoder is implemented and evaluated for SFQ logic. Statistical Off-chip Bandwidth Allocation: A statistical confidence-based technique for allocation of off-chip decoding bandwidth, to efficiently handle the rare complex decodes that are not covered by the Clique Decoder. Decode-Overflow Execution Stalling: A method to stall circuit execution, for the worst-case scenarios in which the provisioned off-chip bandwidth is insufficient to complete all requested off-chip decodes. In all, BTWC decoding achieves 70-99+% off-chip bandwidth elimination across a range of logical and physical error rates, without significantly sacrificing the accuracy of a state-of-the-art off-chip decoder. Further, it achieves 10-1000x bandwidth reduction over prior bandwidth reduction techniques, as well as 15-37x resource overhead reduction compared to prior on-chip decoding.

cryogenic optimization↗
DOE OSTI2023

High-density integrated delay line using extreme skin-depth subwavelength grating waveguides

Optical delay lines control the flow of light in time, introducing phase and group delays for engineering interferences and ultrashort pulses. Photonic integration of such optical delay lines is essential for chip-scale lightwave signal processing and pulse control. However, typical photonic delay lines based on long spiral waveguides require extensively large chip footprints, ranging from mm 2 to cm 2 scales. Here we present a scalable, high-density integrated delay line using a skin-depth engineered subwavelength grating waveguide, i.e., an extreme skin-depth (eskid) waveguide. The eskid waveguide suppresses the crosstalk between closely spaced waveguides, significantly saving the chip footprint area. Our eskid-based photonic delay line is easily scalable by increasing the number of turns and should improve the photonic chip integration density.

Ahmed, Ishtiaque↗
DOE OSTI2021

Fiber attach enabled wafer level fanout

A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.

Ardalan, Shahab↗
DOE OSTI2023

Fiber attach enabled wafer level fanout

A package assembly includes a silicon photonics chip having an optical waveguide exposed at a first side of the chip and an optical fiber coupling region formed along the first side of the chip. The package assembly includes a mold compound structure formed to extend around second, third, and fourth sides of the chip. The mold compound structure has a vertical thickness substantially equal to a vertical thickness of the chip. The package assembly includes a redistribution layer formed over the chip and over a portion of the mold compound structure. The redistribution layer includes electrically conductive interconnect structures to provide fanout of electrical contacts on the chip to corresponding electrical contacts on the redistribution layer. The redistribution layer is formed to leave the optical fiber coupling region exposed. An optical fiber is connected to the optical fiber coupling region in optical alignment with the optical waveguide within the chip.

Ardalan, Shahab↗
DOE OSTI2021

Characterization and QC practice of 16-channel ADC ASIC at cryogenic temperature for Liquid Argon TPC front-end readout electronics system in DUNE experiment

ColdADC is a low-noise 16-channel analog-to-digital converter ASIC designed for cold readout electronics of Liquid Argon Time Projection Chambers (LArTPCs) in the Deep Underground Neutrino Experiment (DUNE). ColdADC was specifically designed for operation at cryogenic temperatures (77 K–89 K). Cold electronics is considered to be an enabling technology for liquid argon detectors in neutrino experiments. The main function of the chip is to digitize signals from the 16-channel charge-sensitive amplifier designed at BNL (LArASIC) and send digitized signals to the data aggregator and serializer chip (COLDATA). ColdADC operates with a resolution of 12 bits and a sampling rate of 2 MS/s per channel. A complete characterization of prototype chips was conducted at cryogenic temperature, involving power consumption, noise and linearity performance. In the first DUNE Far-Detector module, 384000 data channels will be read out, corresponding to 24000 ColdADC chips. Therefore, systematic testing of ColdADC chips at cryogenic temperature is vital for the quality and reliability of DUNE Single-Phase modules. We have developed a Quality Control (QC) test stand that includes ColdADC evaluation and characterization at cryogenic temperature. The QC procedure was applied to a first batch of 33 chips, corresponding to 528 data channels. The obtained results meet all the required DUNE specifications for ColdADC. Moreover, the testing outcome allowed us to identify possibilities of performance optimization that are currently being addressed in the design of the next version of the chip. The Quality Control procedure is proved to be successful and will be a reference design for future large-batch production testing of final ColdADC ASICs.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Ultralow-threshold thin-film lithium niobate optical parametric oscillator

Materials with strong second-order ( χ <#comment/> ( 2 ) ) optical nonlinearity, especially lithium niobate, play a critical role in building optical parametric oscillators (OPOs). However, chip-scale integration of low-loss χ <#comment/> ( 2 ) materials remains challenging and limits the threshold power of on-chip χ <#comment/> ( 2 ) OPO. Here we report an on-chip lithium niobate optical parametric oscillator at the telecom wavelengths using a quasi-phase-matched, high-quality microring resonator, whose threshold power ( ∼ <#comment/> 30 µ <#comment/> W ) is 400 times lower than that in previous χ <#comment/> ( 2 ) integrated photonics platforms. An on-chip power conversion efficiency of 11% is obtained from pump to signal and idler fields at a pump power of 93 µW. The OPO wavelength tuning is achieved by varying the pump frequency and chip temperature. With the lowest power threshold among all on-chip OPOs demonstrated so far, as well as advantages including high conversion efficiency, flexibility in quasi-phase-matching, and device scalability, the thin-film lithium niobate OPO opens new opportunities for chip-based tunable classical and quantum light sources and provides a potential platform for realizing photonic neural networks.

Lu, Juanjuan (ORCID:0000000319389119)↗
DOE OSTI2024

Scalable Thin Light-Emitting Diode (LED) Light Sheet Platform

The goal of the Scalable Thin Light-Emitting Diode (LED) Light Sheet Platform project is to derisk the manufacturing scalability for a high chip count heterogeneous smart lighting platform, with the potential to enable significant energy savings through dynamic directional light control and custom. Specifically, the project derisks the scalability of a disruptive new computer controlled microassembly fabrication process SRI International is developing, to address fundamental cost barriers to mass production of high chip count systems. This is key for enabling mass adoption and thus maximum societal energy savings impact. The LED light sheet technology is a smart illumination platform that can be applied to lighting, signage, and display. It has features and a form factor similar to bendable or conformal OLED light sheets but uses more efficient LEDs with a remote phosphor layer that is very close to the LED to deliver a luminous efficacy that exceeds 125 lumen/Watt and enable > 50% Lighting Application Efficiency (LAE) energy savings. During Budget Period 1 (BP1), all of the BP1 milestones were successfully completed: (M2.0.1) Design demonstrator details that will meet the final project goals, (M6.1.1) Show lighting output model can predict illuminance, spatial, spectral distribution for specific light-sheet designs and use case, (M3.2.1) Automated loading supports 200 chip arrays, and (M3.3.1) Finish first interconnect process run for 200 chip array. The BP1 Go/No-Go Decision Point (G/NG 1) 200 chip demonstrator sample was in the process of final assembly and test at the end of BP1 on December 31, 2023. The objective was successfully achieved on January 16, 2024, when a wired 200-chip sample underwent confirmation testing that demonstrated a 93.75% first pass electrical yield that successfully exceeded the 75% first-pass electrical yield BP1 G/NG requirement. In addition, all 93.75% of the sample devices lit up, further demonstrating the ability to assemble and transfer small LED chips without damaging their functionality.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2024

Wireless Frequency‐Multiplexed Acoustic Array‐Based Acoustofluidics

Abstract Acoustofluidics has shown great potential in enabling on‐chip technologies for driving liquid flows and manipulating particles and cells for engineering, chemical, and biomedical applications. To introduce on‐demand liquid sample processing and micro/nano‐object manipulation functions to wearable and embeddable electronics, wireless acoustofluidic chips are highly desired. This paper presents wireless acoustofluidic chips to generate acoustic waves carrying sufficient energy and achieve key acoustofluidic functions, including arranging particles and cells, generating fluid streaming, and enriching in‐droplet particles. To enable these functions, the wireless acoustofluidic chips leverage mechanisms, including inductive coupling‐based wireless power transfer (WPT), frequency multiplexing‐based control of multiple acoustic waves, and the resultant acoustic radiation and drag forces. For validation, the wirelessly generated acoustic waves are measured using laser vibrometry when different materials (e.g., bone, tissue, and hand) are inserted between the WPT transmitter and receiver. Moreover, the wireless acoustofluidic chips successfully arrange nanoparticles into different patterns, align cells into parallel pearl chains, generate streaming, and enrich in‐droplet microparticles. This research is anticipated to facilitate the development of embeddable wireless on‐chip flow generators, wearable sensors with liquid sample processing functions, and implantable devices with flow generation and acoustic stimulation abilities for engineering, veterinary, and biomedical applications.

Li, Jiali↗
DOE OSTI2019

Function reconsideration of indium bump in InSb IRFPAs

Indium bumps are generally accepted to possess functions of electrical connection, mechanical support and heat transfer in flip-chip devices. After comparing the distribution of stress components along different paths in InSb infrared focal plane arrays (IRFPAs), we ascertain that local enhancement effects of the stress components are remarkable in regions where the indium bumps are. More specifically, the local enhanced tensile stress in InSb chip connected with the indium bumps can lead to the local fracture of the InSb chip, and the locally enhanced shear and peeling stresses may give rise to the local interfacial delamination between the InSb chip and the indium bumps. These inferences are confirmed by the observed local failure characteristics, such as the distribution of the local delamination, the distribution of the crack widths, and the distribution of the cracks. In addition, the simulated Z-component strain distribution in InSb IRFPAs is also consistent with the backside surface profile of the InAs/GaSb IRFPAs fabricated in America with the identical structure, that is, the InSb chip glued with the indium bumps is concave downward, and the InSb chip glued with the underfill is convex upward. Judging from all these confirmed simulation results, we are confident that the indium bumps play a pivotal role in inducing the local failure of InSb IRFPAs. So the role of the indium bumps in causing the local failure of InSb IRFPAs needs to be supplemented and emphasized to comprehensively evaluate the structural reliability of InSb IRFPAs.

42 ENGINEERING↗
DOE OSTI2023

Evaluation of HPK n + - p planar pixel sensors for the CMS Phase-2 upgrade

To cope with the challenging environment of the planned high luminosity upgrade of the Large Hadron Collider (HL-LHC), scheduled to start operation in 2029, CMS will replace its entire tracking system. The requirements for the tracker are largely determined by the long operation time of 10 years with an instantaneous peak luminosity of up to 7.5 × 10 34 cm –2 s –1 in the ultimate performance scenario. Depending on the radial distance from the interaction point, the silicon sensors will receive a particle fluence corresponding to a non-ionizing energy loss of up to $\Phi_{\text {eq}}$ = 3.5 × 10 16 cm –2 . Here this paper focuses on planar pixel sensor design and qualification up to a fluence of $\Phi_{\text {eq}}$ = 1.4 × 10 16 cm –2 . For the development of appropriate planar pixel sensors an R&D program was initiated, which includes $n^+ -p$ sensors on 150 mm (6”) wafers with an active thickness of 150 μm with pixel sizes of 100 × 25 μm 2 and 50 × 50 μm 2 manufactured by Hamamatsu. Single chip modules with ROC4Sens and RD53A readout chips were made. Irradiation with protons and neutrons, as well was an extensive test beam campaign at DESY were carried out. This paper presents the investigation of various assemblies mainly with ROC4Sens readout chips. It demonstrates that multiple designs fulfill the requirements in terms of breakdown voltage, leakage current and efficiency. The single point resolution for 50 × 50 μm 2 pixels is measured as 4.0 μm for non-irradiated samples, and 6.3 μm after irradiation to $\Phi_{\text {eq}}$ = 7.2 × 10 15 cm –2 .

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗