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At least 271 records · Page 15

Automatic differentiation for design sensitivity analysis of structural systems using multiple processors

An automatic differentiation tool (ADIFOR) is incorporated into a finite element based structural analysis program for shape and non-shape design sensitivity analysis of structural systems. The entire analysis and sensitivity procedures are parallelized and vectorized for high performance computation. Small scale examples to verify the accuracy of the proposed program and a medium scale example to demonstrate the parallel vector performance on multiple CRAY C90 processors are included.

Nguyen, Duc T.↗

Operational summary of an electric propulsion long term test facility

An automated test facility capable of simultaneously operating three 2.5 kW, 30-cm mercury ion thrusters and their power processors is described, along with a test program conducted for the documentation of thruster characteristics as a function of time. Facility controls are analog, with full redundancy, so that in the event of malfunction the facility automaticcally activates a backup mode and notifies an operator. Test data are recorded by a central data collection system and processed as daily averages. The facility has operated continuously for a period of 37 months, over which nine mercury ion thrusters and four power processor units accumulated a total of over 14,500 hours of thruster operating time.

Trump, G. E.↗

A proposed microcomputer implementation of an Omega navigation processor

A microprocessor navigation systems using the Omega process is discussed. Several methods for correcting incoming sky waves are presented along with the hardware design which depends on a microcomputer. The control program is discussed, and block diagrams of the Omega processor and interface systems are presented.

Abel, J. D.↗

Software Implemented Fault-Tolerant (SIFT) user's guide

Program development for a Software Implemented Fault Tolerant (SIFT) computer system is accomplished in the NASA LaRC AIRLAB facility using a DEC VAX-11 to interface with eight Bendix BDX 930 flight control processors. The interface software which provides this SIFT program development capability was developed by AIRLAB personnel. This technical memorandum describes the application and design of this software in detail, and is intended to assist both the user in performance of SIFT research and the systems programmer responsible for maintaining and/or upgrading the SIFT programming environment.

Green, D. F., Jr.↗

Initial operating capability for the hypercluster parallel-processing test bed

The NASA Lewis Research Center is investigating the benefits of parallel processing to applications in computational fluid and structural mechanics. To aid this investigation, NASA Lewis is developing the Hypercluster, a multi-architecture, parallel-processing test bed. The initial operating capability (IOC) being developed for the Hypercluster is described. The IOC will provide a user with a programming/operating environment that is interactive, responsive, and easy to use. The IOC effort includes the development of the Hypercluster Operating System (HYCLOPS). HYCLOPS runs in conjunction with a vendor-supplied disk operating system on a Front-End Processor (FEP) to provide interactive, run-time operations such as program loading, execution, memory editing, and data retrieval. Run-time libraries, that augment the FEP FORTRAN libraries, are being developed to support parallel and vector processing on the Hypercluster. Special utilities are being provided to enable passage of information about application programs and their mapping to the operating system. Communications between the FEP and the Hypercluster are being handled by dedicated processors, each running a Message-Passing Kernel, (MPK). A shared-memory interface allows rapid data exchange between HYCLOPS and the communications processors. Input/output handlers are built into the HYCLOPS-MPK interface, eliminating the need for the user to supply separate I/O support programs on the FEP.

Cole, Gary L.↗

NASTRAN thermal analyzer in a unified finite-element treatment of thermo-structural analyses

The NASTRAN thermal analyzer (NTA) which performs large-scale unified thermo-structural analyses with the NASTRAN (NASA structural analysis) computer program is described. The mathematical similitude between these two distinct disciplines of thermal and structure is examined. It serves as the theoretical basis upon which the implementation of the thermal capability in NASTRAN was accomplished. The program structure, the functional flow, the solution algorithms, the organization of an input data deck and the solution capabilities of NTA are summarized. Emphasis is placed on the interface of the unified approach in thermo-structural analyses where stresses, deflections, vibrations and bucklings induced by the effect of temperature change are of concern. Attentions are also directed to the preprocessor and post processors. As a specially designed preprocessor, the VIEW program is capable of generating exchange factors which can be output, at user's option, in formats compatible with that required by NTA. Two post processors that serve specific objectives are included. They are the thermal variance analysis and the graphical displaying capability of temperatures in color or black and white.

Lee, H. P.↗

Extended performance electric propulsion power processor design study. Volume 1: Executive summary

Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30cm ion thruster power processor with a beam supply rating of 2.2kW to 10kW. Extensions in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. Preliminary electrical design, mechanical design, and thermal analysis were performed on a 6kW power transformer for the beam supply. Bi-Mod mechanical, structural, and thermal control configurations were evaluated for the power processor, and preliminary estimates of mechanical weight were determined. A program development plan was formulated that outlines the work breakdown structure for the development, qualification and fabrication of the power processor flight hardware.

Biess, J. J.↗

Advanced development of a programmable power processor

The need for the development of a multipurpose flexible programmable power processor (PPP) has increased significantly in recent years to reduce ever rising development costs. One of the program requirements the PPP specification will cover is the 25 kW power module power conversion needs. The 25 kW power module could support the Space Shuttle program during the 1980s and 1990s and could be the stepping stone to future large space programs. Trades that led to selection of a microprocessor controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Component selection and design considerations are also discussed.

Lukens, F. E.↗

Methodologies and Tools for Tuning Parallel Programs: Facts and Fantasies

The need for computing power has forced a migration from serial computation on a single processor to parallel processing on multiprocessors. However, without effective means to monitor (and analyze) program execution, tuning the performance of parallel programs becomes exponentially difficult as program complexity and machine size increase. The recent introduction of performance tuning tools from various supercomputer vendors (Intel's ParAide, TMC's PRISM, CRI's Apprentice, and Convex's CXtrace) seems to indicate the maturity of performance tool technologies and vendors'/customers' recognition of their importance. However, a few important questions remain: What kind of performance bottlenecks can these tools detect (or correct)? How time consuming is the performance tuning process? What are some important technical issues that remain to be tackled in this area? This workshop reviews the fundamental concepts involved in analyzing and improving the performance of parallel and heterogeneous message-passing programs. Several alternative strategies will be contrasted, and for each we will describe how currently available tuning tools (e.g. AIMS, ParAide, PRISM, Apprentice, CXtrace, ATExpert, Pablo, IPS-2) can be used to facilitate the process. We will characterize the effectiveness of the tools and methodologies based on actual user experiences at NASA Ames Research Center. Finally, we will discuss their limitations and outline recent approaches taken by vendors and the research community to address them.

Yan, Jerry C.↗

Validation of an SEU simulation technique for a complex processor: PowerPC7400

Published data on the processors sensitivites with respect to SEU is generally obtained from radiation ground testing during which the program is executed by the DUT consists in the sequential inspection of each of the processor memory cells accessible to the user, through the execution of a suitable instruction sequence. In such programs, so-called static tests, typically considered memory cells are general-purpose registers, special registers (program counter, stack pointer...) and internal memory. Nevertheless, the register use and duty cycle of the final application will be very different, including using instructions no in the static tests and disturbing other potential SEU targets. The ideal would be the use of the final application program for the radiation ground testing, but generally this program is either unknown or unavailable when the qualification testing is performed on candidate circuits to space projects.

Radiation↗

The DLG processor: A data management executive for the engineering design integration (EDIN) system. Volume 1: Engineering description and utilization manual

The DLG processor is a Univac 1100 series computer program designed to read, modify, manipulate, and replace symbolic images. DLG is controlled by a set of user supplied directives and operates from a data base of stratified information which can be merged with the symbolic images. Data bases can be constructed and maintained in the mass storage media using the DLG directive language.

Glatt, C. R.↗

Star tracker constraint violations digital capability description and analysis results. Mission planning, mission analysis, and software formulation

Results of star tracker constraint violation analyses performed with the digital computer program Shuttle Attitude and Pointing Time Line Processor (SAPT) are presented. Results are typical of those utilized to provide the information required to update Baseline Reference Mission Attitude and Pointing Time Lines. Descriptions of SAPT modifications implemented to perform these analyses are also presented.

Poston, P. L.↗

NASTRAN: User's Experiences

The application of NASTRAN to a wide variety of static and dynamic structural problems is discussed. The following topics are focused upon: (1) methods of analysis; (2) hydroelastic methods; (3) complete analysis of structures; (4) elements and material studies; (5) critical comparisons with other programs; and (6) pre- and post-processor operations.

Source record↗

PARS: Programs for Analysis and Resizing of Structures, user manual

PARS processors and their use, flutter analysis, sensitivity analysis for stresses, and resizing are presented. Design variable definition and interface with finite element model, static constraints and their derivatives, flutter derivatives, and optimization are discussed.

Haftka, R. T.↗

Software design and documentation language, revision 1

The Software Design and Documentation Language (SDDL) developed to provide an effective communications medium to support the design and documentation of complex software applications is described. Features of the system include: (1) a processor which can convert design specifications into an intelligible, informative machine-reproducible document; (2) a design and documentation language with forms and syntax that are simple, unrestrictive, and communicative; and (3) methodology for effective use of the language and processor. The SDDL processor is written in the SIMSCRIPT II programming language and is implemented on the UNIVAC 1108, the IBM 360/370, and Control Data machines.

Kleine, H.↗

Programs for analysis and resizing of complex structures

The paper describes the PARS (Programs for Analysis and Resizing of Structures) system. PARS is a user oriented system of programs for the minimum weight design of structures modeled by finite elements and subject to stress, displacement, flutter and thermal constraints. The system is built around SPAR - an efficient and modular general purpose finite element program, and consists of a series of processors that communicate through the use of a data base. An efficient optimizer based on the Sequence of Unconstrained Minimization Technique (SUMT) with an extended interior penalty function and Newton's method is used. Several problems are presented for demonstration of the system capabilities.

Haftka, R. T.↗

A Loran-C prototype navigation receiver for general aviation

Investigations have been conducted regarding the techniques required for Loran-C navigation with application to the general-aviation pilot. The goal has been to produce prototype equipment for flight evaluation which will provide enroute navigation in both latitude-longitude and rho-theta coordinates and to evaluate the nonprecision approach capabilities of such equipment. In connection with the considered project, a prototype Loran-C receiver has been flight-tested using a variety of flight paths, with and without simultaneous ground radar position data collection. Attention is given to a receiver overview, an antenna preamplifier/coupler, the Loran-C receiver RF processor, the tracking loop hardware, tracking loop programming, video output, the laboratory and flight evaluation, and work currently in progress.

Lilley, R. W.↗