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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 271 records · Page 15

All sources NASA NTRS DOE OSTI

NASA NTRS1979

Dedicated nuclear facilities for electrolytic hydrogen production

An advanced technology, fully dedicated nuclear-electrolytic hydrogen production facility is presented. This plant will produce hydrogen and oxygen only and no electrical power will be generated for off-plant use. The conceptual design was based on hydrogen production to fill a pipeline at 1000 psi and a 3000 MW nuclear base, and the base-line facility nuclear-to-shaftpower and shaftpower-to-electricity subsystems, the water treatment subsystem, electricity-to-hydrogen subsystem, hydrogen compression, efficiency, and hydrogen production cost are discussed. The final conceptual design integrates a 3000 MWth high-temperature gas-cooled reactor operating at 980 C helium reactor-out temperature, direct dc electricity generation via acyclic generators, and high-current density, high-pressure electrolyzers based on the solid polymer electrolyte approach. All subsystems are close-coupled and optimally interfaced and pipeline hydrogen is produced at 1000 psi. Hydrogen costs were about half of the conventional nuclear electrolysis process.

Foh, S. E.↗

NASA NTRS1981

Applications study of advanced power generation systems utilizing coal-derived fuels. Volume 1: Executive summary

The technology status of phosphoric acid and molten carbon fuel cells, combined gas and steam turbine cycles, and magnetohydrodynamic energy conversion systems was assessed and the power performance of these systems when operating with medium-Btu fuel gas whether delivered by pipeline to the power plant or in an integrated mode in which the coal gasification process and power system are closely coupled as an overall power plant was evaluated. Commercially available combined-cycle gas turbine systems can reach projected required performance levels for advanced systems using currently available technology. The phosphoric acid fuel cell appears to be the next most likely candidate for commercialization. On pipeline delivery, the systems efficiency ranges from 40.9% for the phosphoric acid fuel cell to 63% for the molten carbonate fuel cell system. The efficiencies of the integrated power plants vary from approximately 39-40% for the combined cycle to 46-47% for the molden carbonate fuel cell systems. Conventional coal-fired steam stations with flue-gas desulfurization have only 33-35% efficiency.

Robson, F. L.↗

NASA NTRS1981

Real time software tools and methodologies

Real time systems are characterized by high speed processing and throughput as well as asynchronous event processing requirements. These requirements give rise to particular implementations of parallel or pipeline multitasking structures, of intertask or interprocess communications mechanisms, and finally of message (buffer) routing or switching mechanisms. These mechanisms or structures, along with the data structue, describe the essential character of the system. These common structural elements and mechanisms are identified, their implementation in the form of routines, tasks or macros - in other words, tools are formalized. The tools developed support or make available the following: reentrant task creation, generalized message routing techniques, generalized task structures/task families, standardized intertask communications mechanisms, and pipeline and parallel processing architectures in a multitasking environment. Tools development raise some interesting prospects in the areas of software instrumentation and software portability. These issues are discussed following the description of the tools themselves.

Christofferson, M. J.↗

NASA NTRS1982

Control structures for high speed processors

A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

Maki, G. K.↗

NASA NTRS1983

VLSI architectures for computing multiplications and inverses in GF(2-m)

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that are easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. A pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal-basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

Wang, C. C.↗

NASA NTRS1985

Fast Control Sequencer

Unit faster than conventional circuits and contains fewer integrated circuits. Fast logic controller accommodates three delays before second half cycle of clock signal strobes status latch: Outputs of pipeline register must settle; selected input status line signal must propagate through status multiplexer and arrive at status latch; and it takes 3 nanoseconds for status latch set up before strobed. During second half cycle, output-enable line produces next instruction and applies it to pipeline register.

Lahmeyer, C. R.↗

NASA NTRS1984

Applications of array processors in the analysis of remote sensing images

The architectures, programming characteristics, and ranges of application of past, present, and planned array processors for the digital processing of remote-sensing images are compared. Such functions as radiometric and geometric corrections, principal-components analysis, cluster coding, histogram generation, grey-level mapping, convolution, classification, and mensuration and modeling operations are considered, and both pipeline-type and single-instruction/multiple-data-stream (SIMD) arrays are evaluated. Numerical results are presented in a table, and it is found that the pipeline-type arrays normally used with minicomputers increase their speed significantly at low cost, while even further gains are provided by the more expensive SIMD arrays. Most image-processing operations become I/O-limited when SIMD arrays are used with current I/O devices.

Ramapriyan, H. K.↗

NASA NTRS1985

VLSI architectures for computing multiplications and inverses in GF(2m)

Wang, C. C.↗

NASA NTRS1984

High speed quantitative digital microscopy

Modern digital image processing hardware makes possible quantitative analysis of microscope images at high speed. This paper describes an application to automatic screening for cervical cancer. The system uses twelve MC6809 microprocessors arranged in a pipeline multiprocessor configuration. Each processor executes one part of the algorithm on each cell image as it passes through the pipeline. Each processor communicates with its upstream and downstream neighbors via shared two-port memory. Thus no time is devoted to input-output operations as such. This configuration is expected to be at least ten times faster than previous systems.

Castleman, K. R.↗

NASA NTRS1986

Integrated-Circuit Active Digital Filter

Pipeline architecture with parallel multipliers and adders speeds calculation of weighted sums. Picture-element values and partial sums flow through delay-adder modules. After each cycle or time unit of calculation, each value in filter moves one position right. Digital integrated-circuit chips with pipeline architecture rapidly move 35 X 35 two-dimensional convolutions. Need for such circuits in image enhancement, data filtering, correlation, pattern extraction, and synthetic-aperture-radar image processing: all require repeated calculations of weighted sums of values from images or two-dimensional arrays of data.

Nathan, R.↗

NASA NTRS1986

Flow Injector Would Keep Slurry From Settling

Ring nozzle helps to prevent choking of coal-slurry pipelines. Intended originally for use in coal mines, nozzle concept generally applicable to short-haul slurry pipelines where high-pressure water (or other slurry fluid) available. Extra water injected into flow near wall of slurry pipe to keep slurry particles from setting and blocking pipe.

Lewis, E. V.↗

NASA NTRS1985

Evaluation of existing and proposed computer architectures for future ground-based systems

Parallel processing architectures and techniques used in current supercomputers are described and projections are made of future advances. Presently, the von Neumann sequential processing pattern has been accelerated by having separate I/O processors, interleaved memories, wide memories, independent functional units and pipelining. Recent supercomputers have featured single-input, multiple data stream architectures, which have different processors for performing various operations (vector or pipeline processors). Multiple input, multiple data stream machines have also been developed. Data flow techniques, wherein program instructions are activated only when data are available, are expected to play a large role in future supercomputers, along with increased parallel processor arrays. The enhanced operational speeds are essential for adequately treating data from future spacecraft remote sensing instruments such as the Thematic Mapper.

Schulbach, C.↗

NASA NTRS1987

Reed-Solomon decoder

A Reed-Solomon decoder with dedicated hardware for five sequential algorithms was designed with overall pipelining by memory swapping between input, processing and output memories, and internal pipelining through the five algorithms. The code definition used in decoding is specified by a keyword received with each block of data so that a number of different code formats may be decoded by the same hardware.

Lahmeyer, Charles R.↗

NASA NTRS1988

A visual programming environment for the Navier-Stokes computer

The Navier-Stokes computer is a high-performance, reconfigurable, pipelined machine designed to solve large computational fluid dynamics problems. Due to the complexity of the architecture, development of effective, high-level language compilers for the system appears to be a very difficult task. Consequently, a visual programming methodology has been developed which allows users to program the system at an architectural level by constructing diagrams of the pipeline configuration. These schematic program representations can then be checked for validity and automatically translated into machine code. The visual environment is illustrated by using a prototype graphical editor to program an example problem.

Tomboulian, Sherryl↗

NASA NTRS1988

Programming the Navier-Stokes computer: An abstract machine model and a visual editor

The Navier-Stokes computer is a parallel computer designed to solve Computational Fluid Dynamics problems. Each processor contains several floating point units which can be configured under program control to implement a vector pipeline with several inputs and outputs. Since the development of an effective compiler for this computer appears to be very difficult, machine level programming seems necessary and support tools for this process have been studied. These support tools are organized into a graphical program editor. A programming process is described by which appropriate computations may be efficiently implemented on the Navier-Stokes computer. The graphical editor would support this programming process, verifying various programmer choices for correctness and deducing values such as pipeline delays and network configurations. Step by step details are provided and demonstrated with two example programs.

Middleton, David↗

NASA NTRS1987

Computational structures for robotic computations

The computational problem of inverse kinematics and inverse dynamics of robot manipulators by taking advantage of parallelism and pipelining architectures is discussed. For the computation of inverse kinematic position solution, a maximum pipelined CORDIC architecture has been designed based on a functional decomposition of the closed-form joint equations. For the inverse dynamics computation, an efficient p-fold parallel algorithm to overcome the recurrence problem of the Newton-Euler equations of motion to achieve the time lower bound of O(log sub 2 n) has also been developed.

Lee, C. S. G.↗

NASA NTRS1990

Feasibility study, software design, layout and simulation of a two-dimensional fast Fourier transform machine for use in optical array interferometry

The NASA-Cornell Univ.-Worcester Polytechnic Institute Fast Fourier Transform (FFT) chip based on the architecture of the systolic FFT computation as presented by Boriakoff is implemented into an operating device design. The kernel of the system, a systolic inner product floating point processor, was designed to be assembled into a systolic network that would take incoming data streams in pipeline fashion and provide an FFT output at the same rate, word by word. It was thoroughly simulated for proper operation, and it has passed a comprehensive set of tests showing no operational errors. The black box specifications of the chip, which conform to the initial requirements of the design as specified by NASA, are given. The five subcells are described and their high level function description, logic diagrams, and simulation results are presented. Some modification of the Read Only Memory (ROM) design were made, since some errors were found in it. Because a four stage pipeline structure was used, simulating such a structure is more difficult than an ordinary structure. Simulation methods are discussed. Chip signal protocols and chip pinout are explained.

Boriakoff, Valentin↗

NASA NTRS1989

Correlative visualization techniques for multidimensional data

Critical to the understanding of data is the ability to provide pictorial or visual representation of those data, particularly in support of correlative data analysis. Despite the advancement of visualization techniques for scientific data over the last several years, there are still significant problems in bringing today's hardware and software technology into the hands of the typical scientist. For example, there are other computer science domains outside of computer graphics that are required to make visualization effective such as data management. Well-defined, flexible mechanisms for data access and management must be combined with rendering algorithms, data transformation, etc. to form a generic visualization pipeline. A generalized approach to data visualization is critical for the correlative analysis of distinct, complex, multidimensional data sets in the space and Earth sciences. Different classes of data representation techniques must be used within such a framework, which can range from simple, static two- and three-dimensional line plots to animation, surface rendering, and volumetric imaging. Static examples of actual data analyses will illustrate the importance of an effective pipeline in data visualization system.

Treinish, Lloyd A.↗