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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Parallelization of ARC3D with Computer-Aided Tools

A series of efforts have been devoted to investigating methods of porting and parallelizing applications quickly and efficiently for new architectures, such as the SCSI Origin 2000 and Cray T3E. This report presents the parallelization of a CFD application, ARC3D, using the computer-aided tools, Cesspools. Steps of parallelizing this code and requirements of achieving better performance are discussed. The generated parallel version has achieved reasonably well performance, for example, having a speedup of 30 for 36 Cray T3E processors. However, this performance could not be obtained without modification of the original serial code. It is suggested that in many cases improving serial code and performing necessary code transformations are important parts for the automated parallelization process although user intervention in many of these parts are still necessary. Nevertheless, development and improvement of useful software tools, such as Cesspools, can help trim down many tedious parallelization details and improve the processing efficiency.

Jin, Haoqiang↗
NASA NTRS1988

BLITZEN - A highly integrated massively parallel machine

The architecture and VLSI design of a new massively parallel processing array chip are described. The BLITZEN processing element array chip, which contains 1.1 million transistors, serves as the basis for a highly integrated, miniaturized, high-performance, massively parallel machine that is currently under development. Each processing element has 1K bits of static RAM and performs bit-serial processing with functional elements for arithmetic, logic, and shifting.

Blevins, D. W.↗
NASA NTRS1988

BLITZEN: A highly integrated massively parallel machine

The architecture and VLSI design of a new massively parallel processing array chip are described. The BLITZEN processing element array chip, which contains 1.1 million transistors, serves as the basis for a highly integrated, miniaturized, high-performance, massively parallel machine that is currently under development. Each processing element has 1K bits of static RAM and performs bit-serial processing with functional elements for arithmetic, logic, and shifting.

Blevins, D. W.↗
NASA NTRS1994

Methodologies and Tools for Tuning Parallel Programs: Facts and Fantasies

The need for computing power has forced a migration from serial computation on a single processor to parallel processing on multiprocessors. However, without effective means to monitor (and analyze) program execution, tuning the performance of parallel programs becomes exponentially difficult as program complexity and machine size increase. The recent introduction of performance tuning tools from various supercomputer vendors (Intel's ParAide, TMC's PRISM, CRI's Apprentice, and Convex's CXtrace) seems to indicate the maturity of performance tool technologies and vendors'/customers' recognition of their importance. However, a few important questions remain: What kind of performance bottlenecks can these tools detect (or correct)? How time consuming is the performance tuning process? What are some important technical issues that remain to be tackled in this area? This workshop reviews the fundamental concepts involved in analyzing and improving the performance of parallel and heterogeneous message-passing programs. Several alternative strategies will be contrasted, and for each we will describe how currently available tuning tools (e.g. AIMS, ParAide, PRISM, Apprentice, CXtrace, ATExpert, Pablo, IPS-2) can be used to facilitate the process. We will characterize the effectiveness of the tools and methodologies based on actual user experiences at NASA Ames Research Center. Finally, we will discuss their limitations and outline recent approaches taken by vendors and the research community to address them.

Yan, Jerry C.↗
NASA NTRS1994

Performance Evaluation Methodologies and Tools for Massively Parallel Programs

The need for computing power has forced a migration from serial computation on a single processor to parallel processing on multiprocessors. However, without effective means to monitor (and analyze) program execution, tuning the performance of parallel programs becomes exponentially difficult as program complexity and machine size increase. The recent introduction of performance tuning tools from various supercomputer vendors (Intel's ParAide, TMC's PRISM, CSI'S Apprentice, and Convex's CXtrace) seems to indicate the maturity of performance tool technologies and vendors'/customers' recognition of their importance. However, a few important questions remain: What kind of performance bottlenecks can these tools detect (or correct)? How time consuming is the performance tuning process? What are some important technical issues that remain to be tackled in this area? This workshop reviews the fundamental concepts involved in analyzing and improving the performance of parallel and heterogeneous message-passing programs. Several alternative strategies will be contrasted, and for each we will describe how currently available tuning tools (e.g., AIMS, ParAide, PRISM, Apprentice, CXtrace, ATExpert, Pablo, IPS-2)) can be used to facilitate the process. We will characterize the effectiveness of the tools and methodologies based on actual user experiences at NASA Ames Research Center. Finally, we will discuss their limitations and outline recent approaches taken by vendors and the research community to address them.

Yan, Jerry C.↗
NASA NTRS1996

Methodologies and Tools for Tuning Parallel Programs: 80% Art, 20% Science, and 10% Luck

The need for computing power has forced a migration from serial computation on a single processor to parallel processing on multiprocessors. However, without effective means to monitor (and analyze) program execution, tuning the performance of parallel programs becomes exponentially difficult as program complexity and machine size increase. In the past few years, the ubiquitous introduction of performance tuning tools from various supercomputer vendors (Intel's ParAide, TMC's PRISM, CRI's Apprentice, and Convex's CXtrace) seems to indicate the maturity of performance instrumentation/monitor/tuning technologies and vendors'/customers' recognition of their importance. However, a few important questions remain: What kind of performance bottlenecks can these tools detect (or correct)? How time consuming is the performance tuning process? What are some important technical issues that remain to be tackled in this area? This workshop reviews the fundamental concepts involved in analyzing and improving the performance of parallel and heterogeneous message-passing programs. Several alternative strategies will be contrasted, and for each we will describe how currently available tuning tools (e.g. AIMS, ParAide, PRISM, Apprentice, CXtrace, ATExpert, Pablo, IPS-2) can be used to facilitate the process. We will characterize the effectiveness of the tools and methodologies based on actual user experiences at NASA Ames Research Center. Finally, we will discuss their limitations and outline recent approaches taken by vendors and the research community to address them.

Yan, Jerry C.↗
NASA NTRS1983

Performance evaluation of the JPL interim digital SAR processor

The performance of the Interim Digital SAR Processor (IDP) was evaluated. The IDP processor was originally developed for experimental processing of digital SEASAT SAR data. One phase of the system upgrade which features parallel processing in three peripheral array processors, automated estimation for Doppler parameters, and unsupervised image pixel location determination and registration was executed. The method to compensate for the target range curvature effect was improved. A four point interpolation scheme is implemented to replace the nearest neighbor scheme used in the original IDP. The processor still maintains its fast throughput speed. The current performance and capability of the processing modes now available on the IDP system are updated.

Wu, C.↗
NASA NTRS1990

Computational methods and software systems for dynamics and control of large space structures

This final report on computational methods and software systems for dynamics and control of large space structures covers progress to date, projected developments in the final months of the grant, and conclusions. Pertinent reports and papers that have not appeared in scientific journals (or have not yet appeared in final form) are enclosed. The grant has supported research in two key areas of crucial importance to the computer-based simulation of large space structure. The first area involves multibody dynamics (MBD) of flexible space structures, with applications directed to deployment, construction, and maneuvering. The second area deals with advanced software systems, with emphasis on parallel processing. The latest research thrust in the second area, as reported here, involves massively parallel computers.

Park, K. C.↗
NASA NTRS2012

Best Merge Region Growing Segmentation with Integrated Non-Adjacent Region Object Aggregation

Best merge region growing normally produces segmentations with closed connected region objects. Recognizing that spectrally similar objects often appear in spatially separate locations, we present an approach for tightly integrating best merge region growing with non-adjacent region object aggregation, which we call Hierarchical Segmentation or HSeg. However, the original implementation of non-adjacent region object aggregation in HSeg required excessive computing time even for moderately sized images because of the required intercomparison of each region with all other regions. This problem was previously addressed by a recursive approximation of HSeg, called RHSeg. In this paper we introduce a refined implementation of non-adjacent region object aggregation in HSeg that reduces the computational requirements of HSeg without resorting to the recursive approximation. In this refinement, HSeg s region inter-comparisons among non-adjacent regions are limited to regions of a dynamically determined minimum size. We show that this refined version of HSeg can process moderately sized images in about the same amount of time as RHSeg incorporating the original HSeg. Nonetheless, RHSeg is still required for processing very large images due to its lower computer memory requirements and amenability to parallel processing. We then note a limitation of RHSeg with the original HSeg for high spatial resolution images, and show how incorporating the refined HSeg into RHSeg overcomes this limitation. The quality of the image segmentations produced by the refined HSeg is then compared with other available best merge segmentation approaches. Finally, we comment on the unique nature of the hierarchical segmentations produced by HSeg.

Tilton, James C.↗
DOE OSTI2024

Process–Property–Performance Mapping of Additively Manufactured 316H Stainless Steel Components

The Advanced Materials and Manufacturing Technologies Program is focused on accelerating the development of advanced materials and components fabricated via additive manufacturing, and is using laser powder bed fusion (LPBF) of 316H stainless steel as an initial case study. In the previous fiscal year, miniature high-throughput specimens were printed on multiple LPBF systems to provide initial processing windows to minimize porosity and limit epitaxial grain growth during prints. This fiscal year, scaled builds were completed on three different LPBF systems at ORNL: a GE Concept Laser M2, a Renishaw AM400, and an EOS M290. Builds on the Concept Laser were conducted on multiple powder lots and processing parameter ranges to provide microstructure effects on time-independent and time-dependent mechanical properties. Builds on the Renishaw were produced using Oak Ridge National Laboratory (ORNL)-optimized printing parameters and Argonne National Laboratory (ANL)-optimized printing parameters to compare outcomes of parallel process optimization efforts at different national laboratories on the same LPBF system. Similarly, the build completed on the EOS M290 replicated the processing parameters of builds completed at Los Alamos National Laboratory (LANL). Optical microscopy and electron backscatter diffraction characterization was completed on all builds. In addition to the general round robin characterization, this work-package generated time-independent data, including tensile and fracture toughness test data on scaled Concept Laser builds as a function of processing parameters and post-build heat treatment. This analysis is complimentary to work in parallel work packages aiming to establish heat treatment and processing effects on time-dependent properties. It was found that although the stress-relief heat treatment provides the highest strength at lower-temperatures, tensile strength begins to converge at higher temperatures regardless of heat treatment condition. In addition, the more rigorous solution annealing and hot-isostatic pressing post-build heat treatments result in higher fracture toughness than the stress-relieved condition. The root-causes of the lower fracture toughness of the stress-relieved LPBF 316H material was informed via a stress-relief optimization study on a scaled concept laser print, where it was found that although dislocation recovery was largely complete after only a couple hours at 650°C, the extended hold of the current 24h heat treatment employed on scaled builds likely caused increased carbide volume fractions along the LPBF 316H grain boundaries, thereby deteriorating crack propagation resistance. This trend was seen to become more deleterious with additional increases of stress-relief temperature to 750°C or 850°C. These results have helped inform a new optimal stress-relief annealing condition for LPBF 316H for future campaign testing (650°C for 2h).

36 MATERIALS SCIENCE↗
DOE OSTI2024

Process–Property–Performance Mapping of Additively Manufactured 316H Stainless Steel Components

The Advanced Materials and Manufacturing Technologies Program is focused on accelerating the development of advanced materials and components fabricated via additive manufacturing, and is using laser powder bed fusion (LPBF) of 316H stainless steel as an initial case study. In the previous fiscal year, miniature high-throughput specimens were printed on multiple LPBF systems to provide initial processing windows to minimize porosity and limit epitaxial grain growth during prints. This fiscal year, scaled builds were completed on three different LPBF systems at ORNL: a GE Concept Laser M2, a Renishaw AM400, and an EOS M290. Builds on the Concept Laser were conducted on multiple powder lots and processing parameter ranges to provide microstructure effects on time-independent and time-dependent mechanical properties. Builds on the Renishaw were produced using Oak Ridge National Laboratory (ORNL)-optimized printing parameters and Argonne National Laboratory (ANL)-optimized printing parameters to compare outcomes of parallel process optimization efforts at different national laboratories on the same LPBF system. Similarly, the build completed on the EOS M290 replicated the processing parameters of builds completed at Los Alamos National Laboratory (LANL). Optical microscopy and electron backscatter diffraction characterization was completed on all builds. In addition to the general round robin characterization, this work-package generated time-independent data, including tensile and fracture toughness test data on scaled Concept Laser builds as a function of processing parameters and post-build heat treatment. This analysis is complimentary to work in parallel work packages aiming to establish heat treatment and processing effects on time-dependent properties. It was found that although the stress-relief heat treatment provides the highest strength at lower-temperatures, tensile strength begins to converge at higher temperatures regardless of heat treatment condition. In addition, the more rigorous solution annealing and hot-isostatic pressing post-build heat treatments result in higher fracture toughness than the stress-relieved condition. The root-causes of the lower fracture toughness of the stress-relieved LPBF 316H material was informed via a stress-relief optimization study on a scaled concept laser print, where it was found that although dislocation recovery was largely complete after only a couple hours at 650°C, the extended hold of the current 24h heat treatment employed on scaled builds likely caused increased carbide volume fractions along the LPBF 316H grain boundaries, thereby deteriorating crack propagation resistance. This trend was seen to become more deleterious with additional increases of stress-relief temperature to 750°C or 850°C. These results have helped inform a new optimal stress-relief annealing condition for LPBF 316H for future campaign testing (650°C for 2h).

36 MATERIALS SCIENCE↗
NASA NTRS1987

Real time identification of large space structures

Identification of frequencies, damping ratios, and mode shapes of large space structures (LSSs) are examined in real time. Real time processing allows for quick updates of model processing after a reconfiguration of structural failure. Recursive lattice least squares (RLLS) was selected as the baseline algorithm for the identification. Simulation results on a one dimensional LSS demonstrated that it provides good estimates, was not ill-conditioned in the presence of under-excited modes, allowed activity by a supervisory control system which prevented damage to the LSS or excessive drift, and was capable of real-time processing for typical LSS models. A suboptimal version of RLLS, which is equivalent to simulated parallel processing, was derived. A NASTRAN model of the dual keel U.S. space station was used to demonstrate the input/identification algorithm package in a more realistic simulation. Because the first eight flexible modes were very close together, the identification was much more difficult than in the simple examples. Even so, the model was accurately identified in real time.

Voss, Janice E.↗
NASA NTRS2018

Body of Knowledge for Graphics Processing Units (GPUs)

Graphics Processing Units (GPU) have emerged as a proven technology that enables high performance computing and parallel processing in a small form factor. GPUs enhance the traditional computer paradigm by permitting acceleration of complex mathematics and providing the capability to perform weighted calculations, such as those in artificial intelligence systems. Despite the performance enhancements provided by this type of microprocessor, there exist tradeoffs in regards to reliability and radiation susceptibility, which may impact mission success. This report provides an insight into GPU architecture and its potential applications in space and other similar markets. It also discusses reliability, qualification, and radiation considerations for testing GPUs.

NASA Electronic Parts and Packaging (NEPP) Program↗
NASA NTRS1990

Autoplan: A self-processing network model for an extended blocks world planning environment

Self-processing network models (neural/connectionist models, marker passing/message passing networks, etc.) are currently undergoing intense investigation for a variety of information processing applications. These models are potentially very powerful in that they support a large amount of explicit parallel processing, and they cleanly integrate high level and low level information processing. However they are currently limited by a lack of understanding of how to apply them effectively in many application areas. The formulation of self-processing network methods for dynamic, reactive planning is studied. The long-term goal is to formulate robust, computationally effective information processing methods for the distributed control of semiautonomous exploration systems, e.g., the Mars Rover. The current research effort is focusing on hierarchical plan generation, execution and revision through local operations in an extended blocks world environment. This scenario involves many challenging features that would be encountered in a real planning and control environment: multiple simultaneous goals, parallel as well as sequential action execution, action sequencing determined not only by goals and their interactions but also by limited resources (e.g., three tasks, two acting agents), need to interpret unanticipated events and react appropriately through replanning, etc.

Dautrechy, C. Lynne↗
NASA NTRS1986

Algorithms and programming tools for image processing on the MPP, part 2

A number of algorithms were developed for image warping and pyramid image filtering. Techniques were investigated for the parallel processing of a large number of independent irregular shaped regions on the MPP. In addition some utilities for dealing with very long vectors and for sorting were developed. Documentation pages for the algorithms which are available for distribution are given. The performance of the MPP for a number of basic data manipulations was determined. From these results it is possible to predict the efficiency of the MPP for a number of algorithms and applications. The Parallel Pascal development system, which is a portable programming environment for the MPP, was improved and better documentation including a tutorial was written. This environment allows programs for the MPP to be developed on any conventional computer system; it consists of a set of system programs and a library of general purpose Parallel Pascal functions. The algorithms were tested on the MPP and a presentation on the development system was made to the MPP users group. The UNIX version of the Parallel Pascal System was distributed to a number of new sites.

Reeves, Anthony P.↗
DOE OSTI2024

Skipper-in-CMOS: Nondestructive Readout With Subelectron Noise Performance for Pixel Detectors

The Skipper-in-CMOS image sensor integrates the nondestructive readout capability of skipper charge coupled devices (Skipper-CCDs) with the high conversion gain of a pinned photodiode (PPD) in a CMOS imaging process while taking advantage of in-pixel signal processing. This allows both single photon counting as well as high frame rate readout through highly parallel processing. The first results obtained from a ${15} \times {15}~\mu $ m2 pixel cell of a Skipper-in-CMOS sensor fabricated in Tower Semiconductor’s commercial 180-nm CMOS image sensor process are presented. Measurements confirm the expected reduction of the readout noise with the number of samples down to deep subelectron noise of $0.15\text {e}^ - $ , demonstrating the charge transfer operation from the PPD and the single photon counting operation when the sensor is exposed to light. This article also discusses new testing strategies employed for its operation and characterization.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1987

Algorithm implementation on the Navier-Stokes computer

The Navier-Stokes Computer is a multi-purpose parallel-processing supercomputer which is currently under development at Princeton University. It consists of multiple local memory parallel processors, called Nodes, which are interconnected in a hypercube network. Details of the procedures involved in implementing an algorithm on the Navier-Stokes computer are presented. The particular finite difference algorithm considered in this analysis was developed for simulation of laminar-turbulent transition in wall bounded shear flows. Projected timing results for implementing this algorithm indicate that operation rates in excess of 42 GFLOPS are feasible on a 128 Node machine.

Krist, Steven E.↗
NASA NTRS1989

Concurrent processing simulation of the space station

The development of a new capability for the time-domain simulation of multibody dynamic systems and its application to the study of a large angle rotational maneuvers of the Space Station is described. The effort was divided into three sequential tasks, which required significant advancements of the state-of-the art to accomplish. These were: (1) the development of an explicit mathematical model via symbol manipulation of a flexible, multibody dynamic system; (2) the development of a methodology for balancing the computational load of an explicit mathematical model for concurrent processing; and (3) the implementation and successful simulation of the above on a prototype Custom Architectured Parallel Processing System (CAPPS) containing eight processors. The throughput rate achieved by the CAPPS operating at only 70 percent efficiency, was 3.9 times greater than that obtained sequentially by the IBM 3090 supercomputer simulating the same problem. More significantly, analysis of the results leads to the conclusion that the relative cost effectiveness of concurrent vs. sequential digital computation will grow substantially as the computational load is increased. This is a welcomed development in an era when very complex and cumbersome mathematical models of large space vehicles must be used as substitutes for full scale testing which has become impractical.

Gluck, R.↗