Simulation Infrastructure for Research on Interconnected Unmanned System (SIRIUS)
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María Consiglio↗
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Results for “interconnections”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Interconnected Hydrologic Extreme Drivers and Impacts Depicted By Remote Sensing Data Assimilation
In a changing climate, the likelihood of hydrologic extremes has been increasing as climate change can impact both means and extremes4 of hydrologic cycle processes, potentially resulting in an increased frequency of floods in some regions and decreases in others. In a warming world, the physical processes that affect hydrologic response, such as rain-on snow runoff events, are also changing, such that the seasonality of streamflow has been shifting. The geography of rain-on-snow runoff events is predicted to move from low to high elevations. In addition to floods, there is also potential for an increase in dry extremes in a warming world with increased drought frequency and occurrences in many parts of the world. The increased frequency of drought and heatwave events is expected to have consequences such as escalating crop failures in future projection scenarios1. Thus, the consensus of literature shows that climate change is increasing the magnitude and frequency of extreme hydrologic events, and the human influence in many of these events is substantial.
Timothy M. Lahmers↗
Development of an Adaptive Droop Control Method for Interconnected Lunar DC Microgrids Using Power Hardware-in-the-Loop
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dc microgrid↗
Wireless Interconnect CubeSat using Bluetooth Low Energy (BLE)
The Bluetooth Low Energy (BLE) subsystem controls the communication between boards on the CubeSat. It will replace wired Universal Asynchronous Receiver-Transmitter (UART) connections between Command and Data Handling (C&DH) and each subsystem. It allows us to only use one UART channel and reduces the length of commands sent to the subsystems.
wireless↗
Examination of Space Vehicle Ethernet Interconnects
The NASA Engineering and Safety Center (NESC) was requested to examine the performance of Ethernet in space vehicle configurations at the physical layer and develop guidance for system designers to ensure correct Ethernet operation in these systems. The objective of the assessment was to develop guidance and requirements for Ethernet cable and connectors for spaceflight environments and make recommendations for Ethernet systems used in flight-critical space applications. This report contains the results of the NESC assessment.
Ethernet↗
Integrating the Interconnections Between Groundwater and Land Surface Processes Through the Coupled NASA Land Information System and ParFlow Environment
Understanding the interactions between the atmosphere, the land, and the subsurface is fundamental to hydrology and is critical for a better assessment of the impacts of climate change and human management on hydrological systems. However, many land surface models simplify the subsurface hydrology and thereby these interactions. In this study, we couple the land surface model Noah-MP included in the NASA Land Information System (LIS) with the integrated hydrologic model ParFlow (ParFlow-LIS) using the Earth System Modeling Framework (ESMF) and the National United Operational Prediction Capability (NUOPC). This coupling improves the simulation of water and energy cycle processes by adding the three-dimensional variably saturated and heterogeneous flow in the subsurface using sophisticated and nonlinear physics-based equations as well as the advances in satellite remote sensing-based data assimilation of the land surface, thereby benefiting the integrated hydrologic modeling and data assimilation community. We use the High Plains aquifer, located in the central United States, as a testbed to evaluate the coupled ParFlow-LIS system. The new ParFlow-LIS system accounts for the effects of topographically driven flows on the land surface, producing more fine-scale patterns of land surface states and fluxes than standalone LIS. In addition, ParFlow-LIS enables the consideration of the effect of subsurface water storage on evapotranspiration. This is particularly important in areas and times with dry soils, such as during drought conditions or in the presence of a cone of depression due to pumping.
land surface modeling↗
Compositional performance certification of interconnected systems using ADMM
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Chris Meissen↗
Advanced Flip Chips in Extreme Temperature Environments
The use of underfill materials is necessary with flip-chip interconnect technology to redistribute stresses due to mismatching coefficients of thermal expansion (CTEs) between dissimilar materials in the overall assembly. Underfills are formulated using organic polymers and possibly inorganic filler materials. There are a few ways to apply the underfills with flip-chip technology. Traditional capillary-flow underfill materials now possess high flow speed and reduced time to cure, but they still require additional processing steps beyond the typical surface-mount technology (SMT) assembly process. Studies were conducted using underfills in a temperature range of -190 to 85 C, which resulted in an increase of reliability by one to two orders of magnitude. Thermal shock of the flip-chip test articles was designed to induce failures at the interconnect sites (-40 to 100 C). The study on the reliability of flip chips using underfills in the extreme temperature region is of significant value for space applications. This technology is considered as an enabling technology for future space missions. Flip-chip interconnect technology is an advanced electrical interconnection approach where the silicon die or chip is electrically connected, face down, to the substrate by reflowing solder bumps on area-array metallized terminals on the die to matching footprints of solder-wettable pads on the chosen substrate. This advanced flip-chip interconnect technology will significantly improve the performance of high-speed systems, productivity enhancement over manual wire bonding, self-alignment during die joining, low lead inductances, and reduced need for attachment of precious metals. The use of commercially developed no-flow fluxing underfills provides a means of reducing the processing steps employed in the traditional capillary flow methods to enhance SMT compatibility. Reliability of flip chips may be significantly increased by matching/tailoring the CTEs of the substrate material and the silicon die or chip, and also the underfill materials. Advanced packaging interconnects technology such as flip-chip interconnect test boards have been subjected to various extreme temperature ranges that cover military specifications and extreme Mars and asteroid environments. The eventual goal of each process step and the entire process is to produce components with 100 percent interconnect and satisfy the reliability requirements. Underfill materials, in general, may possibly meet demanding end use requirements such as low warpage, low stress, fine pitch, high reliability, and high adhesion.
Ramesham, Rajeshuni↗
Skylab observations of X-ray loops connecting separate active regions
One hundred loops interconnecting 94 separate active solar regions detectable in soft X-rays were identified during the Skylab mission. While close active regions are commonly interconnected with loops, the number of such interconnections decreases steeply for longer distances; the longest interconnecting loop observed in the Skylab data connected regions separated by 37 deg. Several arguments are presented which support the point of view that this is the actual limit of the size of magnetic interconnections between active regions. No sympathetic flares could be found in the interconnected regions. These results cast doubt on the hypothesis that accelerated particles can be guided in interconnecting loops from one active region to another over distances of 100 deg or more and eventually produce sympathetic flares in them.
Chase, R. C.↗
Pressurized bellows flat contact heat exchanger interface
Disclosed is an interdigitated plate-type heat exchanger interface. The interface includes a modular interconnect to thermally connect a pair or pairs of plate-type heat exchangers to a second single or multiple plate-type heat exchanger. The modular interconnect comprises a series of parallel, plate-type heat exchangers arranged in pairs to form a slot therebetween. The plate-type heat exchangers of the second heat exchanger insert into the slots of the modular interconnect. Bellows are provided between the pairs of fins of the modular interconnect so that when the bellows are pressurized, they drive the plate-type heat exchangers of the modular interconnect toward one another, thus closing upon the second heat exchanger plates. Each end of the bellows has a part thereof a thin, membrane diaphragm which readily conforms to the contours of the heat exchanger plates of the modular interconnect when the bellows is pressurized. This ensures an even distribution of pressure on the heat exchangers of the modular interconnect thus creating substantially planar contact between the two heat exchangers. The effect of the interface of the present invention is to provide a dry connection between two heat exchangers whereby the rate of heat transfer can be varied by varying the pressure within the bellows.
Voss, Fred E.↗
SpaceVPX Interoperability Assessment
The existing VMEbus (VersaModular Eurocard bus) International Trade Association (VITA)-78 industry standard, also known as SpaceVPX, is an avionics board- and chassis-level standard derived from the OpenVPX standard as defined in VITA-65. While VITA-65 defines backplane and board-level profiles from COTS vendors to ensure interoperability of products used in developing systems and subsystems, the VITA-78 standard defines SpaceVPX to incorporate fault tolerance features that are required by many spaceflight systems. However, VITA-78 allows so much flexibility that interoperability between modules cannot be assured. This assessment provides guidelines on the use of, and extensions to, the VITA-78 standard to enable avionics interoperability for future NASA missions. The assessment team was comprised of subject matter experts (SMEs) from Goddard Space Flight Center (GSFC), the Jet Propulsion Laboratory (JPL), Johnson Space Center (JSC), and Langley Research Center (LaRC). The team included valuable external consulting support from a SME who was a key participant in the development of the VITA-78 standard. The team had extensive collaboration with the NASA Space Technology Mission Directorate (STMD) High Performance Spaceflight Computing (HPSC) project, specifically in the development of SpaceVPX interconnect findings, observations, and NESC recommendations. To provide an understanding of the breadth of implementations that SpaceVPX must accommodate, multiple NASA use cases were analyzed to assess the requirements for SpaceVPX implementations across a wide range of NASA missions (Appendix C). Applications included crewed missions, science missions, and orbital and surface robotic systems. Product surveys were conducted to assess the level of industry support for SpaceVPX, applications, and the variations in their implementations (Appendix D). In-depth analysis was conducted in the areas of: (a) power management and distribution, (b) form factors and daughtercards, (c) interconnect, and (d) fault tolerance. Leveraging the use cases, product surveys, and SMEs from multiple NASA Centers, these areas were analyzed to determine the range of implementations permitted by the VITA-78 standard and potential interoperability issues. Applicable findings and NESC recommendations were provided for each area. During this assessment, there were multiple opportunities to engage with other agencies to learn about their interest in SpaceVPX, their strategies for implementing SpaceVPX-based systems, and their internal development efforts. These engagements also generated findings and NESC recommendations. Based on this assessment analysis, NESC recommendations were made regarding the feature set and module profiles to support NASA SpaceVPX implementations. This feature set includes restrictions on features in VITA-78, and extensions to the standard. Key recommendations in this area include the use of 10 Gigabit Ethernet and Peripheral Component Interconnect Express (PCIe) as high bandwidth interconnect on the backplane, the retention of SpaceWire interconnect for control functions, and support for 3U (unit) and 6U, form factors for NASA systems. Restrictions were proposed on the usage of user-defined signals to promote interoperability, and specific power managements and distribution schemes for 3U systems. Beyond the technical implementation of SpaceVPX, recommendations were made on areas that warrant further investigation. Primary among these is the recommendation for NASA to collaborate with other space-going agencies and industry to incorporate recommendations into a future ‘dot spec’ of VITA-78. This would ensure wide adoption and availability of the modules that comply with the specification. The assessment includes appendices with candidate module profiles that can be considered as a starting point for this activity, and example systems based on the recommendations. Follow-on studies are recommended for architectures beyond SpaceVPX to address potential enhancements including condensed set of interconnect, software required to implement protocol layers on the interconnect (and other features), alternative power architectures, and system-level testability.
SpaceVPX↗
Flexible, FEP-Teflon covered solar cell module development
Techniques and equipment were developed for the large scale, low-cost fabrication of lightweight, roll-up and fold-up, FEP-Teflon encapsulated solar cell modules. Modules were fabricated by interconnecting solderless single-crystal silicon solar cells and heat laminating them at approximately 300 C between layers of optically clear FEP and to a loadbearing Kapton substrate sheet. Modules were fabricated from both conventional and wraparound contact solar cells. A heat seal technique was developed for mechanically interconnecting modules into an array. The electrical interconnections for both roll-up and fold-up arrays were also developed. The use of parallel-gap resistance welding, ultrasonic bonding, and thermocompression bonding processes for attaching interconnects to solar cells were investigated. Parallel-gap welding was found to be best suited for interconnecting the solderless solar cells into modules. Details of the fabrication equipment, fabrication processes, module and interconnect designs, environmental test equipment, and test results are presented.
Rauschenbach, H. S.↗
Solar array arcing in plasmas
Solar cells in space plasma conditions are known to arc into the plasma when the interconnects are at a negative potential of a few hundred volts, relative to plasma potential. For cells with silver-coated interconnects, a threshold voltage for arcing exists at about -230 V, as found in both ground and LEO experiments. The arc rate beyond the threshold voltage depends nearly linearly on plasma density, but has a strong power-law dependence on voltage, such that for small increments in operating voltage there is a large increment in arc rate. The arcs generate broadband radio interference and visible light. In ground tests, interconnects have been damaged by arcs in cells having insufficient isolation from a source of high current. Models for the arcs are highly dependent on the choice of interconnect conductor material exposed to the plasma and possibly on the geometry and choice of adjacent insulator material. Finally, new technology solar cells use copper for the cell interconnects, a material which may have a lower arcing threshold voltage than silver. It is expected, from ground tests of simulated solar cells, that any junction of conductor and insulator exposed to space plasma conditions will arc into the plasma at a few hundred volts negative potential, relative to the local plasma.
Ferguson, Dale C.↗
Novel Highly Parallel and Systolic Architectures Using Quantum Dot-Based Hardware
VLSI technology has made possible the integration of massive number of components (processors, memory, etc.) into a single chip. In VLSI design, memory and processing power are relatively cheap and the main emphasis of the design is on reducing the overall interconnection complexity since data routing costs dominate the power, time, and area required to implement a computation. Communication is costly because wires occupy the most space on a circuit and it can also degrade clock time. In fact, much of the complexity (and hence the cost) of VLSI design results from minimization of data routing. The main difficulty in VLSI routing is due to the fact that crossing of the lines carrying data, instruction, control, etc. is not possible in a plane. Thus, in order to meet this constraint, the VLSI design aims at keeping the architecture highly regular with local and short interconnection. As a result, while the high level of integration has opened the way for massively parallel computation, practical and full exploitation of such a capability in many applications of interest has been hindered by the constraints on interconnection pattern. More precisely. the use of only localized communication significantly simplifies the design of interconnection architecture but at the expense of somewhat restricted class of applications. For example, there are currently commercially available products integrating; hundreds of simple processor elements within a single chip. However, the lack of adequate interconnection pattern among these processing elements make them inefficient for exploiting a large degree of parallelism in many applications.
Fijany, Amir↗
Thermophotovoltaic Cell Technology Transferred to the Department of Energy Laboratory and a Commercial Manufacturer
Researchers in the NASA Lewis Research Center's Photovoltaic Branch have developed novel photovoltaic device, called a Monolithically Interconnected Module (MIM), for use in thermophotovoltaic (TPV) power systems. TPV power systems function by heating an emitter to produce light. This light is then converted into electricity by a photovoltaic device or a solar cell. Possible heat sources for the system include concentrated solar energy, the combustion of various fuels, and nuclear decay. NASA has an interest in TPV systems for deep space (nuclear-powered) and near-Sun (solar-powered) missions. There also are many commercial and military applications for TPV, given its potential for high efficiency, low noise, and reliable power. The Monolithically Interconnected Module consists of many small solar cells that are series-interconnected on a common substrate. The cells are fabricated from indium gallium arsenide (InGaAs), which can convert the near-infrared portion of the emitter output spectrum into electricity. The InGaAs devices are deposited on an indium phosphide (InP) substrate that provides electrical isolation. On the bottom the InP substrate is an infrared reflector that returns all the photons that are not converted by the InGaAs device back to the emitter where they are absorbed. This process helps maintain the emitter temperature and dramatically improves the system efficiency. Monolithically Interconnected Module InGaAs thermophotovoltaic cell developed by Lewis. Compared with conventional TPV cells, this TPV device has higher output voltages and lower resistive losses, higher output power density, simplified thermal management, improved reliability, and higher efficiency. The Monolithically Interconnected Module was initially developed under an internally funded effort (Director's Discretionary Fund). Development is now being funded by another government agency, and prototype devices are being produced by a commercial solar cell manufacturer.
Wilt, David M.↗
Progress in High Power Density SOFC Material Development for Aerospace Applications
Solid oxide fuel cell (SOFC) systems for aircraft applications require order of magnitude increase in specific power density and long life under aircraft operating conditions. Advanced SOFC materials and fabrication processes are being developed at NASA GRC to increase specific power density and durability of SOFC cell and stack. Initial research efforts for increasing specific power density are directed toward increasing the operating temperature for the SOFC system and reducing the weight of the stack. While significant research is underway to develop anode supported SOFC system operating at temperatures in the range of 650 - 850 C for ground power generation applications, such temperatures may not yield the power densities required for aircraft applications. For electrode-supported cells, SOFC stacks with power densities greater than 1.0 W/sq cm are favorable at temperatures in excess of 900 C. The performance of various commercial and developmental anode supported cells is currently being evaluated in the temperature range of 900 to 1000 C to assess the performance gains and materials reliability. The results from these studies will be presented. Since metal interconnects developed for lower temperature operation are not practical at these high temperatures, advanced perovskite based ceramic interconnects with high electronic conductivity and lower sintering temperatures are being developed. Another option for increasing specific power density of SOFC stacks is to decrease the stack weight. Since the interconnect contributes to a significant portion of the stack weight, considerable weight benefits can be derived by decreasing its thickness. Eliminating the gas channels in the interconnect by engineering the pore structure in both anode and cathode can offer significant reduction in thickness of the ceramic interconnect material. New solid oxide fuel cells are being developed with porous engineered electrode supported structures with a 10 - 20 micron thin electrolyte. The performance data for advanced SOFC cells with engineered porosity in both electrodes will be presented.
Cable, Thomas L.↗
Packaging Technology Designed, Fabricated, and Assembled for High-Temperature SiC Microsystems
A series of ceramic substrates and thick-film metalization-based prototype microsystem packages designed for silicon carbide (SiC) high-temperature microsystems have been developed for operation in 500 C harsh environments. These prototype packages were designed, fabricated, and assembled at the NASA Glenn Research Center. Both the electrical interconnection system and the die-attach scheme for this packaging system have been tested extensively at high temperatures. Printed circuit boards used to interconnect these chip-level packages and passive components also are being fabricated and tested. NASA space and aeronautical missions need harsh-environment, especially high-temperature, operable microsystems for probing the inner solar planets and for in situ monitoring and control of next-generation aeronautical engines. Various SiC high-temperature-operable microelectromechanical system (MEMS) sensors, actuators, and electronics have been demonstrated at temperatures as high as 600 C, but most of these devices were demonstrated only in the laboratory environment partially because systematic packaging technology for supporting these devices at temperatures of 500 C and beyond was not available. Thus, the development of a systematic high-temperature packaging technology is essential for both in situ testing and the commercialization of high-temperature SiC MEMS. Researchers at Glenn developed new prototype packages for high-temperature microsystems using ceramic substrates (aluminum nitride and 96- and 90-wt% aluminum oxides) and gold (Au) thick-film metalization. Packaging components, which include a thick-film metalization-based wirebond interconnection system and a low-electrical-resistance SiC die-attachment scheme, have been tested at temperatures up to 500 C. The interconnection system composed of Au thick-film printed wire and 1-mil Au wire bond was tested in 500 C oxidizing air with and without 50-mA direct current for over 5000 hr. The Au thick-film metalization-based wirebond electrical interconnection system was also tested in an extremely dynamic thermal environment to assess thermal reliability. The I-V curve1 of a SiC high-temperature diode was measured in oxidizing air at 500 C for 1000 hr to electrically test the Au thick-film material-based die-attach assembly.
Chen, Liang-Yu↗