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All sources NASA NTRS DOE OSTI

NASA NTRS2001

Status of the Direct Data Distribution (D(exp 3)) Experiment

NASA Glenn Research Center's Direct Data Distribution (D3) project will demonstrate an advanced, high-performance communications system that transmits information from an advanced technology payload carried by a NASA spacecraft in low Earth orbit (LEO) to a small receiving terminal on Earth. The space-based communications package will utilize a solid-state, K-band phased-array antenna that electronically steers the radiated energy beam toward a low-cost, tracking ground terminal, thereby providing agile, vibration-free, electronic steering at reduced size and weight with increased reliability. The array-based link will also demonstrate new digital processing technology that will allow the transmission of substantially increased amounts of latency-tolerant data collected from the LEO spacecraft directly to NASA field centers, principal investigators, or into the commercial terrestrial communications network. The technologies demonstrated by D3 will facilitate NASA's transition from using Government-owned communication assets to using commercial communication services. The hardware for D3 will incorporate advanced technology components developed under the High Rate Data Delivery (HRDD) Thrust Area of NASA's Office of Aerospace Technology Space Base Program at Glenn's Communications Technology Division. The flight segment components will include the electrically steerable phased-array antenna, which is being built by the Raytheon System Corporation and utilizes monolithic microwave integrated circuit (MMIC) technology operating at 19.05 GHz; and the digital encoder/modulator chipset, which uses four-channel orthogonal frequency division multiplexing (OFDM). The encoder/modulator will use a chipset developed by SICOM, Inc., which is both bandwidth and power efficient. The ground segment components will include a low-cost, open-loop tracking ground terminal incorporating a cryoreceiver to minimize terminal size without compromising receiver capability. The project is planning to hold a critical design review in the second quarter of fiscal year 2002.

Wald, Lawrence↗

NASA NTRS1994

Development of a Power Electronics Unit for the Space Station Plasma Contactor

A hollow cathode plasma contactor has been baselined as a charge control device for the Space Station (SS) to prevent deleterious interactions of coated structural components with the ambient plasma. NASA LeRC Work Package 4 initiated the development of a plasma contactor system comprised of a Power Electronics Unit (PEU), an Expellant Management Unit (EMU), a command and data interface, and a Plasma Contactor Unit (PCU). A breadboard PEU was designed and fabricated. The breadboard PEU contains a cathode heater and discharge power supply, which were required to operate the PCU, a control and auxiliary power converter, an EMU interface, a command and telemetry interface, and a controller. The cathode heater and discharge supplies utilized a push-pull topology with a switching frequency of 20 kHz and pulse-width-modulated (PWM) control. A pulse ignition circuit derived from that used in arcjet power processors was incorporated in the discharge supply for discharge ignition. An 8088 based microcontroller was utilized in the breadboard model to provide a flexible platform for controller development with a simple command/data interface incorporating a direct connection to SS Mulitplexer/Demultiplexer (MDM) analog and digital I/O cards. Incorporating this in the flight model would eliminate the hardware and software overhead associated with a 1553 serial interface. The PEU autonomously operated the plasma contactor based on command inputs and was successfully integrated with a prototype plasma contactor unit demonstrating reliable ignition of the discharge and steady-state operation.

Hamley, John A.↗

DOE OSTI2021

A 24-Channel Digitizer With a JESD204B-Compliant Serial Interface for High-Speed Detectors

In this report a 24-channel application-specific integrated circuit (ASIC) for the readout of high-speed CMOS active pixel sensors for charged particle detection is presented. The chip comprises 24 preamplifiers, 24 distinct 12-bit, 25 MSPS Pipelined analog-to-digital converters (ADCs) with self-calibration, an internal phase-locked loop (PLL), and a 3 Gbps serial interface that conforms to the JESD204B standard. To simplify interfacing with a variety of sensors, the ASIC also includes an automatic offset calibration loop. The high level of integration of the ASIC reduces overall system cost and area, and exploiting the signal characteristics of the image sensor allows the ADC to be optimized for reduced power dissipation. The use of an integrated serializer and an industry standard protocol simplifies integration of the ASIC into a complete camera system. The ASIC, called the High-Speed Image Preprocessor Targeted for Electron Readout, or HIPSTER, with a die area of 64.26 mm 2 , is packaged in a 480-ball grid array (BGA) and is fabricated in 180-nm CMOS technology. HIPSTER achieves typical differential nonlinearity (DNL) < 0.55 LSB, input-referred thermal noise of $114.5 μV-rms, and a bit error rate (BER) of better than 10-14. The power dissipation is 98 mW/channel.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

NASA NTRS2000

Development of a Two Dimensional Synthetic Aperture Radiometer at L-Band

A radiometer that uses aperture synthesis in two dimensions is being built as part of research under NASA's Instrument Incubator Program. The instrument development team consists of engineers at the Goddard Space Flight Center, the University of Massachusetts and Quadrant Engineering. This will be an aircraft instrument operating at L-band which builds on the heritage of Electronically Steered Thinned Array Radiometer (ESTAR). This instrument is a next step in the development of aperture synthesis (STAR technology) to meet the goal of a future mission to monitor soil moisture globally from space. The instrument will be designed to fly on the NASA P-3 aircraft in a nadir pointing mode, although other options are possible. The antenna will consist of an array of modules in a rectangular grid. Each module will be comprised of a printed circuit dual-polarized patch and integrated receiver. The distribution of modules within the rectangular array will be adjustable so that several different imaging configurations (e.g. '+', 'Y', 'T') can be employed. The integrated receiver will provide amplification and conversion to infrared (IF). The IF signal will be routed to a processor where the required correlations performed. The I and Q channels will be created digitally and the correlations will be done digitally in this processor. The digitization will be done with sufficient bits to study the effects of quantization on radiometer performance. A computer/controller will store the data for conversion to an image and will also perform temperature control and other data interfacing and housekeeping tasks. The design of critical components has been completed and hardware is being assembled to test the individual elements. It is expected that a complete two-channel correlator will be tested by the end of 2000 and that the complete instrument will be ready for flight tests the following summer (2001).

LeVine, D. M.↗

NASA NTRS1996

Microelectromechanical Systems for Aerodynamics Applications

Microelectromechanical systems (MEMS) embody the integration of sensors, actuators, and electronics on a single substrate using integrated circuit fabrication techniques and compatible micromachining processes. Silicon and its derivatives form the material base for the MEMS technology. MEMS devices, including micro-sensors and micro-actuators, are attractive because they can be made small (characteristic dimension about microns), be produced in large numbers with uniform performance, include electronics for high performance and sophisticated functionality, and be inexpensive. MEMS pressure sensors, wall-shear-stress sensors, and micromachined hot-wires are nearing application in aeronautics. MEMS actuators face a tougher challenge since they have to be scaled (up) to the physical phenomena that are being controlled. MEMS actuators are proposed, for example, for controlling the small structures in a turbulent boundary layer, for aircraft control, for cooling, and for mixing enhancement. Data acquisition or control logistics require integration of electronics along with the transducer elements with appropriate consideration of analog-to-digital conversion, multiplexing, and telemetry. Altogether, MEMS technology offers exciting opportunities for aerodynamics applications both in wind tunnels and in flight

Mehregany, Mehran↗

NASA NTRS2005

Software-Reconfigurable Processors for Spacecraft

A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

Farrington, Allen↗

NASA NTRS2018

Building Reliable Printed Circuit Boards - the Lessons Learned

"Printed circuit boards (PCBs) are the baseline for electronics manufacturing upon which electronic components are mounted and formed into electronic systems. PCBs are used in a variety of electronic circuits from simple one-transistor amplifiers to large super computers. A PCB serves three main functions: 1) it provides the necessary mechanical support for the components in the circuit 2) it provides the necessary electrical interconnections, and 3) it bears some form of legend which identifies the components it carries. The failure modes on the PCBs can be categorized in a hierarchical structure, in which the mechanisms and causes are site or location dependant. This one day workshop will discuss a variety of failure mechanisms that effect the functionality of PCBs. These mechanisms can be related to how PCB materials are selected, PCBs are designed, manufactured, tested and used in the field conditions. The workshop will begin with an overview of PCB manufacturing, materials and processes. With the help of examples and case studies, a wide range of failure mechanisms will be discussed, case studies are focused on digital circuits, however some failures in analog, double sided boards are also presented. The workshop then provides the guideline for selection of methodologies for identifying potential failure mechanisms based on the failure history and how a systematic root cause failure analysis of the PCB can result in prevention of future issues."

Sood, Bhanu↗

NASA NTRS2008

On-Wafer Measurement of a Silicon-Based CMOS VCO at 324 GHz

The world s first silicon-based complementary metal oxide/semiconductor (CMOS) integrated-circuit voltage-controlled oscillator (VCO) operating in a frequency range around 324 GHz has been built and tested. Concomitantly, equipment for measuring the performance of this oscillator has been built and tested. These accomplishments are intermediate steps in a continuing effort to develop low-power-consumption, low-phase-noise, electronically tunable signal generators as local oscillators for heterodyne receivers in submillimeter-wavelength (frequency > 300 GHz) scientific instruments and imaging systems. Submillimeter-wavelength imaging systems are of special interest for military and law-enforcement use because they could, potentially, be used to detect weapons hidden behind clothing and other opaque dielectric materials. In comparison with prior submillimeter- wavelength signal generators, CMOS VCOs offer significant potential advantages, including great reductions in power consumption, mass, size, and complexity. In addition, there is potential for on-chip integration of CMOS VCOs with other CMOS integrated circuitry, including phase-lock loops, analog- to-digital converters, and advanced microprocessors.

Samoska, Lorene↗

DOE OSTI2024

Cryogenic Front-End ASICs for Low-Noise Readout of Charge Signals

This paper presents design details and measurement results of LArASIC, a front-end application specific integrated circuit (ASIC) designed for low-noise readout of charge signals generated in neutrino study experiments within liquid argon time projection chambers. LArASIC comprises of 16-channels of programmable charge amplification and pulse shaping stages that provide a voltage readout proportional to the input charge and was optimized for operation at liquid argon temperature, i.e., 89 K. The chip was fabricated in a 180 nm CMOS process. Measurements at liquid nitrogen temperature, i.e., 77 K, indicate that the channel outputs have high linearity (INL < 0.1%) within the operating range, an equivalent noise charge of 534 electrons for a peaking time of 1 µs and a detector capacitance of 150 pF, and a worst-case inter-channel cross-talk of 0.35%. The paper also presents design choices made in the process of migrating LArASIC to CHARMS, an ASIC to be fabricated in a 65 nm process that includes all features provided by LArASIC, along with additional digital programmability for improved robustness and flexibility. CHARMS is intended for use in future high-energy physics experiments that require high-resolution charge or light readout with shorter pulse peaking times.

47 OTHER INSTRUMENTATION↗

NASA NTRS2001

Flight Computer Design for the Space Technology 5 (ST-5) Mission

As part of NASA's New Millennium Program, the Space Technology 5 mission will validate a variety of technologies for nano-satellite and constellation mission applications. Included are: a miniaturized and low power X-band transponder, a constellation communication and navigation transceiver, a cold gas micro-thruster, two different variable emittance (thermal) controllers, flex cables for solar array power collection, autonomous groundbased constellation management tools, and a new CMOS ultra low-power, radiation-tolerant, +0.5 volt logic technology. The ST-5 focus is on small and low-power. A single-processor, multi-function flight computer will implement direct digital and analog interfaces to all of the other spacecraft subsystems and components. There will not be a distributed data system that uses a standardized serial bus such as MIL-STD-1553 or MIL-STD-1773. The flight software running on the single processor will be responsible for all real-time processing associated with: guidance, navigation and control, command and data handling (C&DH) including uplink/downlink, power switching and battery charge management, science data analysis and storage, intra-constellation communications, and housekeeping data collection and logging. As a nanosatellite trail-blazer for future constellations of up to 100 separate space vehicles, ST-5 will demonstrate a compact (single board), low power (5.5 watts) solution to the data acquisition, control, communications, processing and storage requirements that have traditionally required an entire network of separate circuit boards and/or avionics boxes. In addition to the New Millennium technologies, other major spacecraft subsystems include the power system electronics, a lithium-ion battery, triple-junction solar cell arrays, a science-grade magnetometer, a miniature spinning sun sensor, and a propulsion system.

Speer, David↗

NASA NTRS2007

G4-FETs as Universal and Programmable Logic Gates

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Johnson, Travis↗

NASA NTRS2012

NASA Tech Briefs, August 2012

Topics covered include: Mars Science Laboratory Drill; Ultra-Compact Motor Controller; A Reversible Thermally Driven Pump for Use in a Sub-Kelvin Magnetic Refrigerator; Shape Memory Composite Hybrid Hinge; Binding Causes of Printed Wiring Assemblies with Card-Loks; Coring Sample Acquisition Tool; Joining and Assembly of Bulk Metallic Glass Composites Through Capacitive Discharge; 670-GHz Schottky Diode-Based Subharmonic Mixer with CPW Circuits and 70-GHz IF; Self-Nulling Lock-in Detection Electronics for Capacitance Probe Electrometer; Discontinuous Mode Power Supply; Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI; Hardware for Accelerating N-Modular Redundant Systems for High-Reliability Computing; Blocking Filters with Enhanced Throughput for X-Ray Microcalorimetry; High-Thermal-Conductivity Fabrics; Imidazolium-Based Polymeric Materials as Alkaline Anion-Exchange Fuel Cell Membranes; Electrospun Nanofiber Coating of Fiber Materials: A Composite Toughening Approach; Experimental Modeling of Sterilization Effects for Atmospheric Entry Heating on Microorganisms; Saliva Preservative for Diagnostic Purposes; Hands-Free Transcranial Color Doppler Probe; Aerosol and Surface Parameter Retrievals for a Multi-Angle, Multiband Spectrometer LogScope; TraceContract; AIRS Maps from Space Processing Software; POSTMAN: Point of Sail Tacking for Maritime Autonomous Navigation; Space Operations Learning Center; OVERSMART Reporting Tool for Flow Computations Over Large Grid Systems; Large Eddy Simulation (LES) of Particle-Laden Temporal Mixing Layers; Projection of Stabilized Aerial Imagery Onto Digital Elevation Maps for Geo-Rectified and Jitter-Free Viewing; Iterative Transform Phase Diversity: An Image-Based Object and Wavefront Recovery; 3D Drop Size Distribution Extrapolation Algorithm Using a Single Disdrometer; Social Networking Adapted for Distributed Scientific Collaboration; General Methodology for Designing Spacecraft Trajectories; Hemispherical Field-of-View Above-Water Surface Imager for Submarines; and Quantum-Well Infrared Photodetector (QWIP) Focal Plane Assembly.

Source record↗

DOE OSTI2024

ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade

We present the design and characterization of the first fullchain precision timing prototype ASIC, named ETL Readout Chipversion 1 (ETROC1) for the CMS MTD endcap timing layer (ETL)upgrade. The ETL utilizes Low Gain Avalanche Diode (LGAD) sensors todetect charged particles, with the goal to achieve a time resolutionof 40–50 ps per hit, and 30–40 ps per track with hits from twodetector layers. The ETROC1 is composed of a 5 × 5 pixelarray and peripheral circuits. The pixel array includes a4 × 4 active pixel array with an H-tree shaped networkdelivering clock and charge injection signals. Each active pixel iscomposed of various components, including a bump pad, a chargeinjection circuit, a pre-amplifier, a discriminator, adigital-to-analog converter, and a time-to-digital converter. Thesecomponents play essential roles as the front-end link in processingLGAD signals and measuring timing-related information. Theperipheral circuits provide clock signals and readoutfunctionalities. The size of the ETROC1 chip is7 mm× 9 mm. ETROC1 has been fabricated in a 65 nmCMOS process, and extensively tested under stimuli of chargeinjection, infrared laser, and proton beam. The time resolution ofbump-bonded ETROC1 + LGAD chipsets reaches 42–46 ps per hit in thebeam test.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2025

Semiconductor-compatible topological digital alloys

Recently, GeSn alloys have attracted much interest for direct-gap infrared photonics and as potential topological materials which are compatible with the semiconductor industry. However, for photonics, the high-Sn content required leads to low detectivity, associated with poor material quality, and the (>35 %) Sn required for topological properties have been out of reach experimentally. Here, we demonstrate that by patterning the Sn distribution within Ge, the electronic properties have a far greater tunability than is possible with the random alloy. For the GeSn δ-digital alloy (DA) formed by confining Sn atoms in atomic layer(s) along the [111] direction of Ge, we show that ∼ 10 % Sn can lead to a triple-point semimetal. These findings are understood in terms of Sn ordering causing spatial separation of Sn and Ge band edges, leading to band inversion. This mechanism can also lead to a weak topological insulator, Weyl semimetal, and enables tunable direct bandgaps down to 2 meV, covering the entire infrared range. This DA induced topological properties are also identified in compound semiconductors, such as InAs 1-x Sb x , showing the general applicability of the DA design for realizing topological properties on conventional semiconductor platforms. Furthermore, our findings not only point to a new class of currently unexplored topological systems accessible by epitaxy, but also establish the promise of low-Sn GeSn DAs for application as infrared laser diodes and photodetectors in Si photonic integrated circuits and infrared image sensors.

3D topological semimetal↗

NASA NTRS2023

Development of a Field-Deployable Microphone Phased Array for Airframe Noise Flyover Measurements

This technical memorandum describes in detail the construction and use of a large channel-count, field-deployable microphone phased array designed for airframe noise flyover measurements for a range of aircraft types and scales. The array incorporated 185 hardened, weather-resistant sensors suitable for outdoor use. A custom 4-mA current loop receiver circuit with temperature compensation was developed to power the sensors over extended cable lengths with minimal loss of signal-to-noise. Extensive calibrations and performance testing of the sensors were conducted to verify the design specifications. A compact data system combining sensor power, signal conditioning, and digitization was assembled for use with the array. Complementing the data system was a robust analysis system capable of near real-time presentation of beamformed and deconvolved contour plots and integrated spectra obtained from data acquired during flyover passes of the array. Additional instrumentation systems needed to process the array data were also developed, including a commercial 10-meter weather station comprised of a sonic anemometer, aspirated temperature/humidity probe and pressure sensor. Unique methods for assessing the health of the array in-situ were developed and demonstrated. A detailed mock-up of the instrumentation suite (phased array, weather station, and data processor) was performed in the NASA Langley Acoustic Development Laboratory in 2014 to vet the system performance. Issues with the sensors and electronics were identified during the mock-up and subsequently corrected. The array was then deployed for preliminary field testing at Fort A.P. Hill in Virginia in 2015 followed by the array being utilized in three separate full-scale airframe noise test campaigns at Edwards Air Force Base in California from 2016 to 2018 where the system was used to characterize the noise generated by both baseline and treated flaps and main landing gear on a commercial transport-sized vehicle.

Phased Array↗

DOE OSTI2022

The VMM3a ASIC

The VMM3a is a custom low-noise Application Specific Integrated Circuit. It is intended to be used in the front end readout electronics of both the Micromegas and sTGC detectors of the ATLAS New Small Wheels upgrade project at CERN. It is fabricated in the 130 nm GlobalFoundries 8RF-DM process. Here, the 64 channels with highly configurable parameters, although designed for a specific project, can meet the processing needs of signals from various detector types in several other applications. In this note, the VMM3a, which is the production version of the VMM family, will be presented along with the features incorporated and its performance.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2026

Analog-to-digital converter based on voltage-controlled superconducting devices

The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.

Analog-to-digital converter↗

NASA NTRS2011

Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

Strickland, S. M.↗