Results for “digital circuits designs” — Page 15

NASA NTRS2001

Relative Navigation for Formation Flying of Spacecraft

This paper presents a robust and efficient approach for relative navigation and attitude estimation of spacecraft flying in formation. This approach uses measurements from a new optical sensor that provides a line of sight vector from the master spacecraft to the secondary satellite. The overall system provides a novel, reliable, and autonomous relative navigation and attitude determination system, employing relatively simple electronic circuits with modest digital signal processing requirements and is fully independent of any external systems. Experimental calibration results are presented, which are used to achieve accurate line of sight measurements. State estimation for formation flying is achieved through an optimal observer design. Also, because the rotational and translational motions are coupled through the observation vectors, three approaches are suggested to separate both signals just for stability analysis. Simulation and experimental results indicate that the combined sensor/estimator approach provides accurate relative position and attitude estimates.

Alonso, Roberto↗

NASA NTRS1981

Development of design, qualification, screening, and application requirements for plastic encapsulated solid-state devices for space applications

Test data were collected on 1035 plastic encapsulated devices and 75 hermetically scaled control group devices that were purchased from each of five different manufacturers in the categories of (1) low power Schottsky TTL (bipolar) digital circuits; (2) CMOS digital circuits; (3) operational amplifier linear circuits; and (4) NPN transistors. These parts were subjected to three different initial screening conditions, then to extended life testing, to determine any possible advantages or trends for any particular screen. Several tests were carried out in the areas of flammability testing, humidity testing, high pressure steam (auroclave) testing, and high temperature storage testing. Test results are presented. Procurement and application considerations for use of plastic encapsulated semiconductors are presented and a statistical analysis program written to study the log normal distributions resulting from life testing is concluded.

Source record↗

NASA NTRS1972

Light-detection electronics for a Raman lidar

A light-detection system for an optical radar, or lidar, unit to be used for remote temperature and composition measurements was designed, built, and bench tested. This detection system processes three return signal wavelengths: two Raman wavelengths, and the Rayleigh-Mie wavelength at 694.3 nanometers. Means of coping with photomultiplier tube instabilities and limitations are discussed. Circuits for gain control, ranging, and digitizing are included. The phototube gains can be switched fully on in 80 meters (450 nsec) or off in 30 meters (200 nsec) of range. The range circuit processes signals from 0.1 to 2 kilometers, with an estimated range resolution of less than 5 meters.

Leser, R. J.↗

NASA NTRS1986

DSP-based non-coherent dual detector demodulator for land mobile radio channels

This paper outlines the development of a digital demodulator suitable for the non-coherent detection of various modulation formats including: Phase Shift Keying (PSK), Continuous Phase Frequency Shift Keying (CPFSK) and Frequency Modulation (FM). The demodulator design concept has been derived with a view towards a single integrated circuit (IC) implementation. Two detectors, one non-coherent and one differentially coherent, operate concurrently, providing data detection and automatic frequency control (AFC). Bit error rate results are provided which illustrate the receiver performance in white Gaussian noise.

Saulnier, Gary J.↗

NASA NTRS1989

SEU In An Advanced Bipolar Integrated Circuit

Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

Zoutendyk, John A.↗

NASA NTRS1993

Total Ionizing Dose Effects in 12-Bit Successive-Approximation Analog-To-Digital Converters

Analog-to-digital (A/D) converters are critical components in many space and military systems, and there have been numerous advances in A/D converter technology that have increased the resolution and conversion time. The increased performance is due to two factors: (1) advances in circuit design and complexity, which have increased the number of components and the integration density; and (2) new process technologies, such as BiCMOS, which provide better performance, cost, and smaller size in mixed-signal circuits. High-speed A/D converters, with conversion rates above 1 MHz, present a challenge to circuit designers and test engineers. Their complex architectures and high-performance specifications result in numerous possible failure modes when they are subjected to ionizing radiation. The dominant failure mode may depend on the specific application because the fundamental effects on MOS and bipolar transistors are strongly affected by bias conditions.

Lee, C. I.↗

NASA NTRS2005

Reconfiguration of Analog Electronics for Extreme Environments: Problem or Solution?

This paper argues in favor of adaptive reconfiguration as a technique to expand the operational envelope of analog electronics for extreme environments (EE). In addition to hardening-by-process and hardening-by-design, "hardening-by-reconfiguration", when applicable, could be used to mitigate drifts, degradation, or damage on electronic devices (chips) in EE, by using re-configurable devices and an adaptive self-reconfiguration of their circuit topology. Conventional circuit design exploits device characteristics within a certain temperature/radiation range; when that is exceeded, the circuit function degrades. On a reconfigurable device, although component parameters change in EE, as long as devices still operate, albeit degraded, a new circuit design, suitable for new parameter values, may be mapped into the reconfigurable structure to recover the initial circuit function. Partly degraded resources are still used, while completely damaged resources are bypassed. Designs suitable for various environmental conditions can be determined prior to operation or can be determined in-situ, by adaptive reconfiguration algorithms running on built-in digital controllers. Laboratory demonstrations of this technique were performed by JPL in several independent experiments in which bulk CMOS reconfigurable devices were exposed to, and degraded by, low temperatures (approx. 196 C), high temperatures (approx.300 C) or radiation (300kRad TID), and then recovered by adaptive reconfiguration using evolutionary search algorithms. Taking this technology from Technology Readiness Level (TRL) 3 to TRL 5 is the target of a current NASA project.

Field Programmable Transistor Array (FPTA)↗

NASA NTRS1977

A digital goniometer for VOR

A new VOR (VHF omni-range) goniometer design which promises to improve the reliability and maintainability of the VOR ground station is described. The heart of the new concept is the use of two digital phase shifters to produce the rotating figure-of-eight pattern of conventional VOR. Using digital circuits, the goniometer adjustments and calibration reduce to timing adjustments of binary signals. A common clock used for timing the digital phase shifters also synchronizes the 30 Hz modulation of the 9.96 kHz reference.

Meer, S. A.↗

NASA NTRS1980

Payload/orbiter signal processing and data handling system evaluation presentation

It is recommended that standard digital and along interfaces be adopted. These include: (1) define interfaces compatible with NASA/DOD/industry-accepted design standards; (2) investigate costs of modifying orbiter sybsystem interfaces, (3) investigate cost of designing attached payload interface unit for NASA and commercial payloads and (4) investigate costs of designing interface circuits that can be incorporated into each payload design.

Source record↗

DOE OSTI2026

Versatile High-Gain Low-Noise Readout ASIC for Silicon Microstrip Tracking Detectors

This work presents Turpial, a custom-designed low- power front-end readout ASIC for microstrip silicon sensors. Implemented in 130 nm CMOS technology, the chip integrates 64 identical readout channels, each including a configurable charge-sensitive amplifier, a bipolar pulse shaper, a 32-sample 50 Msps analog memory, and a 12-bit RC-hybrid SAR ADC operating at 1 Msps. To satisfy the target power budget of 5 mW per channel, the architecture employs a time-decoupled readout scheme in which fast transient signals are first captured in the analog memory and subsequently digitized at a lower rate. Turpial supports a wide dynamic range from 1 kℎ+ to 1 Mℎ+ while maintaining low noise performance, targeting an equivalent noise charge (ENC) below 200 𝑒−including the sensor, and providing a maximum gain of 1500 mV/fC. A digital block manages slow control, data acquisition, and data serialization through dual CML 300 Mb/s serializers. In addition, an on-chip reference circuit, based on a sub-1 V bandgap reference and an integrated LDO regulator, eliminates the need for external reference circuitry. Experimental results demonstrate that both the individual building blocks and the fully integrated ASIC meet the design specifications.

Hernandez, Hugo [Stanford University] (ORCID:00000↗

NASA NTRS1997

Ultra Small Aperture Terminal for Ka-Band SATCOM

An ultra small aperture terminal (USAT) at Ka-band frequency has been developed by Lewis Research Center (LeRC) for data rates up to 1.5 Mbps in the transmit mode and 40 Mbps in receive mode. The terminal consists of a 35 cm diameter offset-fed parabolic antenna which is attached to a solid state power amplifier and low noise amplifier. A single down converter is used to convert the Ka-band frequency to 70 MHz intermediate frequency (IF). A variable rate (9.6 Kbps to 10 Mbps) commercial modem with a standard RS-449/RS-232 interface is used to provide point-to-point digital services. The terminal has been demonstrated numerous times using the Advanced Communications Technology Satellite (ACTS) and the 4.5 in Link Evaluation Terminal (LET) in Cleveland. A conceptual design for an advanced terminal has also been developed. This advanced USAT utilizes Microwave Monolithic Integrated Circuit (MMIC) and flat plate array technologies. This terminal will be self contained in a single package which will include a 1 watt solid state amplifier (SSPA), low noise amplifier (LNA) and a modem card located behind the aperture of the array. The advanced USAT will be light weight, transportable, low cost and easy to point to the satellite. This paper will introduce designs for the reflector based and array based USAT's.

Acosta, Roberto↗

NASA NTRS2014

All-Digital Baseband 65nm PLL/FPLL Clock Multiplier using 10-cell Library

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

Shuler, Robert L., Jr.↗

NASA NTRS2014

ALL-Digital Baseband 65nm PLL/FPLL Clock Multiplier Using 10-Cell Library

PLLs for clock generation are essential for modern circuits, to generate specialized frequencies for many interfaces and high frequencies for chip internal operation. These circuits depend on analog circuits and careful tailoring for each new process, and making them fault tolerant is an incompletely solved problem. Until now, all digital PLLs have been restricted to sampled data DSP techniques and not available for the highest frequency baseband applications. This paper presents the design and preliminary evaluation of an all-digital baseband technique built entirely with an easily portable 10-cell digital library. The library is also described, as it aids in research and low volume design porting to new processes. The advantages of the digital approach are the wide variety of techniques available to give varying degrees of fault tolerance, and the simplicity of porting the design to new processes, even to exotic processes that may not have analog capability. The only tuning parameter is digital gate delay. An all-digital approach presents unique problems and standard analog loop stability design criteria cannot be directly used. Because of the quantization of frequency, there is effectively infinite gain for very small loop error feedback. The numerically controlled oscillator (NCO) based on a tapped delay line cannot be reliably updated while a pulse is active in the delay line, and ordinarily does not have enough frequency resolution for a low-jitter output.

Schuler, Robert L., Jr.↗

NASA NTRS2002

Hardware Evolution of Closed-Loop Controller Designs

Poster presentation will outline on-going efforts at NASA, MSFC to employ various Evolvable Hardware experimental platforms in the evolution of digital and analog circuitry for application to automatic control. Included will be information concerning the application of commercially available hardware and software along with the use of the JPL developed FPTA2 integrated circuit and supporting JPL developed software. Results to date will be presented.

Gwaltney, David↗

DOE OSTI2022

Hardware-Based Randomized Encoding for Sensor Authentication in Power Grid SCADA Systems

Supervisory Control and Data Acquisition (SCADA) systems are utilized extensively in critical power grid infrastructures. Modern SCADA systems have been proven to be susceptible to cyber-security attacks and require improved security primitives in order to prevent unwanted influence from an adversarial party. One section of weakness in the SCADA system is the integrity of field level sensors providing essential data for control decisions at a master station. In this paper we propose a lightweight hardware scheme providing inferred authentication for SCADA sensors by combining an analog to digital converter and a permutation generator as a single integrated circuit. Through this method we encode critical sensor data at the time of sensing, so that unencoded data is never stored in memory, increasing the difficulty of software attacks. We show through experimentation how our design stops both software and hardware false data injection attacks occurring at the field level of SCADA systems.

42 ENGINEERING↗

NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗

NASA NTRSDate not supplied

Electrical and Dielectric Characterizations of HTCC Electronic Packages for High Temperature Harsh Environment Applications

A prototype high temperature co-fired ceramic (HTCC) alumina packaging system composed of a 32-I/Os package and a compatible circuit board was previously developed and demonstrated for long term operation in 500 °C environments. The electrical / dielectric parasitic parameters of that chip level package were characterized and reported. This co-fired packaging system with platinum (Pt) conductor has successfully facilitated tests of silicon carbide (SiC) analog and digital integrated circuits (ICs) developed at NASA GRC at 500°C for up to 10,000 hours in ambient oven environment and 60 earth days in Venus surface environment with simulated temperature, pressure, and chemical constituents. Based on these previous results, this paper introduces new designs of Pt-HTCC packages with 16, 24, and 44 I/Os for packaging a new generation SiC ICs with 8, 24, 56, 62, and 72 I/Os to be tested in high temperature harsh environments. The package with 44 I/Os is specifically designed for the new SiC ICs with 56, 62, and 72-I/Os and electrical connection needs, the power pads of this package are consolidated, and an array of I/O pads distributed on separated vertical levels (inside the package) is used to control the overall package dimensions and mitigate the parasitic effects at high temperatures. This paper will present the detailed design of these chip-level packages and results of electrical and dielectric characterization of these newly fabricated chip-level Pt-HTCC packages.

High temperature↗

DOE OSTI2022

A Low-Power 1 Gb/s Line Driver with Configurable Pre-Emphasis for Lossy Transmission Lines

A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization (FFE) architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval (UI) via an 8-stage delay-locked loop (DLL) and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated (SST) drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.

47 OTHER INSTRUMENTATION↗