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NASA NTRSDate not supplied

Navigation Doppler Lidar Signal Processing Architecture and Algorithms

A coherent Doppler lidar has been developed to address the need for a high-performance, compact, and cost-effective velocity and altitude sensor onboard landing vehicles. One of the core subsystems within NDL is its signal processing architecture. The primary function of this subsystem is to digitize the analog output of the homodyned signal received from the photo-diode associated with each telescope, process this signal in the frequency domain, and then turn this information into velocity and range measurements. A secondary function of this subsystem is to setup and control the internal components within NDL and to enable the instrument to interface with external systems by receiving commands, sending telemetry, and synchronizing its measurements with external clocks and pulses. This paper will give an overview of the signal processing architecture within NDL. This will include a discussion on its fundamental processing components and the core signal processing algorithms. Command, telemetry and internal component controls will also be discussed as will how the signal processing architecture has also evolved over the years of development. We will discuss provisions for robust operation including Triple-Mode Redundancy (TMR) within NDL’s Field Programmable Gate Array (FPGA) and storage elements, a fault-tolerant boot process, and Error Detection and Correction (EDAC) on the Static Random-Access Memories (SRAMs). Finally, we conclude this paper with how this architecture could continue to evolve.

Doppler Lidar↗
NASA NTRS2023

LunaNet Position, Navigation, and Timing Services and Signal, Enabling the Future of Lunar Exploration

The International Space Exploration Coordination Group established in 2018 the 3rd edition of the Global Exploration Roadmap (ISECG, 2018) that aims to achieve Mars human surface activities and identifies the exploration of the Moon as a critical intermediate step. A supplement covering updates on surface exploration scenarios was released in 2020 (ISECG, 2020). The Artemis Accords (NASA Artemis, 2020), first signed in October 2020, now includes over two dozen nations, in an agreement on the principles for best practices, including interoperability. September 2022 introduced the National Aeronautics and Space Administration’s (NASA) Moon to Mars Objectives highlighting recurring tenets of collaboration with international and industry partners and interoperability, along with infrastructure objectives for Position, Navigation, and Timing (PNT). The successful Artemis 1 mission paved the way to the ambitious plans to establish a sustainable human presence on the Moon. Just a few months after Artemis 1 launch (NASA, 2022), iSpace HAKUTO-R Mission1 (iSpace, 2022) launched, being the first-ever commercial mission, launched by a commercial launch service provider, aiming to land on the lunar surface. The NASA Artemis programme plans initial crewed landings and traverses in 2025, supported by the Lunar Gateway, followed by regular launches to build the lunar systems (NASA Artemis Plan, 2020), (NASA, 2022). NASA’s contracts with Commercial Lunar Payload Services (CLPS, (NASA, n.d.)) to deliver science and technology to the Moon, with launches starting in November 2023. The European Space Agency (ESA) Argonaut (ESA Argonaut, 2022) programme plans to have recurrent missions to bring payloads to the lunar surface, supporting lunar exploration. These are just a few examples of planned missions that will target the Earth’s natural satellite in the next decade, with forecasts of tens of missions per year (NSR, 2022), (Euroconsult, 2020). The large number of missions and the complexity of landing and operating are expected to demand a change of paradigm from the current Earth-based communication and navigation services. In recent years, several agencies have proposed to deploy cislunar communication and navigation services to support lunar missions (NASA LCRNS, 2022), (ESA Moonlight, 2022), (JAXA, 2022)). All these proposals seek to deploy service-providing satellites in lunar orbit to ease the user missions’ operations. The PNT services objective is to support all types of lunar users (e.g.: orbiters, landers, ascent vehicles, and surface crew and rovers). At the same time, NASA and ESA initiated an effort to define a common framework to ensure interoperability among different service providers: the LunaNet framework. The LunaNet Interoperability Specification (NASA and ESA, 2023) covers communication, PNT, and auxiliary services, by establishing a common set of requirements to ensure interoperability. This conference contribution will present the LunaNet PNT services, focusing on the Lunar Augmented Navigation Service (LANS) that resembles the Global Navigation Satellite System (GNSS) concept on Earth: constellations of satellites broadcasting a radio navigation signal synchronized to a common reference clock, with augmentations to accommodate users’ needs in an environment away from Earth. This includes a description of the high-level LANS concept and the basic principles defined to ensure interoperability. In addition, it will describe the common S-band PNT Augmented Forward Signal (AFS) and common messages to be adopted for compliance with the LunaNet framework, and the justification of the selected approach.

LunaNet↗
NASA NTRS2023

Lunanet Position, Navigation, and Timing Services and Signals, Enabling the Future of Lunar Exploration

The International Space Exploration Coordination Group established in 2018 the 3rd edition of the Global Exploration Roadmap (ISECG, 2018) that aims to achieve Mars human surface activities and identifies the exploration of the Moon as a critical intermediate step. A supplement covering updates on surface exploration scenarios was released in 2020 (ISECG, 2020). The Artemis Accords (NASA Artemis, 2020), first signed in October 2020, now includes over two dozen nations, in an agreement on the principles for best practices, including interoperability. In September 2022 the National Aeronautics and Space Administration (NASA) introduced the Moon to Mars Objectives highlighting recurring tenets of collaboration with international and industry partners and interoperability, along with infrastructure objectives for Position, Navigation, and Timing (PNT). The successful Artemis 1 mission paved the way to the ambitious plans to establish a sustainable human presence on the Moon. Just a few months after Artemis 1 launch (NASA, 2022), iSpace HAKUTO-R Mission1 (iSpace, 2022) launched, being the first-ever mission launched by a commercial launch service provider aiming to land on the lunar surface. The NASA Artemis program plans initial crewed landings and surface traverses in 2025, supported by the Lunar Gateway. Regular launches will follow to build the lunar systems for a sustained presence as presented in the Artemis Plan (NASA Artemis Plan, 2020), (NASA, 2022). NASA’s contracts with commercial providers through the Commercial Lunar Payload Services program (CLPS, (NASA, n.d.)) will deliver science and technology demonstration missions to the Moon starting in November 2023. The European Space Agency (ESA) Argonaut (ESA Argonaut, 2022) program plans to have recurrent missions to bring payloads to the lunar surface, supporting lunar exploration. These are just a few examples of planned missions that will target Earth’s natural satellite in the next decade, with forecasts of tens of missions per year (NSR, 2022), (Euroconsult, 2020). The large number of missions and the complexity of landing and operating are expected to demand a change of paradigm from the current Earth-based communication and navigation services, that may be combined with onboard sensors. In recent years, several agencies have proposed to deploy cislunar communication and navigation services to support lunar missions (NASA LCRNS, 2022), (ESA Moonlight, 2022), (JAXA, 2022)). All these proposals seek to deploy service-providing satellites in lunar orbit to ease the user missions’ operations. The PNT services objective is to support all types of lunar users (e.g.: orbiters, landers, ascent vehicles, surface crew, rovers, and deployed science payloads). At the same time, NASA and ESA initiated an effort to define a common framework to ensure interoperability among different service providers: the LunaNet framework. The LunaNet Interoperability Specification (NASA and ESA, 2023) covers communication, PNT, and auxiliary services, by establishing a common set of requirements to ensure interoperability. This conference contribution will present the LunaNet PNT services, focusing on the Lunar Augmented Navigation Service (LANS) that would be provided by a system that resembles the Global Navigation Satellite System (GNSS) concept on Earth: constellations of satellites broadcasting a radio navigation signal synchronized to a common reference clock, with augmentations to accommodate users’ needs in an environment away from Earth. This paper includes a description of the high-level LANS concept, and the basic principles defined to ensure interoperability. In addition, it will describe the common S-band PNT Augmented Forward Signal (AFS) and common messages to be adopted for compliance with the LunaNet framework, and the justification of the selected approach.

LunaNet↗
NASA NTRS1979

Multiple speed expandable bit synchronizer

A multiple speed bit synchronizer was designed for installation in an inertial navigation system data decoder to extract non-return-to-zero level data and clock signal from biphase level data. The circuit automatically senses one of four pre-determined biphase data rates and synchronizes the proper clock rate to the data. Through a simple expansion of the basic design, synchronization of more than four binarily related data rates can be accomplished. The design provides an easily adaptable, low cost, low power alternative to external bit synchronizers with additional savings in size and weight.

Bundinger, J. M.↗
NASA NTRS1995

Network time synchronization servers at the US Naval Observatory

Responding to an increased demand for reliable, accurate time on the Internet and Milnet, the U.S. Naval Observatory Time Service has established the network time servers, tick.usno.navy.mil and tock.usno.navy.mil. The system clocks of these HP9000/747i industrial work stations are synchronized to within a few tens of microseconds of USNO Master Clock 2 using VMEbus IRIG-B interfaces. Redundant time code is available from a VMEbus GPS receiver. UTC(USNO) is provided over the network via a number of protocols, including the Network Time Protocol (NTP) (DARPA Network Working Group Report RFC-1305), the Daytime Protocol (RFC-867), and the Time protocol (RFC-868). Access to USNO network time services is presently open and unrestricted. An overview of USNO time services and results of LAN and WAN time synchronization tests will be presented.

Schmidt, Richard E.↗
NASA NTRS2012

Radiation-Hard SpaceWire/Gigabit Ethernet-Compatible Transponder

A radiation-hard transponder was developed utilizing submicron/nanotechnology from IBM. The device consumes low power and has a low fabrication cost. This device utilizes a Plug-and-Play concept, and can be integrated into intra-satellite networks, supporting SpaceWire and Gigabit Ethernet I/O. A space-qualified, 100-pin package also was developed, allowing space-qualified (class K) transponders to be delivered within a six-month time frame. The novel, optical, radiation-tolerant transponder was implemented as a standalone board, containing the transponder ASIC (application specific integrated circuit) and optical module, with an FPGA (field-programmable gate array) friendly parallel interface. It features improved radiation tolerance; high-data-rate, low-power consumption; and advanced functionality. The transponder utilizes a patented current mode logic library of radiation-hardened-by-architecture cells. The transponder was developed, fabricated, and radhard tested up to 1 MRad. It was fabricated using 90-nm CMOS (complementary metal oxide semiconductor) 9 SF process from IBM, and incorporates full BIT circuitry, allowing a loop back test. The low-speed parallel LVCMOS (lowvoltage complementary metal oxide semiconductor) bus is compatible with Actel FPGA. The output LVDS (low-voltage differential signaling) interface operates up to 1.5 Gb/s. Built-in CDR (clock-data recovery) circuitry provides robust synchronization and incorporates two alarm signals such as synch loss and signal loss. The ultra-linear peak detector scheme allows on-line control of the amplitude of the input signal. Power consumption is less than 300 mW. The developed transponder with a 1.25 Gb/s serial data rate incorporates a 10-to-1 serializer with an internal clock multiplication unit and a 10-1 deserializer with internal clock and data recovery block, which can operate with 8B10B encoded signals. Three loop-back test modes are provided to facilitate the built-in-test functionality. The design is based on a proprietary library of differential current switching logic cells implemented in the standard 90-nm CMOS 9SF technology from IBM. The proprietary low-power LVDS physical interface is fully compatible with the SpaceWire standard, and can be directly connected to the SFP MSA (small form factor pluggable Multiple Source Agreement) optical transponder. The low-speed parallel interfaces are fully compatible with the standard 1.8 V CMOS input/output devices. The utilized proprietary annular CMOS layout structures provide TID tolerance above 1.2 MRad. The complete chip consumes less than 150 mW of power from a single 1.8-V positive supply source.

Katzman, Vladimir↗
NASA NTRS1990

The Galileo Orbiter - Command and telemetry subsystems on their way to Jupiter

An overview is given of the Galileo command and telemetry subsystems, which exemplify the rigid time-synchronized systems required by TDM (time division multiplexing). The spacecraft clock is examined, along with some of the rationale for the development of the clock structure and timing to give a sense of the design imperatives for rigidly synchronized systems. Additional subjects include the structure of the science and engineering frames, emphasizing the subcommutated structure of the engineering frame and its relationship to the spacecraft clock; ground processing for and basic uses of the telemetry; the various message types used to transmit commands to the spacecraft; and the generation processes for the command message types.

Erickson, James K.↗
NASA NTRS2012

Sample-Clock Phase-Control Feedback

To demodulate a communication signal, a receiver must recover and synchronize to the symbol timing of a received waveform. In a system that utilizes digital sampling, the fidelity of synchronization is limited by the time between the symbol boundary and closest sample time location. To reduce this error, one typically uses a sample clock in excess of the symbol rate in order to provide multiple samples per symbol, thereby lowering the error limit to a fraction of a symbol time. For systems with a large modulation bandwidth, the required sample clock rate is prohibitive due to current technological barriers and processing complexity. With precise control of the phase of the sample clock, one can sample the received signal at times arbitrarily close to the symbol boundary, thus obviating the need, from a synchronization perspective, for multiple samples per symbol. Sample-clock phase-control feedback was developed for use in the demodulation of an optical communication signal, where multi-GHz modulation bandwidths would require prohibitively large sample clock frequencies for rates in excess of the symbol rate. A custom mixedsignal (RF/digital) offset phase-locked loop circuit was developed to control the phase of the 6.4-GHz clock that samples the photon-counting detector output. The offset phase-locked loop is driven by a feedback mechanism that continuously corrects for variation in the symbol time due to motion between the transmitter and receiver as well as oscillator instability. This innovation will allow significant improvements in receiver throughput; for example, the throughput of a pulse-position modulation (PPM) with 16 slots can increase from 188 Mb/s to 1.5 Gb/s.

Quirk, Kevin J.↗
NASA NTRS1976

Power spectra of sinusoidal amplitude-modulated binary signals

Power spectra for binary phase-shift keyed (PSK) and frequency-shift keyed (FSK) signals with combined sinusoidal amplitude modulation by the bit rate clock are presented. Such signal formats have application in 'burst' communication systems wherein reliable bit synchronization is provided with relative receiver simplicity. Effects of the clock amplitude modulation index and phase are considered, and corresponding power spectra are illustrated. Further, effects of the clock parameters on the rate of spectral rolloff are given and compared with those of conventional PSK and FSK spectra.

Gee, T. H.↗
NASA NTRS1989

Apparatus for using a time interval counter to measure frequency stability

An apparatus for measuring the relative stability of two signals is disclosed comprising a means for mixing the two signals down to a beat note sine wave and for producing a beat note square wave whose upcrossings are the same as the sine wave. A source of reference frequency is supplied to a clock divider and interval counter to synchronize them and to generate a picket fence for providing a time reference grid of period shorter than the beat period. An interval counter is employed to make a preliminary measurement between successive upcrossings of the beat note square wave for providing an approximate time interval therebetween as a reference. The beat note square wave and the picket fence are then provided to the interval counter to provide an output consisting of the time difference between the upcrossing of each beat note square wave cycle and the next picket fence pulse such that the counter is ready for each upcrossing and dead time is avoided. A computer containing an algorithm for calculating the exact times of the beat note upcrossings then computes the upcrossing times.

Greenhall, Charles A.↗
NASA NTRS1990

Verifying an interactive consistency circuit: A case study in the reuse of a verification technology

The work done at ORA for NASA-LRC in the design and formal verification of a hardware implementation of a scheme for attaining interactive consistency (byzantine agreement) among four microprocessors is presented in view graph form. The microprocessors used in the design are an updated version of a formally verified 32-bit, instruction-pipelined, RISC processor, MiniCayuga. The 4-processor system, which is designed under the assumption that the clocks of all the processors are synchronized, provides software control over the interactive consistency operation. Interactive consistency computation is supported as an explicit instruction on each of the microprocessors. An identical user program executing on each of the processors decides when and on what data interactive consistency must be performed. This exercise also served as a case study to investigate the effectiveness of reusing the technology which was developed during the MiniCayuga effort for verifying synchronous hardware designs. MiniCayuga was verified using the verification system Clio which was also developed at ORA. To assist in reusing this technology, a computer-aided specification and verification tool was developed. This tool specializes Clio to synchronous hardware designs and significantly reduces the tedium involved in verifying such designs. The tool is presented and how it was used to specify and verify the interactive consistency circuit is described.

Bickford, Mark↗
NASA NTRS1993

Plans to improve the experimental limit in the comparison of the east-west and west-east one-way light propagation times on the rotating earth

The preceding paper describes the results so far (interrupted in the Spring of 1989 because of lack of funds) of an experiment comparing the one-way light propagation times on the surface of the rotating Earth. For the 20 Km path length component in the East-West direction the predicted difference between the opposite sense propagation times would be 160 ps, if the approximately 360 Km/s surface speed of the Earth gives effective light speeds of 3 x 10(exp 8) m/s +/- 360 m/s. This could lead to a prediction of the difference between the clock transport and the light pulse synchronization methods described in the preceding paper: delta(T) = 0.5 (160) = 80 ps. The current upper bound of approximately 100 ps for delta(T) is limited by poorly understood systematic errors. The most important seems to be intensity-dependent time delays in the remote light pulse avalanche photo-diode detector. This will be replaced by a continuously operating circular scan streak camera having single photon sensitivity and a time resolution of approximately 5 ps. (This camera has recently been developed by the Xian Institute of Optics and Precision Mechanics in the P.R.C.). Better isolation from shocks and vibration for the Sigma-Tau hydrogen maser during transport will be provided. It is hoped that delta(T) is less than 20 ps can be achieved.

Alley, C. O.↗
NASA NTRS2011

STRS SpaceWire FPGA Module

An FPGA module leverages the previous work from Goddard Space Flight Center (GSFC) relating to NASA s Space Telecommunications Radio System (STRS) project. The STRS SpaceWire FPGA Module is written in the Verilog Register Transfer Level (RTL) language, and it encapsulates an unmodified GSFC core (which is written in VHDL). The module has the necessary inputs/outputs (I/Os) and parameters to integrate seamlessly with the SPARC I/O FPGA Interface module (also developed for the STRS operating environment, OE). Software running on the SPARC processor can access the configuration and status registers within the SpaceWire module. This allows software to control and monitor the SpaceWire functions, but it is also used to give software direct access to what is transmitted and received through the link. SpaceWire data characters can be sent/received through the software interface, as well as through the dedicated interface on the GSFC core. Similarly, SpaceWire time codes can be sent/received through the software interface or through a dedicated interface on the core. This innovation is designed for plug-and-play integration in the STRS OE. The SpaceWire module simplifies the interfaces to the GSFC core, and synchronizes all I/O to a single clock. An interrupt output (with optional masking) identifies time-sensitive events within the module. Test modes were added to allow internal loopback of the SpaceWire link and internal loopback of the client-side data interface.

Lux, James P.↗
NASA NTRS2013

Apparatus and Method for Compensating for Process, Voltage, and Temperature Variation of the Time Delay of a Digital Delay Line

A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.

Seefeldt, James↗
NASA NTRS2014

Centering a DDR Strobe in the Middle of a Data Packet

The Orion CEV Northstar ASIC (application- specific integrated circuit) project required a DDR (double data rate) memory bus driver/receiver (DDR PHY block) to interface with external DDR memory. The DDR interface (JESD79C) is based on a source synchronous strobe (DQS\) that is sent along with each packet of data (DQ). New data is provided concurrently with each edge of strobe and is sent irregularly. In order to capture this data, the strobe needs to be delayed and used to latch the data into a register. A circuit solves the need for training a DDR PRY block by incorporating a PVT-compensated delay element in the strobe path. This circuit takes an external reference clock signal and uses the regular clock to calibrate a known delay through a data path. The compensated delay DQS signal is then used to capture the DQ data in a normal register. This register structure can be configured as a FIFO (first in first out), in order to transfer data from the DDR domain to the system clock domain. This design is different in that it does not rely upon the need for training the system response, nor does it use a PLL (phase locked loop) or a DLL (delay locked loop) to provide an offset of the strobe signal. The circuit is created using standard ASIC building blocks, plus the PVT (process, voltage, and temperature) compensated delay line. The design uses a globally available system clock as a reference, alleviating the need to operate synchronously with the remote memory. The reference clock conditions the PVT compensated delay line to provide a pre-determined amount of delay to any data signal that passes through this delay line. The delay line is programmed in degrees of offset, so that one could think of the clock period representing 360deg of delay. In an ideal environment, delaying the strobe 1/4 of a clock cycle (90deg) would place the strobe in the middle of the data packet. This delayed strobe can then be used to clock the data into a register, satisfying setup and hold requirements of the system.

Johnson, Michael↗
NASA NTRS1981

Cross-spectrum symbol synchronization

A popular method of symbol synchronization exploits one aspect of generalized harmonic analysis, normally referred to as the cross-spectrum. Utilizing nonlinear techniques, the input symbol energy is effectively concentrated onto multiples of the symbol clock frequency, facilitating application of conventional phase lock synchronization techniques. A general treatment of the cross-spectrum technique is developed and shown to be applicable across a broad class of symbol modulation formats. An important specific symbol synchronization application is then treated, focusing the general development to provide both insight and quantitative measure of the performance impact associated with variation in these key synchronization parameters: symbol modulation format, symbol transition probability, symbol energy to noise density ratio, and symbol rate to filter bandwidth ratio.

Mccallister, R. D.↗
NASA NTRS2009

Digital Synchronizer without Metastability

A proposed design for a digital synchronizing circuit would eliminate metastability that plagues flip-flop circuits in digital input/output interfaces. This metastability is associated with sampling, by use of flip-flops, of an external signal that is asynchronous with a clock signal that drives the flip-flops: it is a temporary flip-flop failure that can occur when a rising or falling edge of an asynchronous signal occurs during the setup and/or hold time of a flip-flop. The proposed design calls for (1) use of a clock frequency greater than the frequency of the asynchronous signal, (2) use of flip-flop asynchronous preset or clear signals for the asynchronous input, (3) use of a clock asynchronous recovery delay with pulse width discriminator, and (4) tying the data inputs to constant logic levels to obtain (5) two half-rate synchronous partial signals - one for the falling and one for the rising edge. Inasmuch as the flip-flop data inputs would be permanently tied to constant logic levels, setup and hold times would not be violated. The half-rate partial signals would be recombined to construct a signal that would replicate the original asynchronous signal at its original rate but would be synchronous with the clock signal.

Simle, Robert M.↗
NASA NTRS2008

An Overview of Starfish: A Table-Centric Tool for Interactive Synthesis

Engineering is an interactive process that requires intelligent interaction at many levels. My thesis [1] advances an engineering discipline for high-level synthesis and architectural decomposition that integrates perspicuous representation, designer interaction, and mathematical rigor. Starfish, the software prototype for the design method, implements a table-centric transformation system for reorganizing control-dominated system expressions into high-level architectures. Based on the digital design derivation (DDD) system a designer-guided synthesis technique that applies correctness preserving transformations to synchronous data flow specifications expressed as co- recursive stream equations Starfish enhances user interaction and extends the reachable design space by incorporating four innovations: behavior tables, serialization tables, data refinement, and operator retiming. Behavior tables express systems of co-recursive stream equations as a table of guarded signal updates. Developers and users of the DDD system used manually constructed behavior tables to help them decide which transformations to apply and how to specify them. These design exercises produced several formally constructed hardware implementations: the FM9001 microprocessor, an SECD machine for evaluating LISP, and the SchemEngine, garbage collected machine for interpreting a byte-code representation of compiled Scheme programs. Bose and Tuna, two of DDD s developers, have subsequently commercialized the design derivation methodology at Derivation Systems, Inc. (DSI). DSI has formally derived and validated PCI bus interfaces and a Java byte-code processor; they further executed a contract to prototype SPIDER-NASA's ultra-reliable communications bus. To date, most derivations from DDD and DRS have targeted hardware due to its synchronous design paradigm. However, Starfish expressions are independent of the synchronization mechanism; there is no commitment to hardware or globally broadcast clocks. Though software back-ends for design derivation are limited to the DDD stream-interpreter, targeting synchronous or real-time software is not substantively different from targeting hardware.

Tsow, Alex↗