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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
NASA NTRS1997

Root-Raised Cosine Filter Implementation That Uses Canonical Signed Digits for High-Speed Digital Filter Applications

NASA Lewis Research Center's Space Communications Division has been investigating high-speed digital filters that can operate at a higher speed than those in current use for a digital modulator and demodulator (modem). Using the Canonical Signed Digits (CSD) number representation for filter coefficients is a very effective way to increase the filter's speed while reducing complexity in the digital filter hardware design. This approach is a good alternative to using an expensive parallel-processing design technique or custom, application-specific integrated circuits. Such integrated circuits may not be suitable for applications that require filter speeds faster than what application-specific integrated circuits digital signal processors can offer for a dedicated channel. When a communication channel is a dedicated, multiplication process--a costly, time-consuming process--it can be greatly simplified by a replacement of the filter coefficients with CSD numbers. A computer code written with the MATLAB software package runs the program and generates CSD-represented filter coefficients that are based on minimizing minimum mean square errors. Also, the Alta Group of Cadence's Signal Processing Workstation is used to simulate and analyze the CSD filter responses. The impulse response of the root-raised cosine filter that is used as a base model is defined. From this filter, a set of coefficients is sampled and stored in a file. For the all coefficients, the optimal CSD number for each coefficient is searched on the basis of the minimum-mean-square-errors criterion. Because the distribution of CSD numbers is not uniform, quantization errors tend to be bigger for coefficients greater than 1/2. To offset errors that occur in a region of coefficients between 1/2 to 1 and to better represent fractions with CSD numbers, an extra nonzero digit is allowed for any coefficients exceeding 1/2. This will greatly improve frequency response as well as intersymbol interference at the receiver. The frequency response of a set of collected CSD-represented filter coefficients was compared with the same filter that was conventionally implemented. Analyses show CSD-implemented filters perform as well as conventional filters. Comparison of eye diagrams and bit-error-rate curves between CSD filters and traditionally implemented filters are almost indistinguishable. However, filter complexity was reduced from almost 3.5 to 1 for CSD filters. Complete computer simulation results are available. In the near future, work will focus on building actual working digital filter hardware in a field programmable gate array (FPGA).

Kim, Heechul↗
NASA NTRS1981

The effects of receiver tracking phase error on the performance of the concatenated Reed-Solomon/Viterbi channel coding system

Analytical and experimental results are presented of the effects of receiver tracking phase error, caused by weak signal conditions on either the uplink or the downlink or both, on the performance of the concatenated Reed-Solomon (RS) Viterbi channel coding system. The test results were obtained under an emulated S band uplink and X band downlink, two way space communication channel in the telecommunication development laboratory of JPL with data rates ranging from 4 kHz to 20 kHz. It is shown that, with ideal interleaving, the concatenated RS/Viterbi coding system is capable of yielding large coding gains at very low bit error probabilities over the Viterbi decoded convolutional only coding system. Results on the effects of receiver tracking phase errors on the performance of the concatenated coding system with antenna array combining are included.

Liu, K. Y.↗
NASA NTRS2000

Enhancement of the NMSU Channel Error Simulator to Provide User-Selectable Link Delays

This is the third in a continuing series of reports describing the development of the Space-to-Ground Link Simulator (SGLS) to be used for testing data transfers under simulated space channel conditions. The SGLS is based upon Virtual Instrument (VI) software techniques for managing the error generation, link data rate configuration, and, now, selection of the link delay value. In this report we detail the changes that needed to be made to the SGLS VI configuration to permit link delays to be added to the basic error generation and link data rate control capabilities. This was accomplished by modifying the rate-splitting VIs to include a buffer the hold the incoming data for the duration selected by the user to emulate the channel link delay. In sample tests of this configuration, the TCP/IP(sub ftp) service and the SCPS(sub fp) service were used to transmit 10-KB data files using both symmetric (both forward and return links set to 115200 bps) and unsymmetric (forward link set at 2400 bps and a return link set at 115200 bps) link configurations. Transmission times were recorded at bit error rates of 0 through 10(exp -5) to give an indication of the link performance. In these tests. we noted separate timings for the protocol setup time to initiate the file transfer and the variation in the actual file transfer time caused by channel errors. Both protocols showed similar performance to that seen earlier for the symmetric and unsymmetric channels. This time, the delays in establishing the file protocol also showed that these delays could double the transmission time and need to be accounted for in mission planning. Both protocols also showed a difficulty in transmitting large data files over large link delays. In these tests, there was no clear favorite between the TCP/IP(sub ftp) and the SCPS(sub fp). Based upon these tests, further testing is recommended to extend the results to different file transfer configurations.

Horan, Stephen↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1984

On the passage of high-level pulsed radio frequency interference through a nonlinear satellite transponder

Attention is given to the uncoded bit error rate (BER) performance of a satellite communications system whose modulation scheme is binary PSK and whose transponder contains an arbitrary amplitude nonlinearity, all in the presence of high level pulsed radio frequency interference (RFI). A general approach is presented for direct BER evaluations, in contrast to other approaches which may employ SNR suppression factors. The computed results are based on arbitrarily specified RFI scenarios, in the presence of hard limiter, clipper, or blanker amplitude nonlinearities. Performance curves demonstrate the superiority of an appropriately chosen blanker when the RFI environment is most severe. The results obtained also pertain to the sensitivity of performance to the information bit rate, signal power variations, and the ratio of CW to noise content. The CW effects are found to be the most severe.

Weinberg, A.↗
NASA NTRS1996

Computer Simulation Results and Analysis for a Root-Raised Cosine Filter Design using Canonical Signed Digits

Filters implemented using Canonical Signed-Digit (CSD) number representation for the coefficients have been studied for many years as an efficient way to increase the speed and reduce the hardware complexity. A simple and very effective method for designing a CSD filter with a specific set of filter parameters has been investigated and its simulation results are presented here. In order to optimize filter coefficients into the corresponding CSD numbers, the Minimum Mean Square Error (MMSE) criterion is used. Furthermore, an attempt is made to improve frequency response of the CSD filter by allocating an extra non-zero digit for normalized coefficients exceeding one-half. Due to limited filter aperture width in examples presented here, the frequency response of CSD filter as the number of non-zero digits in a CSD code increases is not affected much. A root-raised cosine filter model is employed as a base line for this design approach. Finally, the CSD filter simulation results and a hardware complexity comparison with a conventional filter are also shown along with the eye diagrams an Bit-Error-Rate (BER) performance curves.

Kim, Heechul↗
NASA NTRS1990

The performance of trellis-coded MDPSK with multiple symbol detection

The idea of using a multiple (more than two) symbol observation interval to improve error probability performance is applied to differential detection of trellis-coded multiple phase-shift keying (MPSK) over an additive white Gaussian noise (AWGN) channel. An equivalent Euclidean distance measure per trellis branch is determined for this detection scheme. This is used to define an augmented (larger multiplicity) trellis code whose distance measure is the conventional squared Euclidean distance typical of conventional trellis-coded modulation on the AWGN. Such an augmented multiple trellis code is a convenient mathematical tool for simplifying the analysis. Results are obtained by a combination of analysis (upper Chernoff bounds and asymptotic large-SNR approximations) and computer simulation. It is shown that only a slight increase (e.g., one symbol) in the length of the observation interval will provide a significant improvement in bit error probability performance.

Divsalar, Dariush↗
NASA NTRS1991

Comparative study on the performance of power and bandwidth efficient modulations in LMSS under fading and interference

Aspects of error performance of various power and bandwidth efficient modulations for the land mobile satellite systems (LMSS) were investigated under multipath fading and interferences by using Monte-Carlo simulation. A differential detection for 16QAM (quadrature amplitude modulation) was proposed to cope with Ricean fading and Doppler shift. Computer simulation results show that the performance of 16QAM with differential detection is as good as that of 16PSK with coherent detection and 3 dB better than that of 16PSK with differential detection, although it degrades by about 4.5 dB as compared to 16QAM with coherent detection under an additive white Gaussian noise (AWGN) channel. For the nonlinear channels, 16QAM with modified signal constellations is introduced and analyzed. The simulation results show that the modified 16QAM exhibits a gain of 2.5 dB over 16PSK under traveling-wave tube nonlinearity, and about 4 dB gain over 16PSK at the bit error rate of 10 exp -5 under AWGN. Computer simulation results for modified 16 QAM under cochannel interference and adjacent-channel interference are also presented.

Liu, Jian↗
NASA NTRS1970

Digital demodulation with data subcarrier tracking

Digital demodulator is based on early-late bit timing scheme coupled with Costas data tracking loop. System is successful in enhancement of weak signals from space where atmospheric and other interference media cause bit error rate to reach excessive level.

Sanger, D. K.↗
NASA NTRS1971

Development and testing of the infrared interferometer spectrometer for the Mariner Mars 1971 spacecraft

The design, development and testing of the infrared interferometer spectrometer is reported with emphasis on the unique features of the Mariner instrument as compared to previous IRIS instruments flown on the Nimbus meteorological research satellites. The interferometer functions in the spectral range from 50 microns to 6.3 microns. A noise equivalent radiance of 0.5 X 10 to the -7th power W/sq cm/ster/cm has been achieved. Major improvements that were implemented included the cesium iodide beamsplitter and electronic features to suppress the effect of vibration on the Michelson mirror motion and digital filtering through the summation of increased sampling of the infrared signal. A bit error detection and correction scheme was also implemented in order to recover the science data with a higher level of confidence over the telecommunication link.

Hanel, R. H.↗
NASA NTRS1971

Variable-rate optical communication through the turbulent atmosphere

It was demonstrated that the data transmitter can extract real time, channel state information by processing the field received when a pilot tone is sent from the data receiver to the data transmitter. Based on these channel measurements, optimal variable rate techniques were derived and significant improvements in system perforamnce were obtained, particularly at low bit error rates.

Levitt, B. K.↗
NASA NTRS1972

A study of FM threshold extension techniques

The characteristics of three postdetection threshold extension techniques are evaluated with respect to the ability of such techniques to improve the performance of a phase lock loop demodulator. These techniques include impulse-noise elimination, signal correlation for the detection of impulse noise, and delta modulation signal processing. Experimental results from signal to noise ratio data and bit error rate data indicate that a 2- to 3-decibel threshold extension is readily achievable by using the various techniques. This threshold improvement is in addition to the threshold extension that is usually achieved through the use of a phase lock loop demodulator.

Arndt, G. D.↗