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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
DOE OSTI2015

Characterization of Silicon Detector Readout Electronics

Configuration and calibration of the front-end electronics typical of many silicon detector configurations were investigated in a lab activity based on a pair of strip sensors interfaced with FSSR2 read-out chips and an FPGA. This simple hardware configuration, originally developed for a telescope at the Fermilab Test Beam Facility, was used to measure thresholds and noise on individual readout channels and to study the influence that different configurations of the front-end electronics had on the observed levels of noise in the system. An understanding of the calibration and operation of this small detector system provided an opportunity to explore the architecture of larger systems such as those currently in use at LHC experiments.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2015

A front-end readout Detector Board for the OpenPET electronics system

Here, we present a 16-channel front-end readout board for the OpenPET electronics system. A major task in developing a nuclear medical imaging system, such as a positron emission computed tomograph (PET) or a single-photon emission computed tomograph (SPECT), is the electronics system. While there are a wide variety of detector and camera design concepts, the relatively simple nature of the acquired data allows for a common set of electronics requirements that can be met by a flexible, scalable, and high-performance OpenPET electronics system. The analog signals from the different types of detectors used in medical imaging share similar characteristics, which allows for a common analog signal processing. The OpenPET electronics processes the analog signals with Detector Boards. Here we report on the development of a 16-channel Detector Board. Each signal is digitized by a continuously sampled analog-to-digital converter (ADC), which is processed by a field programmable gate array (FPGA) to extract pulse height information. A leading edge discriminator creates a timing edge that is "time stamped" by a time-to-digital converter (TDC) implemented inside the FPGA. In conclusion, this digital information from each channel is sent to an FPGA that services 16 analog channels, and then information from multiple channels is processed by this FPGA to perform logic for crystal lookup, DOI calculation, calibration, etc.

47 OTHER INSTRUMENTATION↗
DOE OSTI2020

Development of a FELIX based readout system for ITk strip hybrid module demonstrator for ATLAS Phase-II Upgrade

The Large Hadron Collider (LHC) will undergo a major upgrade around 2024 with a roughly tenfold increase in luminosity. It results in corresponding increases in particle rates and radiation doses that the current ATLAS Inner Tracking Detector cannot cope with. Therefore the ATLAS experiment will build a new all-silicon tracking system called the ITk (Inner Tracker) that includes an inside pixel detector close to the beam line and a strip detector in outside layer. Meanwhile the ATLAS experiment will adopt the Front-End Link eXchange (FELIX) system as the interface between the data acquisition and front-end electronics for all sub-detectors in the Phase II Upgrade. In this contribution, we present a prototype of FELIX based readout system for the strip hybrid module. Its hardware, firmware and software GUI application will be discussed, as well as integration test results.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2021

Characterization and QC practice of 16-channel ADC ASIC at cryogenic temperature for Liquid Argon TPC front-end readout electronics system in DUNE experiment

ColdADC is a low-noise 16-channel analog-to-digital converter ASIC designed for cold readout electronics of Liquid Argon Time Projection Chambers (LArTPCs) in the Deep Underground Neutrino Experiment (DUNE). ColdADC was specifically designed for operation at cryogenic temperatures (77 K–89 K). Cold electronics is considered to be an enabling technology for liquid argon detectors in neutrino experiments. The main function of the chip is to digitize signals from the 16-channel charge-sensitive amplifier designed at BNL (LArASIC) and send digitized signals to the data aggregator and serializer chip (COLDATA). ColdADC operates with a resolution of 12 bits and a sampling rate of 2 MS/s per channel. A complete characterization of prototype chips was conducted at cryogenic temperature, involving power consumption, noise and linearity performance. In the first DUNE Far-Detector module, 384000 data channels will be read out, corresponding to 24000 ColdADC chips. Therefore, systematic testing of ColdADC chips at cryogenic temperature is vital for the quality and reliability of DUNE Single-Phase modules. We have developed a Quality Control (QC) test stand that includes ColdADC evaluation and characterization at cryogenic temperature. The QC procedure was applied to a first batch of 33 chips, corresponding to 528 data channels. The obtained results meet all the required DUNE specifications for ColdADC. Moreover, the testing outcome allowed us to identify possibilities of performance optimization that are currently being addressed in the design of the next version of the chip. The Quality Control procedure is proved to be successful and will be a reference design for future large-batch production testing of final ColdADC ASICs.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

In-pixel automatic threshold calibration for the CMS Endcap Timing Layer readout chip

We present the implementation and verification of an in-pixel automatic threshold calibration circuit for the CMS Endcap Timing Layer (ETL) in the High-Luminosity LHC upgrade. The discriminator threshold of the ETL readout chip (ETROC) needs to be calibrated regularly to mitigate the circuit baseline change. Traditional methods need a lot of communication through a slow control system hence are time-consuming. This paper describes an in-pixel automatic scheme with improvements in operating time and usability. In this scheme, a sample-accumulation circuit is used to measure the average discriminator output. A binary successive approximation and linear combination scan are applied to find the equivalent baseline. The actual calibration procedure has been first implemented in FPGA firmware and tested with the ETROC front-end prototype chip (ETROC0). The calibration circuit has been implemented with Triple Modular Redundancy (TMR) and verified with Single Event Effects (SEEs) simulation. A complete calibration process lasts 35 ms with a 40 MHz clock. In the worst case, the dynamic and static power consumption are estimated to be 300 uW and 10.4 uW, respectively. The circuit design, implemented in a 65 CMOS technology, will be integrated into ETROC2, the next iteration of the ETROC with a 16 x16 pixel matrix.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

RD53 pixel readout integrated circuits for ATLAS and CMS HL-LHC upgrades

The RD53 collaboration has since 2013 developed new hybrid pixel detector chips with 50 × 50 μm2 pixels for the HL-LHC upgrades of the ATLAS and CMS experiments at CERN. A common architecture, design and verification framework has been developed to enable final pixel chips of different sizes to be designed, verified and tested to handle extreme hit rates of 3 GHz/cm2 (up to 12 GHz per chip) together with an increased trigger rate of 1 MHz and efficient readout of up to 5.12 Gbits/s per pixel chip. Tolerance to an extremely hostile radiation environment with 1 Grad over 10 years and induced SEU (Single Event Upset) rates of up to 100 upsets per second per chip have been major challenges to make reliable pixel chips. Three generations of pixel chips, and many specific mixed signal building blocks and radiation test chips, have been submitted and extensively tested to get to final production chips. The large, complex and high rate pixel chips have been developed with a strong emphasis on low power consumption together with a concurrent development and qualification of novel serial powering at chip, module and system level, to minimize detector material budget.

Alimonti, G↗
DOE OSTI2025

Testing the limits of ITkPixV2: the ATLAS inner tracker pixel detector readout chip

The ITkPixV2 chip is the final production readout chip for the ATLAS Phase 2 Inner Tracker (ITk) upgrade at the upcoming High-Luminosity LHC (HL-LHC). Due to the extraordinarily high peak luminosity at the HL-LHC of 5 × 1034 cm-1 s-1, ITkPixV2 must meet significant increases in nearly all design requirements compared to the current ATLAS Inner Detector (ID), including a 10× increase in trigger rate, a 7.5× increase in hit rate, a 3× increase in radiation tolerance, and a 12.5× decrease in pixel current draw per unit area, all while maintaining a similar power per unit area as present pixel detectors. Here we present the first measurements of the ITkPixV2 chip operated at the limits of the full chip design requirements, including in particular a measurement of the activity-induced current of the chip as a function of increasing hit rate.

Le Pottier, L↗
DOE OSTI2025

Anode sensitivity calibration of photomultiplier tubes used as a readout of the ELOSS detector

We present and discuss the methodology and results for an anode sensitivity calibration of Photomultiplier Tubes (PMTs) that serve as the optical readout of the Energy Loss Optical Scintillation System (ELOSS). The ELOSS detector, under development at the Facility for Rare Isotope Beams (FRIB), is a gaseous Xe scintillation-based detector designed to identify the atomic number (Z) of nuclear reaction fragments by energy-loss measurement. Variation in the anode sensitivity from tube to tube of commercially available PMTs limits ELOSS from reaching its ultimate Z resolution. A methodical approach to calibrating PMT anode sensitivities to a single target value by systematic PMT gain corrections is presented. Although the calibration process is discussed in terms of its impact on ELOSS performance, the presented method is applicable to any optical detector system composed of a large number of PMTs needing anode sensitivity calibration.

Instrumentation for heavy-ion accelerators↗
DOE OSTI2014

Fiber-optic links based on silicon photonics for high-speed readout of trackers

We propose to use silicon photonics technology to build radiation-hard fiber-optic links for high-bandwidth readout of tracking detectors. The CMOS integrated silicon photonics was developed by Luxtera and commercialized by Molex. The commercial off-the-shelf (COTS) fiber-optic links feature moderate radiation tolerance insufficient for trackers. A transceiver contains four RX and four TX channels operating at 10 Gbps each. The next generation will likely operate at 25 Gbps per channel. The approach uses a standard CMOS process and single-mode fibers, providing low power consumption and good scalability and reliability.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

Engineering, Control, and Longitudinal Readout of Floquet Qubits

We discuss how properties of time-periodic Hamiltonians can be exploited to increase the dephasing time of qubits and to design protected one- and two-qubit gates. Recently, Huang et al. [Phys. Rev. Applied 15, 034065 (2021)] have shown that Floquet states offer a manifold of working points with dynamical protection larger than the few, usual, static sweet spots. Here, we show how Floquet theory, often used on systems with a single drive tone, can be used to describe approaches to robustly control Floquet qubits in the presence of multiple commensurate drive tones. Using this formulation, we introduce a longitudinal readout protocol to measure the Floquet qubit without the need of first adiabatically mapping the Floquet states back to the static qubit states, resulting in a significant speedup in the measurement time of the Floquet qubit. The analytical approach developed here can be applied to any Hamiltonian involving a small number of distinct drive tones, typical in the study of standard parametric gates for qubits outside of the rotating-wave approximation.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2018

Dual-readout calorimetry

In the past 20 years, dual-readout calorimetry has emerged as a technique for measuring the properties of high-energy hadrons and hadron jets that offers considerable advantages compared with the instruments that are currently used for this purpose in experiments at the high-energy frontier. The status of this experimental technique and the challenges faced for its further development are reviewed.

47 OTHER INSTRUMENTATION↗
DOE OSTI2016

Submillisecond X-ray photon correlation spectroscopy from a pixel array detector with fast dual gating and no readout dead-time

Small-angle scattering X-ray photon correlation spectroscopy (XPCS) studies were performed using a novel photon-counting pixel array detector with dual counters for each pixel. Each counter can be read out independently from the other to ensure there is no readout dead-time between the neighboring frames. A maximum frame rate of 11.8 kHz was achieved. Results on test samples show good agreement with simple diffusion. Lastly, the potential of extending the time resolution of XPCS beyond the limit set by the detector frame rate using dual counters is also discussed.

43 PARTICLE ACCELERATORS↗
DOE OSTI2017

A Novel Charge Sensitive Pre-Amplifier Structure for Biological Temperature Readout Applications

Charge sensitive pre-amplifier architectures have been studied for decades for various applications, most of which adopt a gain stage with capacitor feedback to integrate the signal and a reset path to provide DC bias. For the biological temperature readout front-end, we propose a novel structure without the gain stage, which implies a strong potential for fully integrated high frequency applications. The proposed design provides 0.94 mV/pC with high conversion linearity while consuming only 1.4 micro watts of power with buffer under a 1.2-V supply rail. The prototype occupying a chip area of 0.038 square millimeter is fabricated in 130 nm standard CMOS process.

Wang, Hangfeng↗
DOE OSTI2013

A Pixel Readout Chip in 40 nm CMOS Process for High Count Rate Imaging Systems with Minimization of Charge Sharing Effects

We present a prototype chip in 40 nm CMOS technology for readout of hybrid pixel detector. The prototype chip has a matrix of 18x24 pixels with a pixel pitch of 100 μm. It can operate both in single photon counting (SPC) mode and in C8P1 mode. In SPC the measured ENC is 84 e ₋ rms (for the peaking time of 48 ns), while the effective offset spread is below 2 mV rms. In the C8P1 mode the chip reconstructs full charge deposited in the detector, even in the case of charge sharing, and it identifies a pixel with the largest charge deposition. The chip architecture and preliminary measurements are reported.

Rad Hard Vertex Detector↗
DOE OSTI2025

A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.

DAQ↗
DOE OSTI2022

FALCON readout channel for X-ray ptychography applications

This work reports the current state of the development of a pixelated readout for nanometer resolution X-ray ptychography applications. A very dense, low-noise and low-power pixel developed in a commercial 65nm CMOS technology is envisioned for such applications, targeting a pixel area of 150 μm × 150 μm, an overall noise of 200e- rms and a power consumption of 150μW per pixel. In the paper, an introduction to the application and an overview of the experimental setup are given, the designed frontend channel is reported and revised in its components and simulation results of the schematic-level design are shown and discussed.

Lazzaroni, Paolo↗
DOE OSTI2026

Comparing Thermal Neutron Scintillators for Use With SiPM-Readout Detectors

Scintillator-based thermal neutron detectors for scientific scattering facilities offer an effective combination of large-area coverage and good spatial resolution. At Oak Ridge National Laboratory, silicon photomultiplier (SiPM)-readout Anger cameras using 6 Li glass scintillators have been developed, but the spatial resolution of these detectors is limited by the relatively low light yield of the glass. Recently, several brighter scintillator compositions with sufficient 6 Li concentration have emerged as promising candidates for higher-resolution imaging. Here, in this work, we evaluate five scintillator materials: GS20, LiF/ZnS:Ag, LiF/ZnO:Zn, LiI:Eu, and Cs 2 LiYCl 6 :Ce, each mounted on a SiPM Anger camera. For each scintillator, the neutron detection efficiency, spatial resolution, and count rate capabilities were measured and compared. Each of the new compositions achieved a spatial resolution better than 0.5 mm, compared to 0.66 mm for GS20, with LiI:Eu reaching the best value of 0.32 mm. Although these compositions improve the spatial resolution of the Anger camera, their longer pulse decay times limit their use in high count rate applications, and the camera’s hardware must be optimized for the different properties of the new scintillators.

Neutron detectors↗
DOE OSTI2021

Development of FD-SOI cryogenic amplifier for application to STJ readout in COBAND project

The COBAND is a project of an experimental search for the cosmic background neutrino decay [1] – [9] . The existence of the cosmic background neutrino is predicted as a relic of the big bang in the theoretical cosmology. Since the neutrino is found to have mass generations and mixing between them, a heavier neutrino is possible to decay to a lighter neutrino with a far-infrared photon, even though its lifetime is expected to be much longer than the age of the universe [10] . However, neither the cosmic background neutrino nor the neutrino decay is yet established experimentally. Only a lower limit in the order of 10 12 years is given on the heaviest neutrino lifetime. We, thus, search for photons which come from the cosmic background neutrino decays. The photons from the cosmic background neutrino decays are expected to shape a spectrum of a unique signature with a sharp edge at a wavelength of around 50μm depending on the heaviest neutrino mass. To identify the signature against the overwhelming zodiacal emission foreground as well as the cosmic infrared background, the photodetectors are required to have an ability to measure the FIR spectrum around 50pm with sufficient precision. Thus, we aim at developing a photodetector with capability of FIR photon-by-photon spectrometry. We employ superconducting tunnel junction (STJ) sensors in combination with cryogenic amplifiers for signal readout to maximize the potential of STJ.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗