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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 271 records · Page 15
All sourcesNASA NTRSDOE OSTI
NASA NTRS2007

Filling the Assurance Gap on Complex Electronics

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled by software, such as communication protocols. For example, the James Webb Space Telescope will use Field Programmable Gate Arrays (FPGAs), which can have over a million logic gates, to send telemetry. System-on-chip (SoC) devices, another type of complex electronics, can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, mature software methodologies have been proposed, with slight modifications, to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and bugs can be detected earlier in the development cycle, thus creating a development process for CE that can be easily maintained and configurable based on the device used.

Plastow, Richard A.↗
DOE OSTI2015

Reversible migration of silver on memorized pathways in Ag-Ge{sub 40}S{sub 60} films

Reversible and reproducible formation and dissolution of silver conductive filaments are studied in Ag-photodoped thin-film Ge{sub 40}S{sub 60} subjected to electric fields. A tip-planar geometry is employed, where a conductive-atomic-force microscopy tip is the tip electrode and a silver patch is the planar electrode. We highlight an inherent “memory” effect in the amorphous chalcogenide solid-state electrolyte, in which particular silver-ion migration pathways are preserved “memorized” during writing and erasing cycles. The “memorized” pathways reflect structural changes in the photodoped chalcogenide film. Structural changes due to silver photodoping, and electrically-induced structural changes arising from silver migration, are elucidated using Raman spectroscopy. Conductive filament formation, dissolution, and electron (reduction) efficiency in a lateral device geometry are related to operation of the nano-ionic Programmable Metallization Cell memory and to newly emerging chalcogenide-based lateral geometry MEMS technologies. The methods in this work can also be used for qualitative multi-parameter sampling of metal/amorphous-chalcogenide combinations, characterizing the growth/dissolution rates, retention and endurance of fractal conductive filaments, with the aim of optimizing devices.

36 MATERIALS SCIENCE↗
DOE OSTI2019

The JET upgraded toroidal Alfvén Eigenmode Diagnostic System

The Alfvén Eigenmode Active Diagnostic system (AEAD) has undergone a major upgrade and redesign to provide a state-of-the-art excitation and real-time detection system for JET. The new system consists of individual 4 kW amplifiers allowing for increased current, separate excitation and real time control of relative phasing between antenna currents. The amplifiers have a frequency range of 10–1000 kHz, divided into various frequency bands by external matching filters. Due to the varying transmission line impedance throughout the frequency range, the amplifiers were designed with a very high resilience to reflected power. The existing amplifier control electronics have been replaced with a digital control system incorporating a National Instruments platform and Field Programmable Gate Array (FPGA) modules for frequency, gain and phase control with a frequency and phase resolution of less than 1 kHz and 1 degree respectively. Complementing the digital control system is the Protection and Control System, which utilizes Field Programmable Analog Arrays (FPAAs) and an array of electronic devices to monitor and control the AEAD. New capabilities such as independent antenna current/phase control, allow for improved excitation control, better definition of antenna spectrum combined with enhanced system reliability. This paper will review the new AEAD system, its unique capabilities and improvements over the previous diagnostic system.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2018

A programmable two-qubit quantum processor in silicon

Now that it is possible to achieve measurement and control fidelities for individual quantum bits (qubits) above the threshold for fault tolerance, attention is moving towards the difficult task of scaling up the number of physical qubits to the large numbers that are needed for fault-tolerant quantum computing (1,2). In this context, quantum-dot-based spin qubits could have substantial advantages over other types of qubit owing to their potential for all-electrical operation and ability to be integrated at high density onto an industrial platform (3,4,5). Initialization, readout and single- and two-qubit gates have been demonstrated in various quantum-dot-based qubit representations (6,7,8,9). However, as seen with small-scale demonstrations of quantum computers using other types of qubit (10,11,12,13), combining these elements leads to challenges related to qubit crosstalk, state leakage, calibration and control hardware. We overcome these challenges by using carefully designed control techniques to demonstrate a programmable two-qubit quantum processor in a silicon device that can perform the Deutsch–Josza algorithm and the Grover search algorithm—canonical examples of quantum algorithms that outperform their classical analogues. We characterize the entanglement in our processor by using quantum-state tomography of Bell states, measuring state fidelities of 85–89 per cent and concurrences of 73–82 per cent. These results pave the way for larger-scale quantum computers that use spins confined to quantum dots.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2017

Plasma–wall interaction studies within the EUROfusion consortium: progress on plasma-facing components development and qualification

The provision of a particle and power exhaust solution which is compatible with first-wall components and edge-plasma conditions is a key area of present-day fusion research and mandatory for a successful operation of ITER and DEMO. The work package plasma-facing components (WP PFC) within the European fusion programme complements with laboratory experiments, i.e. in linear plasma devices, electron and ion beam loading facilities, the studies performed in toroidally confined magnetic devices, such as JET, ASDEX Upgrade, WEST etc. The connection of both groups is done via common physics and engineering studies, including the qualification and specification of plasma-facing components, and by modelling codes that simulate edge-plasma conditions and the plasma–material interaction as well as the study of fundamental processes. WP PFC addresses these critical points in order to ensure reliable and efficient use of conventional, solid PFCs in ITER (Be and W) and DEMO (W and steel) with respect to heat-load capabilities (transient and steady-state heat and particle loads), lifetime estimates (erosion, material mixing and surface morphology), and safety aspects (fuel retention, fuel removal, material migration and dust formation) particularly for quasi-steady-state conditions. Alternative scenarios and concepts (liquid Sn or Li as PFCs) for DEMO are developed and tested in the event that the conventional solution turns out to not be functional. Here, we present an overview of the activities with an emphasis on a few key results: (i) the observed synergistic effects in particle and heat loading of ITER-grade W with the available set of exposition devices on material properties such as roughness, ductility and microstructure; (ii) the progress in understanding of fuel retention, diffusion and outgassing in different W-based materials, including the impact of damage and impurities like N; and (iii), the preferential sputtering of Fe in EUROFER steel providing an in situ W surface and a potential first-wall solution for DEMO.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
DOE OSTI2013

Ant Colony Optimization for Mapping, Scheduling and Placing in Reconfigurable Systems

Modern heterogeneous embedded platforms, com- posed of several digital signal, application specific and general purpose processors, also include reconfigurable devices support- ing partial dynamic reconfiguration. These devices can change the behavior of some of their parts during execution, allowing hardware acceleration of more sections of the applications. Never- theless, partial dynamic reconfiguration imposes severe overheads in terms of latency. For such systems, a critical part of the design phase is deciding on which processing elements (mapping) and when (scheduling) executing a task, but also how to place them on the reconfigurable device to guarantee the most efficient reuse of the programmable logic. In this paper we propose an algorithm based on Ant Colony Optimization (ACO) that simultaneously executes the scheduling, the mapping and the linear placing of tasks, hiding reconfiguration overheads through prefetching. Our heuristic gradually constructs solutions and then searches around the best ones, cutting out non-promising areas of the design space. We show how to consider the partial dynamic reconfiguration constraints in the scheduling, placing and mapping problems and compare our formulation to other heuristics that address the same problems. We demonstrate that our proposal is more general and robust, and finds better solutions (16.5% in average) with respect to competing solutions.

Ant Colony Optimization↗
DOE OSTI2020

Measuring Cities with Software-Defined Sensors

The Chicago Array of Things (AoT) project, funded by the US National Science Foundation, created an experimental, urban-scale measurement capability to support diverse scientific studies. Initially conceived as a traditional sensor network, collaborations with many science communities guided the project to design a system that is remotely programmable to implement Artificial Intelligence (AI) within the devices-at the “edge” of the network-as a means for measuring urban factors that heretofore had only been possible with human observers, such as human behavior including social interaction. The concept of “software-defined sensors” emerged from these design discussions, opening new possibilities, such as stronger privacy protections and autonomous, adaptive measurements triggered by events or conditions. We provide examples of current and planned social and behavioral science investigations uniquely enabled by software-defined sensors as part of the SAGE project, an expanded follow-on effort that includes AoT.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1987

Implementation of a robotic flexible assembly system

As part of the Intelligent Task Automation program, a team developed enabling technologies for programmable, sensory controlled manipulation in unstructured environments. These technologies include 2-D/3-D vision sensing and understanding, force sensing and high speed force control, 2.5-D vision alignment and control, and multiple processor architectures. The subsequent design of a flexible, programmable, sensor controlled robotic assembly system for small electromechanical devices is described using these technologies and ongoing implementation and integration efforts. Using vision, the system picks parts dumped randomly in a tray. Using vision and force control, it performs high speed part mating, in-process monitoring/verification of expected results and autonomous recovery from some errors. It is programmed off line with semiautomatic action planning.

Benton, Ronald C.↗
NASA NTRS2001

Microshutter Arrays for the NGST NIRSpec

We are developing a programmable multiobject field selector for the NGST NIRSpec. This device is a microshutter array, a close-packed 2000 x 2000 array of 100 micrometer x 100 micrometer shutters fabricated with Micro-ElectroMechanical Systems (MEMS) technologies. The shutters are opened using a magnet scanned over the array. The shutters are held open by electrostatic potentials on adjacent vertical electrodes. Modeling of the magnetic actuation of the microshutters allowed optimization of the magnetic field configuration, the distance between magnet and shutters, and the force and torque produced by the magnet. The results of laboratory tests are consistent with our modeling. We have demonstrated actuation, latching and addressing. We are able to rotate shutters out of the plane up to 90 degree and more, to latch them electrostatically to the walls and release them selectively. During the last six month all critical elements of the array have been demonstrated. Fabrication processes were developed to deposit vertical electrodes on support grid side walls and insulated light-shields that block the gaps between shutters and the support grid. Physical optics analysis was performed to assess the expected optical performance of the microshutters. A preliminary Fourier optics analysis on the microshutter array performance has been carried out. More detailed analysis of wave propagation through 3D structures is a next step. An optical test station for verifying optical parameters of the shutter array at room temperature has been developed. It allows to measure parameters, such as transmission, scattering, contrast ratio, and diffraction of the array structure. Initial data have been acquired and are being analyzed and compared to theoretical predictions.

Moseley, Harvey↗
NASA NTRS2007

Risk Reduction for Use of Complex Devices in Space Projects

We present guidel!nes to reduce risk to an acceptable level when using complex devices in space applications. Application to Virtex 4 Field Programmable Gate Array (FPGA) on Express Logistic Carrier (ELC) project is presented.

Berg, Melanie↗
NASA NTRS2009

Digital Beamforming Scatterometer

This paper discusses scatterometer measurements collected with multi-mode Digital Beamforming Synthetic Aperture Radar (DBSAR) during the SMAP-VEX 2008 campaign. The 2008 SMAP Validation Experiment was conducted to address a number of specific questions related to the soil moisture retrieval algorithms. SMAP-VEX 2008 consisted on a series of aircraft-based.flights conducted on the Eastern Shore of Maryland and Delaware in the fall of 2008. Several other instruments participated in the campaign including the Passive Active L-Band System (PALS), the Marshall Airborne Polarimetric Imaging Radiometer (MAPIR), and the Global Positioning System Reflectometer (GPSR). This campaign was the first SMAP Validation Experiment. DBSAR is a multimode radar system developed at NASA/Goddard Space Flight Center that combines state-of-the-art radar technologies, on-board processing, and advances in signal processing techniques in order to enable new remote sensing capabilities applicable to Earth science and planetary applications [l]. The instrument can be configured to operate in scatterometer, Synthetic Aperture Radar (SAR), or altimeter mode. The system builds upon the L-band Imaging Scatterometer (LIS) developed as part of the RadSTAR program. The radar is a phased array system designed to fly on the NASA P3 aircraft. The instrument consists of a programmable waveform generator, eight transmit/receive (T/R) channels, a microstrip antenna, and a reconfigurable data acquisition and processor system. Each transmit channel incorporates a digital attenuator, and digital phase shifter that enables amplitude and phase modulation on transmit. The attenuators, phase shifters, and calibration switches are digitally controlled by the radar control card (RCC) on a pulse by pulse basis. The antenna is a corporate fed microstrip patch-array centered at 1.26 GHz with a 20 MHz bandwidth. Although only one feed is used with the present configuration, a provision was made for separate corporate feeds for vertical and horizontal polarization. System upgrades to dual polarization are currently under way. The DBSAR processor is a reconfigurable data acquisition and processor system capable of real-time, high-speed data processing. DBSAR uses an FPGA-based architecture to implement digitally down-conversion, in-phase and quadrature (I/Q) demodulation, and subsequent radar specific algorithms. The core of the processor board consists of an analog-to-digital (AID) section, three Altera Stratix field programmable gate arrays (FPGAs), an ARM microcontroller, several memory devices, and an Ethernet interface. The processor also interfaces with a navigation board consisting of a GPS and a MEMS gyro. The processor has been configured to operate in scatterometer, Synthetic Aperture Radar (SAR), and altimeter modes. All the modes are based on digital beamforming which is a digital process that generates the far-field beam patterns at various scan angles from voltages sampled in the antenna array. This technique allows steering the received beam and controlling its beam-width and side-lobe. Several beamforming techniques can be implemented each characterized by unique strengths and weaknesses, and each applicable to different measurement scenarios. In Scatterometer mode, the radar is capable to.generate a wide beam or scan a narrow beam on transmit, and to steer the received beam on processing while controlling its beamwidth and side-lobe level. Table I lists some important radar characteristics

Rincon, Rafael F.↗
NASA NTRS2024

Single-Event Effects Test Report Lattice Semiconductor, LCMXO3D-9400HC-5BG484I Field Programmable Gate Array

The purpose of this test was to characterize single event effects (SEE) in the LCMXO3D-9400HC-5BG484I, a low power and low density field programmable gate array (FPGA). The SEE concerns for the device that were investigated in this testing are single event upsets (SEUs) in the configuration static random-access memory (SRAM), SEUs in the FPGA fabric, single event latch up (SEL), and single event functional interrupts (SEFIs). Testing was conducted at Lawrence Berkeley National Laboratory (LBNL) on August 26th, 2024 and August 28th, 2024.

Adia M Wood↗
DOE OSTI2016

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2015

Virtex-5QV Self Scrubber

This HDL code (hereafter referred to as "software") implements circuitry in Xilinx Virtex-5QV Field Programmable Gate Array (FPGA) hardware. This software allows the device to self-check the consistency of its own configuration memory for radiation-induced errors. The software then provides the capability to correct any single-bit errors detected in the memory using the device's inherent circuitry, or reload corrupted memory frames when larger errors occur that cannot be corrected with the device's built-in error correction and detection scheme.

Wojahn, Christopher K.↗
DOE OSTI2019

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

42 ENGINEERING↗
DOE OSTI2021

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Asaad, Sameh W.↗
NASA NTRS1993

Programmable DMA controller

In a data system having a memory, plural input/output (I/O) devices and a bus connecting each of the I/O devices to the memory, a direct memory access (DMA) controller regulating access of each of the I/O devices to the bus, including a priority register storing priorities of bus access requests from the I/O devices, an interrupt register storing bus access requests of the I/O devices, a resolver for selecting one of the I/O devices to have access to the bus, a pointer register storing addresses of locations in the memory for communication with the one I/O device via the bus, a sequence register storing an address of a location in the memory containing a channel program instruction which is to be executed next, an ALU for incrementing and decrementing addresses stored in the pointer register, computing the next address to be stored in the sequence register, computing an initial contents of each of the register. The memory contains a sequence of channel program instructions defining a set up operation wherein the contents of each of the registers in the channel register is initialized in accordance with the initial contents computed by the ALU and an access operation wherein data is transferred on the bus between a location in the memory whose address is currently stored in the pointer register and the one I/O device enabled by the resolver.

Hendry, David F.↗
DOE OSTI2022

KokkACC: Enhancing Kokkos with OpenACC

Template metaprogramming is gaining popularity as a high-level solution for achieving performance portability on heterogeneous computing resources. Kokkos is a representative approach that offers programmers high-level abstractions for generic programming while most of the device-specific code generation and optimizations are delegated to the compiler through template specializations. For this, Kokkos provides a set of device-specific code specializations in multiple back ends, such as CUDA and HIP. Unlike CUDA or HIP, OpenACC is a high-level and directive-based programming model. This descriptive model allows developers to insert hints (pragmas) into their code that help the compiler to parallelize the code. The compiler is responsible for the transformation of the code, which is completely transparent to the programmer. This paper presents an OpenACC back end for Kokkos: KokkACC. As an alternative to Kokkos’s existing device-specific back ends, KokkACC is a multi-architecture back end providing a high-productivity programming environment enabled by OpenACC’s high-level and descriptive programming model. Moreover, we have observed competitive performance; in some cases, KokkACC is faster (up to 9×) than NVIDIA’s CUDA back end and much faster than OpenMP’s GPU offloading back end. This work also includes implementation details and a detailed performance study conducted with a set of mini-benchmarks (AXPY and DOT product) and three mini-apps (LULESH, miniFE and SNAP, a LAMMPS proxy mini-app).

Valero Lara, Pedro↗